OSDN Git Service
Craig Topper [Mon, 29 Apr 2019 06:13:41 +0000 (06:13 +0000)]
[X86] Remove some intel syntax aliases on (v)cvtpd2(u)dq, (v)cvtpd2ps, (v)cvt(u)qq2ps. Add 'x' and'y' suffix aliases to masked version of the same in att syntax.
The 128/256 bit version of these instructions require an 'x' or 'y' suffix to
disambiguate the memory form in att syntax.
We were allowing the same suffix in intel syntax, but it appears gas does not
do that.
gas does allow the 'x' and 'y' suffix on register and broadcast forms even
though its not needed. We were allowing it on unmasked register form, but not on
masked versions or on masked or unmasked broadcast form.
While there fix some test coverage holes so they can be extended with the 'x'
and 'y' suffix tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359418
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Mon, 29 Apr 2019 06:03:59 +0000 (06:03 +0000)]
[llvm-nm] -print-size => --print-size
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359417
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Mon, 29 Apr 2019 05:38:22 +0000 (05:38 +0000)]
[llvm-nm] Simplify and fix a buffer overflow
* char SymbolAddrStr[18] can't hold "%" PRIo64 which may need 22 characters.
* Use range-based for
* Delete unnecessary typedef
* format(...).print(Str, sizeof(Str)) + outs() << Str => outs() << format(...)
* Use cascading outs() << .. << ..
* Use iterator_range(Container &&c)
* (A & B) == B => A & B if B is a power of 2
* replace null sentinel in constants with makeArrayRef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359416
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Mon, 29 Apr 2019 00:51:41 +0000 (00:51 +0000)]
llvm-cvtres: Attempt to make llvm-cvtres/duplicate.test work on big-endian systems
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359414
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 28 Apr 2019 21:04:47 +0000 (21:04 +0000)]
[X86] Add PR39921 HADD pairwise reduction test and AVX2 test coverage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359409
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 28 Apr 2019 20:04:08 +0000 (20:04 +0000)]
[X86][AVX] Add fast-hops target for add/fadd reduction tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359408
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 28 Apr 2019 20:03:11 +0000 (20:03 +0000)]
[X86] Add PR39936 HADD Tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359407
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 28 Apr 2019 19:12:58 +0000 (19:12 +0000)]
[X86][SSE] combineExtractVectorElt - add early-out to return zero/undef for out-of-range extraction indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359406
91177308-0d34-0410-b5e6-
96231b3b80d8
Nikita Popov [Sun, 28 Apr 2019 15:40:56 +0000 (15:40 +0000)]
[ConstantRange] Add makeExactNoWrapRegion()
I got confused on the terminology, and the change in D60598 was not
correct. I was thinking of "exact" in terms of the result being
non-approximate. However, the relevant distinction here is whether
the result is
* Largest range such that:
Forall Y in Other: Forall X in Result: X BinOp Y does not wrap.
(makeGuaranteedNoWrapRegion)
* Smallest range such that:
Forall Y in Other: Forall X not in Result: X BinOp Y wraps.
(A hypothetical makeAllowedNoWrapRegion)
* Both. (makeExactNoWrapRegion)
I'm adding a separate makeExactNoWrapRegion method accepting a
single APInt (same as makeExactICmpRegion) and using it in the
places where the guarantee is relevant.
Differential Revision: https://reviews.llvm.org/D60960
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359402
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 28 Apr 2019 15:04:30 +0000 (15:04 +0000)]
[X86][AVX] Enabled AVX512F tests and add PR40815 test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359401
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 28 Apr 2019 14:31:01 +0000 (14:31 +0000)]
[X86][AVX] Combine non-lane crossing binary shuffles using X86ISD::VPERMV3
Some of the combines might be further improved if we lower more shuffles with X86ISD::VPERMV3 directly, instead of waiting to combine the results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359400
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sun, 28 Apr 2019 13:19:29 +0000 (13:19 +0000)]
[SelectionDAG] include FP min/max variants as binary operators
The x86 test diffs don't look great because of extra move ops,
but FP min/max should clearly be included in the list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359399
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sun, 28 Apr 2019 12:23:43 +0000 (12:23 +0000)]
[DAGCombiner] try repeated fdiv divisor transform before building estimate
This was originally part of D61028, but it's an independent diff.
If we try the repeated divisor reciprocal transform before producing an estimate sequence,
then we have an opportunity to use scalar fdiv. On x86, the trade-off is 1 divss vs. 5
vector FP ops in the default estimate sequence. On recent chips (Skylake, Ryzen), the
full-precision division is only 3 cycle throughput, so that's probably the better perf
default option and avoids problems from x86's inaccurate estimates.
The last 2 tests show that users still have the option to override the defaults by using
the function attributes for reciprocal estimates, but those patterns are potentially made
faster by converting the vector ops (including ymm ops) to scalar math.
Differential Revision: https://reviews.llvm.org/D61149
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359398
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Sun, 28 Apr 2019 10:54:45 +0000 (10:54 +0000)]
[MCA] Fix typo in AVX2 gather tests. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359397
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 28 Apr 2019 10:46:17 +0000 (10:46 +0000)]
[X86][SSE] Optimize llvm.experimental.vector.reduce.xor.vXi1 parity reduction (PR38840)
An xor reduction of a bool vector can be optimized to a parity check of the MOVMSK/BITCAST'd integer - if the population count is odd return 1, else return 0.
Differential Revision: https://reviews.llvm.org/D61230
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359396
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 28 Apr 2019 10:02:34 +0000 (10:02 +0000)]
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359395
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 28 Apr 2019 06:25:33 +0000 (06:25 +0000)]
[X86] Remove (V)MOV64toSDrr/m and (V)MOVDI2SSrr/m. Use 128-bit result MOVD/MOVQ and COPY_TO_REGCLASS instead
Summary:
The register form of these instructions are CodeGenOnly instructions that cover
GR32->FR32 and GR64->FR64 bitcasts. There is a similar set of instructions for
the opposite bitcast. Due to the patterns using bitcasts these instructions get
marked as "bitcast" machine instructions as well. The peephole pass is able to
look through these as well as other copies to try to avoid register bank copies.
Because FR32/FR64/VR128 are all coalescable to each other we can end up in a
situation where a GR32->FR32->VR128->FR64->GR64 sequence can be reduced to
GR32->GR64 which the copyPhysReg code can't handle.
To prevent this, this patch removes one set of the 'bitcast' instructions. So
now we can only go GR32->VR128->FR32 or GR64->VR128->FR64. The instruction that
converts from GR32/GR64->VR128 has no special significance to the peephole pass
and won't be looked through.
I guess the other option would be to add support to copyPhysReg to just promote
the GR32->GR64 to a GR64->GR64 copy. The upper bits were basically undefined
anyway. But removing the CodeGenOnly instruction in favor of one that won't be
optimized seemed safer.
I deleted the peephole test because it couldn't be made to work with the bitcast
instructions removed.
The load version of the instructions were unnecessary as the pattern that selects
them contains a bitcasted load which should never happen.
Fixes PR41619.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61223
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359392
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 27 Apr 2019 20:44:08 +0000 (20:44 +0000)]
Revert rL359389: [X86][SSE] Add support for <64 x i1> bool reduction
Minor generalization of the existing <32 x i1> pre-AVX2 split code.
........
Causing irregular buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359391
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 27 Apr 2019 20:20:02 +0000 (20:20 +0000)]
[X86][AVX] Add additional SSE/AVX expandload and compressstore targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359390
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 27 Apr 2019 20:04:44 +0000 (20:04 +0000)]
[X86][SSE] Add support for <64 x i1> bool reduction
Minor generalization of the existing <32 x i1> pre-AVX2 split code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359389
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 27 Apr 2019 19:57:34 +0000 (19:57 +0000)]
[X86][AVX] Cleanup and add additional expandload and compressstore tests
sort order by types and add vXi32/vXi16/vXi8 test coverage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359388
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 27 Apr 2019 17:32:46 +0000 (17:32 +0000)]
[X86][AVX512] Improve vector bool reductions
As predicate masks are legal on AVX512 targets, we avoid MOVMSK in these cases, but we can just bitcast the bool vector to the integer equivalent directly - avoiding expansion of the reduction to a shuffle pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359386
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 27 Apr 2019 16:49:54 +0000 (16:49 +0000)]
[X86] Add vector boolean reduction tests (PR38840)
AND/OR/XOR tests for the @llvm.experimental.vector.reduce intrinsics
AND/OR are pretty good (pre-AVX512), XOR (not so common but used for parity reduction) is still pretty bad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359385
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Sat, 27 Apr 2019 16:13:53 +0000 (16:13 +0000)]
[lli] Fix a typo in a cl::opt description.
Patch by Wasiher. Thanks Wasiher!
Differential Revision: https://reviews.llvm.org/D61135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359384
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Sat, 27 Apr 2019 16:12:14 +0000 (16:12 +0000)]
[llvm-nm][llvm-readelf] Avoid single-dash -long-option in tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359383
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 27 Apr 2019 15:41:14 +0000 (15:41 +0000)]
Fix check-prefixes typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359382
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Sat, 27 Apr 2019 15:33:22 +0000 (15:33 +0000)]
[DJB] Fix variable case after D61178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359381
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Sat, 27 Apr 2019 15:32:53 +0000 (15:32 +0000)]
[llvm-nm] Support section type 'u': STB_GNU_UNIQUE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359380
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 27 Apr 2019 15:30:06 +0000 (15:30 +0000)]
[X86][SSE] Add initial test case for subvector insert/extract of illegal types
Suggested by @nikic on D59188
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359379
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 27 Apr 2019 13:35:32 +0000 (13:35 +0000)]
[X86][AVX] Merge mask select with shuffles across extract_subvector (PR40332)
Fixes PR40332 in the limited case where we're selecting between a target shuffle and a zero vector.
We can extend this in the future to handle more opcodes and non-zero selections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359378
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Sat, 27 Apr 2019 11:59:11 +0000 (11:59 +0000)]
[MCA] Add field `IsEliminated` to class Instruction. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359377
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Atanasyan [Sat, 27 Apr 2019 09:28:54 +0000 (09:28 +0000)]
[cmake] Disable a GCC optimization when building LLVM for MIPS
GCC when compiling LLVM for MIPS can introduce a jump to an uninitialized
value when shrink wrapping is enabled. As shrink wrapping is enabled in
GCC at all optimization levels, it must be disabled. This bug exists for
all versions of GCC since 4.9.2.
This partially resolves PR37701 / GCC PR target/86069.
Patch by Simon Dardis.
Differential Revision: https://reviews.llvm.org/D48069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359376
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 27 Apr 2019 03:38:15 +0000 (03:38 +0000)]
[X86] Use MOVQ for i64 atomic_stores when SSE2 is enabled
Summary: If we have SSE2 we can use a MOVQ to store 64-bits and avoid falling back to a cmpxchg8b loop. If its a seq_cst store we need to insert an mfence after the store.
Reviewers: spatel, RKSimon, reames, jfb, efriedma
Reviewed By: RKSimon
Subscribers: hiraditya, dexonsmith, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60546
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359368
91177308-0d34-0410-b5e6-
96231b3b80d8
Mark Searles [Sat, 27 Apr 2019 00:51:18 +0000 (00:51 +0000)]
Revert "AMDGPU: Split block for si_end_cf"
This reverts commit
7a6ef3004655dd86d722199c471ae78c28e31bb4.
We discovered some internal test failures, so reverting for now.
Differential Revision: https://reviews.llvm.org/D61213
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359363
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Fri, 26 Apr 2019 23:16:16 +0000 (23:16 +0000)]
[AMDGPU] gfx1010 VOPC implementation
Differential Revision: https://reviews.llvm.org/D61208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359358
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Fri, 26 Apr 2019 22:58:39 +0000 (22:58 +0000)]
[ORC] Add a 'plugin' interface to ObjectLinkingLayer for events/configuration.
ObjectLinkingLayer::Plugin provides event notifications when objects are loaded,
emitted, and removed. It also provides a modifyPassConfig callback that allows
plugins to modify the JITLink pass configuration.
This patch moves eh-frame registration into its own plugin, and teaches
llvm-jitlink to only add that plugin when performing execution runs on
non-Windows platforms. This should allow us to re-enable the test case that was
removed in r359198.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359357
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Fri, 26 Apr 2019 21:53:13 +0000 (21:53 +0000)]
[GlobalISel][AArch64] Use getConstantVRegValWithLookThrough for extracts
getConstantVRegValWithLookThrough does the same thing as the
getConstantValueForReg function, and has more visibility across GISel. Plus, it
supports looking through G_TRUNC, G_SEXT, and G_ZEXT. So, we get better code
reuse and more functionality for free by using it.
Add some test cases to select-extract-vector-elt.mir to show that we can now
look through those instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359351
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Desaulniers [Fri, 26 Apr 2019 18:45:04 +0000 (18:45 +0000)]
[AsmPrinter] refactor to support %c w/ GlobalAddress'
Summary:
Targets like ARM, MSP430, PPC, and SystemZ have complex behavior when
printing the address of a MachineOperand::MO_GlobalAddress. Move that
handling into a new overriden method in each base class. A virtual
method was added to the base class for handling the generic case.
Refactors a few subclasses to support the target independent %a, %c, and
%n.
The patch also contains small cleanups for AVRAsmPrinter and
SystemZAsmPrinter.
It seems that NVPTXTargetLowering is possibly missing some logic to
transform GlobalAddressSDNodes for
TargetLowering::LowerAsmOperandForConstraint to handle with "i" extended
inline assembly asm constraints.
Fixes:
- https://bugs.llvm.org/show_bug.cgi?id=41402
- https://github.com/ClangBuiltLinux/linux/issues/449
Reviewers: echristo, void
Reviewed By: void
Subscribers: void, craig.topper, jholewinski, dschuff, jyknight, dylanmckay, sdardis, nemanjai, javed.absar, sbc100, jgravelle-google, eraman, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, jrtc27, atanasyan, jsji, llvm-commits, kees, tpimh, nathanchance, peter.smith, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60887
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359337
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 26 Apr 2019 18:02:14 +0000 (18:02 +0000)]
[X86][AVX] Fold extract_subvector(broadcast(x)) -> broadcast(x) iff x has one use
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359332
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Fri, 26 Apr 2019 18:00:01 +0000 (18:00 +0000)]
[AArch64][GlobalISel] Select G_BSWAP for vectors of s32 and s64
There are instructions for these, so mark them as legal. Select the correct
instruction in AArch64InstructionSelector.cpp.
Update select-bswap.mir and arm64-rev.ll to reflect the changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359331
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Fri, 26 Apr 2019 17:56:03 +0000 (17:56 +0000)]
[AMDGPU] gfx1010 VOP3 and VOP3P implementation
Differential Revision: https://reviews.llvm.org/D61202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359328
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 26 Apr 2019 17:49:02 +0000 (17:49 +0000)]
[DAGCombine] Cleanup visitEXTRACT_SUBVECTOR. NFCI.
Use ArrayRef::slice, reduce some rather awkward long lines for legibility and run clang-format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359326
91177308-0d34-0410-b5e6-
96231b3b80d8
Nikita Popov [Fri, 26 Apr 2019 16:50:31 +0000 (16:50 +0000)]
[ConstantRange] Add abs() support
Add support for abs() to ConstantRange. This will allow to handle
SPF_ABS select flavor in LVI and will also come in handy as a
primitive for the srem implementation.
The implementation is slightly tricky, because a) abs of signed min
is signed min and b) sign-wrapped ranges may have an abs() that is
smaller than a full range, so we need to explicitly handle them.
Differential Revision: https://reviews.llvm.org/D61084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359321
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 26 Apr 2019 16:39:38 +0000 (16:39 +0000)]
[X86] Sink NoRegister creation for unused Base/Index registers into getAddressOperands. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359318
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 26 Apr 2019 16:39:35 +0000 (16:39 +0000)]
[X86] Segment registers should have i16 type not i32.
Probably doesn't really matter, but was inconsistent with the rest of the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359317
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Fri, 26 Apr 2019 16:37:51 +0000 (16:37 +0000)]
[AMDGPU] gfx1010 VOP2 changes
Differential Revision: https://reviews.llvm.org/D61156
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359316
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 26 Apr 2019 16:27:11 +0000 (16:27 +0000)]
[llvm-nm] Revert inadvertently committed 'i' change in r359314
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359315
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 26 Apr 2019 16:21:51 +0000 (16:21 +0000)]
[ThinLTO] Fix X86/strong_non_prevailing.ll after llvm-nm 'r' change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359314
91177308-0d34-0410-b5e6-
96231b3b80d8
Roland Froese [Fri, 26 Apr 2019 16:14:17 +0000 (16:14 +0000)]
[PowerPC] Update P9 vector costs for insert/extract element
The PPC vector cost model values for insert/extract element reflect older
processors that lacked vector insert/extract and move-to/move-from VSR
instructions. Update getVectorInstrCost to give appropriate values for when
the newer instructions are present.
Differential Revision: https://reviews.llvm.org/D60160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359313
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 26 Apr 2019 16:03:31 +0000 (16:03 +0000)]
[llvm-nm] Generalize symbol types 'N', 'n' and '?'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359312
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 26 Apr 2019 16:01:48 +0000 (16:01 +0000)]
[llvm-nm] Fix handling of symbol types 't' 'd' 'r'
In addition, fix and convert the two tests to yaml2obj based. This
allows us to delete two executables.
X86/weak.test: 'v' was not tested
X86/init-fini.test: symbol types of __bss_start _edata _end were wrong
GNU nm reports __init_array_start as 't', and __preinit_array_start as 'd'.
__init_array_start is 't' just because its section ".init_array" starts with ".init"
'd' makes more sense and allows us to drop the weird SHT_INIT_ARRAY rule.
So, change __init_array_start to 'd' instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359311
91177308-0d34-0410-b5e6-
96231b3b80d8
Don Hinton [Fri, 26 Apr 2019 15:22:21 +0000 (15:22 +0000)]
[docs] Put DefaultOption bullet in alphabetical order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359309
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 26 Apr 2019 13:42:16 +0000 (13:42 +0000)]
[llvm-nm][llvm-size] Use --double-dash options in tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359308
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 26 Apr 2019 13:41:19 +0000 (13:41 +0000)]
s/Dwarf 5/DWARF v5/ NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359307
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 26 Apr 2019 13:36:37 +0000 (13:36 +0000)]
[x86] add tests for fmin/fmax; NFC
'maximum' and 'minimum' still crash, so they are commented out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359306
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexandre Ganea [Fri, 26 Apr 2019 13:09:26 +0000 (13:09 +0000)]
Fix llvm-objcopy/ELF/preserve-segment-contents test on UTF-8 locale
Differential Revision: https://reviews.llvm.org/D61137
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359302
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Fri, 26 Apr 2019 13:09:11 +0000 (13:09 +0000)]
[yaml2obj] - Make implicitSectionNames() return std::vector<StringRef>. NFCI.
No need to use SmallVector of char* here.
This simplifies the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359301
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Fri, 26 Apr 2019 12:45:54 +0000 (12:45 +0000)]
[yaml2obj] - Remove excessive variable. NFC.
`auto &Strtab` was used only once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359300
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 26 Apr 2019 12:23:42 +0000 (12:23 +0000)]
Fix Wparentheses warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359299
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Fri, 26 Apr 2019 12:20:51 +0000 (12:20 +0000)]
[yaml2obj] - Make the code to match the LLVM style. NFCI.
This renames the variables to uppercase and
removes use of `auto` for unobvious type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359298
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Fri, 26 Apr 2019 12:15:32 +0000 (12:15 +0000)]
[yaml2elf] - Cleanup the initSectionHeaders(). NFCI.
This encapsulates the section specific code inside the
corresponding writeSectionContent methods.
Making the code a bit more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359297
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 26 Apr 2019 11:45:54 +0000 (11:45 +0000)]
[X86][SSE] Pull out OR(EXTRACTELT(X,0),OR(EXTRACTELT(X,1),...)) matching code from LowerVectorAllZeroTest
Create a matchBitOpReduction helper that checks for the pattern with any opcode.
First step towards reusing this code to recognize other scalar reduction patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359296
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Fri, 26 Apr 2019 11:44:10 +0000 (11:44 +0000)]
Minor formatting tweak, no behavior change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359295
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 26 Apr 2019 10:56:10 +0000 (10:56 +0000)]
caseFoldingDjbHash: simplify and make the US-ASCII fast path faster
The slow path (with at least one non US-ASCII) will be slower but that
doesn't matter.
Differential Revision: https://reviews.llvm.org/D61178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359294
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 26 Apr 2019 10:49:13 +0000 (10:49 +0000)]
[X86][SSE] Disable shouldFoldConstantShiftPairToMask for btver1/btver2 targets (PR40758)
As detailed on PR40758, Bobcat/Jaguar can perform vector immediate shifts on the same pipes as vector ANDs with the same latency - so it doesn't make sense to replace a shl+lshr with a shift+and pair as it requires an additional mask (with the extra constant pool, loading and register pressure costs).
Differential Revision: https://reviews.llvm.org/D61068
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359293
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 26 Apr 2019 09:56:14 +0000 (09:56 +0000)]
[X86][AVX] Combine shuffles extracted from a common vector
A small step towards combining shuffles across vector sizes - this recognizes when a shuffle's operands are all extracted from the same larger source and tries to combine to an unary shuffle of that source instead. Fixes one of the test cases from PR34380.
Differential Revision: https://reviews.llvm.org/D60512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359292
91177308-0d34-0410-b5e6-
96231b3b80d8
Sven van Haastregt [Fri, 26 Apr 2019 09:21:25 +0000 (09:21 +0000)]
[InferAddressSpaces] Add AS parameter to the pass factory
This enables the pass to be used in the absence of
TargetTransformInfo. When the argument isn't passed, the factory
defaults to UninitializedAddressSpace and the flat address space is
obtained from the TargetTransformInfo as before this change. Existing
users won't have to change.
Patch by Kevin Petit.
Differential Revision: https://reviews.llvm.org/D60602
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359290
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Fri, 26 Apr 2019 08:31:00 +0000 (08:31 +0000)]
Fix alignment in AArch64InstructionSelector::emitConstantPoolEntry()
The code was using the alignment of a pointer to the value, not the
alignment of the constant itself.
Maybe we got away with it so far because the pointer alignment is
fairly high, but we did end up under-aligning <16 x i8> vectors,
which was caught in the Chromium build after lld stopped over-aligning
the .rodata.cst16 section in r356428. (See crbug.com/953815)
Differential revision: https://reviews.llvm.org/D61124
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359287
91177308-0d34-0410-b5e6-
96231b3b80d8
Marcello Maggioni [Fri, 26 Apr 2019 07:21:56 +0000 (07:21 +0000)]
[GlobalISel] Fix inserting copies in the right position for reg definitions
When constrainRegClass is called if the constraining happens on a use the COPY
needs to be inserted before the instruction that contains the MachineOperand,
but if we are constraining a definition it actually needs to be added
after the instruction. In addition, the COPY needs to have its operands
flipped (in the use case we are copying from the old unconstrained register
to the new constrained register, while in the definition case we are copying
from the new constrained register that the instruction defines to the old
unconstrained register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359282
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 26 Apr 2019 05:56:23 +0000 (05:56 +0000)]
Fix typos: (re)?sor?uce -> (re)?source
Closes: https://github.com/llvm/llvm-project/pull/10
In-collaboration-with: Olivier Cochard-Labbé <olivier@FreeBSD.org>
Signed-off-by: Enji Cooper <yaneurabeya@gmail.com>
Differential Revision: https://reviews.llvm.org/D61021
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359277
91177308-0d34-0410-b5e6-
96231b3b80d8
Dan Robertson [Fri, 26 Apr 2019 02:55:54 +0000 (02:55 +0000)]
[NFC] Add baseline tests for int isKnownNonZero
Add baseline tests for improvements of isKnownNonZero for integer types.
Differential Revision: https://reviews.llvm.org/D60932
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359267
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 26 Apr 2019 02:10:10 +0000 (02:10 +0000)]
[llvm-objcopy] Accept --long-option but not -long-option
Summary:
llvm-{objcopy,strip} (and many other LLVM binary utilities) accept
cl::opt style -long-option as well as many short options (e.g. -p -S
-x). People who use them as replacement of GNU binutils often use the
grouped option syntax (POSIX Utility Conventions), e.g. -Sx => -S -x,
-Wd => -W -d, -sj.text => -s -j.text
There is ambiguity if a long option starts with the character used by a
short option. Drop the support for -long-option to resolve the ambiguity.
This divergence from other utilities is accepted (other utilities
continue supporting -long-option).
https://lists.llvm.org/pipermail/llvm-dev/2019-April/131786.html
Reviewers: alexshap, jakehehrlich, jhenderson, rupprecht, espindola
Reviewed By: jakehehrlich, jhenderson, rupprecht
Subscribers: grimar, emaste, arichardson, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359265
91177308-0d34-0410-b5e6-
96231b3b80d8
Justin Bogner [Fri, 26 Apr 2019 00:12:50 +0000 (00:12 +0000)]
[GlobalOpt] Swap the expensive check for cold calls with the cheap TTI check
isValidCandidateForColdCC is much more expensive than
TTI.useColdCCForColdCall, which by default just returns false. Avoid
doing this work if we're not going to look at the answer anyway.
This change is NFC, but I see significant compile time improvements on
some code with pathologically many functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359253
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 25 Apr 2019 23:31:33 +0000 (23:31 +0000)]
[ORC] Remove symbols from dependency lists when failing materialization.
When failing materialization of a symbol X, remove X from the dependants list
of any of X's dependencies. This ensures that when X's dependencies are
emitted (or fail themselves) they do not try to access the no-longer-existing
MaterializationInfo for X.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359252
91177308-0d34-0410-b5e6-
96231b3b80d8
Artem Belevich [Thu, 25 Apr 2019 22:28:09 +0000 (22:28 +0000)]
[CUDA] Implemented _[bi]mma* builtins.
These builtins provide access to the new integer and
sub-integer variants of MMA (matrix multiply-accumulate) instructions
provided by CUDA-10.x on sm_75 (AKA Turing) GPUs.
Also added a feature for PTX 6.4. While Clang/LLVM does not generate
any PTX instructions that need it, we still need to pass it through to
ptxas in order to be able to compile code that uses the new 'mma'
instruction as inline assembly (e.g used by NVIDIA's CUTLASS library
https://github.com/NVIDIA/cutlass/blob/master/cutlass/arch/mma.h#L101)
Differential Revision: https://reviews.llvm.org/D60279
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359248
91177308-0d34-0410-b5e6-
96231b3b80d8
Artem Belevich [Thu, 25 Apr 2019 22:27:57 +0000 (22:27 +0000)]
PTX 6.3 extends `wmma` instruction to support s8/u8/s4/u4/b1 -> s32.
All of the new instructions are still handled mostly by tablegen. I've slightly
refactored the code to drive intrinsic/instruction generation from a master
list of supported variants, so all irregularities have to be implemented in one place only.
The test generation script wmma.py has been refactored in a similar way.
Differential Revision: https://reviews.llvm.org/D60015
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359247
91177308-0d34-0410-b5e6-
96231b3b80d8
Artem Belevich [Thu, 25 Apr 2019 22:27:46 +0000 (22:27 +0000)]
[NVPTX] generate correct MMA instruction mnemonics with PTX63+.
PTX 6.3 requires using ".aligned" in the MMA instruction names.
In order to generate correct name, now we pass current
PTX version to each instruction as an extra constant operand
and InstPrinter adjusts its output accordingly.
Differential Revision: https://reviews.llvm.org/D59393
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359246
91177308-0d34-0410-b5e6-
96231b3b80d8
Artem Belevich [Thu, 25 Apr 2019 22:27:35 +0000 (22:27 +0000)]
[NVPTX] Refactor generation of MMA intrinsics and instructions. NFC.
Generalized constructions of 'fragments' of MMA operations to provide
common primitives for construction of the ops. This will make it easier
to add new variants of the instructions that operate on integer types.
Use nested foreach loops which makes it possible to better control
naming of the intrinsics.
This patch does not affect LLVM's output, so there are no test changes.
Differential Revision: https://reviews.llvm.org/D59389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359245
91177308-0d34-0410-b5e6-
96231b3b80d8
Sean Fertile [Thu, 25 Apr 2019 21:36:04 +0000 (21:36 +0000)]
[Object][XCOFF] Add intial support for section header table.
Adds a representation of the section header table to XCOFFObjectFile,
and implements enough to dump the section headers with llvm-obdump.
Differential Revision: https://reviews.llvm.org/D60784
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359244
91177308-0d34-0410-b5e6-
96231b3b80d8
Keno Fischer [Thu, 25 Apr 2019 21:28:03 +0000 (21:28 +0000)]
[CMake][PowerPC] Recognize LLVM_NATIVE_TARGET="ppc64le" as PowerPC
Summary:
This value is derived from the host triple, which on the machine
I'm currently using is `ppc64le-linux-redhat`. This change makes
LLVM compile.
Reviewers: nemanjai
Differential Revision: https://reviews.llvm.org/D57118
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359242
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Thu, 25 Apr 2019 20:39:06 +0000 (20:39 +0000)]
[AMDGPU] gfx1010 - fix ubsan failure
Revert DecoderNamespace in one place for now. It will need more
changes to properly work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359239
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 25 Apr 2019 20:35:47 +0000 (20:35 +0000)]
[x86] add tests for vector fdiv reciprocal estimate; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359238
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Thu, 25 Apr 2019 20:09:00 +0000 (20:09 +0000)]
Assigning to a local object in a return statement prevents copy elision. NFC.
I added a diagnostic along the lines of `-Wpessimizing-move` to detect `return x = y` suppressing copy elision, but I don't know if the diagnostic is really worth it. Anyway, here are the places where my diagnostic reported that copy elision would have been possible if not for the assignment.
P1155R1 in the post-San-Diego WG21 (C++ committee) mailing discusses whether WG21 should fix this pitfall by just changing the core language to permit copy elision in cases like these.
(Kona update: The bulk of P1155 is proceeding to CWG review, but specifically *not* the parts that explored the notion of permitting copy-elision in these specific cases.)
Reviewed By: dblaikie
Author: Arthur O'Dwyer
Differential Revision: https://reviews.llvm.org/D54885
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359236
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Thu, 25 Apr 2019 20:00:57 +0000 (20:00 +0000)]
[GlobalISel][AArch64] Make G_EXTRACT_VECTOR_ELT legal for v8s16s
This case was missing before, so we couldn't legalize it.
Add it to AArch64LegalizerInfo.cpp and update select-extract-vector-elt.mir.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359231
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Thu, 25 Apr 2019 19:42:55 +0000 (19:42 +0000)]
[ObjC][ARC] Let ARC optimizer bail out if the number of pointer states
it keeps track of becomes too large
ARC optimizer does a top-down and a bottom-up traversal of the whole
function to pair up retain and release instructions and remove them.
This can be expensive if the number of instructions in the function and
pointer states it tracks are large since it has to look at each pointer
state and determine whether the instruction being visited can
potentially use the pointer.
This patch adds a command line option that sets a limit to the number of
pointers it tracks.
rdar://problem/
49477063
Differential Revision: https://reviews.llvm.org/D61100
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359226
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Thu, 25 Apr 2019 19:01:51 +0000 (19:01 +0000)]
[AMDGPU] gfx1010 VOP1 instructions
Differential Revision: https://reviews.llvm.org/D61099
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359225
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Thu, 25 Apr 2019 18:53:41 +0000 (18:53 +0000)]
[AMDGPU] gfx1010 utility functions
Differential Revision: https://reviews.llvm.org/D61094
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359224
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Thu, 25 Apr 2019 18:42:00 +0000 (18:42 +0000)]
[GlobalISel][AArch64] Add generic legalization rule for extends
This adds a legalization rule for G_ZEXT, G_ANYEXT, and G_SEXT which allows
extends whenever the types will fit in registers (or the source is an s1).
Update tests. Add GISel checks throughout all of arm64-vabs.ll,
where we now select a good portion of the code. Add GISel checks to
arm64-subvector-extend.ll, which has a good number of vector extends in it.
Differential Revision: https://reviews.llvm.org/D60889
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359222
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 25 Apr 2019 18:19:59 +0000 (18:19 +0000)]
[SelectionDAG][X86] Use stack load/store in PromoteIntRes_BITCAST when the input needs to be be split and the output type is a vector.
We had special case handling here, but it uses a scalar any_extend for the
promotion then bitcasts to the final type. This won't split up the input data
into multiple promoted elements like we need.
This patch falls back to doing the conversion through memory.
Fixes PR41594 which I believe was reflected in the bitcast-vector-bool.ll
changes. The changes to vector-half-conversions.ll are fixing a previously
unknown miscompile from this issue.
Differential Revision: https://reviews.llvm.org/D61114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359219
91177308-0d34-0410-b5e6-
96231b3b80d8
Robert Lougher [Thu, 25 Apr 2019 17:00:01 +0000 (17:00 +0000)]
[Evaluator] Walk initial elements when handling load through bitcast
When evaluating a store through a bitcast, the evaluator tries to move the
bitcast from the pointer onto the stored value. If the cast is invalid, it
tries to "introspect" the type to get a valid cast by obtaining a pointer to
the initial element (if the type is nested, this may require walking several
initial elements).
In some situations it is possible to get a bitcast on a load (e.g. with
unions, where the bitcast may not be the same type as the store). However,
equivalent logic to the store to introspect the type is missing. This patch
add this logic.
Note, when developing the patch I was unhappy with adding similar logic
directly to the load case as it could get out of step. Instead, I have
abstracted the "introspection" into a helper function, with the specifics
being handled by a passed-in lambda function.
Differential Revision: https://reviews.llvm.org/D60793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359205
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Thu, 25 Apr 2019 16:44:40 +0000 (16:44 +0000)]
[GlobalISel][AArch64] Legalize G_FNEARBYINT
Add legalizer support for G_FNEARBYINT. It's the same as G_FCEIL etc.
Since the importer allows us to automatically select this after legalization,
also add tests for selection etc. Also update arm64-vfloatintrinsics.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359204
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Thu, 25 Apr 2019 16:39:28 +0000 (16:39 +0000)]
[GlobalISel] Add IRTranslator support for G_FNEARBYINT
Translate llvm.nearbyint into G_FNEARBYINT as a simple intrinsic. Update
arm64-irtranslator.ll.
Differential Revision: https://reviews.llvm.org/D60922
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359203
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Thu, 25 Apr 2019 16:36:03 +0000 (16:36 +0000)]
[GlobalISel] Add a G_FNEARBYINT opcode
For eventually selecting llvm.nearbyint. Equivalent to the SelectionDAG
nearbyint node.
Update legalizer-info-validation.mir.
Differential Revision: https://reviews.llvm.org/D60921
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359201
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 25 Apr 2019 15:18:31 +0000 (15:18 +0000)]
Revert "[JITLink] Make the JITLink MachO/x86-64 eh-frame test work on Windows."
This reverts r359169, as it broke one of the windows bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359198
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Thu, 25 Apr 2019 14:56:56 +0000 (14:56 +0000)]
gn build: Document llvm_enable_dia_sdk variable better
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359196
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Thu, 25 Apr 2019 14:53:53 +0000 (14:53 +0000)]
gn build: Make setting llvm_enable_dia_sdk=true work
If this is set, %INCLUDE% must contain ".../DIA SDK/include"
and %LIB% must contain ".../DIA SKD/lib/amd64" (assuming you're doing a
64-bit build).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359195
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 25 Apr 2019 13:51:57 +0000 (13:51 +0000)]
[InstCombine][X86] Tweak generic expansion of PACKSS/PACKUS to shuffle then truncate. NFCI.
This has no effect on constant folding but will be useful when we expand non-saturating PACKSS/PACKUS intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359191
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam McCall [Thu, 25 Apr 2019 13:33:18 +0000 (13:33 +0000)]
[Support] json::OStream::flush(), which passes through to the underlying stream
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359190
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Thu, 25 Apr 2019 13:29:34 +0000 (13:29 +0000)]
gn build: Merge r359179
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359189
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Thu, 25 Apr 2019 13:26:54 +0000 (13:26 +0000)]
gn build: Merge r359174
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359188
91177308-0d34-0410-b5e6-
96231b3b80d8