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Simon Pilgrim [Thu, 12 Apr 2018 18:25:38 +0000 (18:25 +0000)]
[X86] Remove gpr shift/extension schedule itineraries (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329933
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Lei Huang [Thu, 12 Apr 2018 18:00:14 +0000 (18:00 +0000)]
[Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision
Legalize and emit code for:
* xscvsdqp
* xscvudqp
Differential Revision: https://reviews.llvm.org/D45230
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329931
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Benjamin Kramer [Thu, 12 Apr 2018 17:28:30 +0000 (17:28 +0000)]
[MCJIT] Remove the anchor from mcjit.
This is a layering violation. LTO shouldn't depend on MCJIT. The right
fix for this is moving the class somewhere else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329929
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Petar Jovanovic [Thu, 12 Apr 2018 17:01:46 +0000 (17:01 +0000)]
[MIPS GlobalISel] remove superfluous #includes (NFC)
Remove superfluous #includes.
Minor code style change in MipsCallLowering::lowerFormalArguments().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329926
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Jessica Paquette [Thu, 12 Apr 2018 16:16:18 +0000 (16:16 +0000)]
[AArch64] Move AFI->setRedZone(false) to top of emitPrologue
AFI->setRedZone(false) was put in the wrong place before, and so it only fired
on functions that didn't have stack frames. This moves that to the top of
emitPrologue to make sure that every function without a redzone has it set
correctly.
This also adds a function representing one of the early exit cases (GHC calling
convention) to the MachineOutliner noredzone test to ensure that we can outline
from functions like these, where we never use a redzone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329922
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Sanjay Patel [Thu, 12 Apr 2018 15:27:01 +0000 (15:27 +0000)]
revert r328921 - [DAGCombine] (float)((int) f) --> ftrunc (PR36617)
This change is exposing UB in source code - as was warned/predicted. :)
See D44909 for discussion. Reverting while we figure out how to fix things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329920
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Krzysztof Parzyszek [Thu, 12 Apr 2018 15:11:11 +0000 (15:11 +0000)]
[Pipeliner] Use std::stable_sort when ordering NodeSets
There are cases when individual NodeSets can be equal with respect to
the ordering criteria. Since they are stored in an ordered container,
use stable_sort to preserve the relative order of equal NodeSets.
This should remove non-determinism discovered by shuffling done in
llvm::sort with expensive checks enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329915
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Simon Dardis [Thu, 12 Apr 2018 14:41:38 +0000 (14:41 +0000)]
[mips] Correct the predicates of the load/store (double)word for coprocessor 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329913
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Simon Pilgrim [Thu, 12 Apr 2018 14:31:42 +0000 (14:31 +0000)]
[X86] Remove AES/CLMUL/CRC32/LDDQU/MOVNT/POPCNT/SHA schedule itineraries (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329912
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Benjamin Kramer [Thu, 12 Apr 2018 13:52:02 +0000 (13:52 +0000)]
Revert "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time."
This reverts commit r329865. Causes stage2/stage3 miscompare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329910
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Sander de Smalen [Thu, 12 Apr 2018 13:19:32 +0000 (13:19 +0000)]
[AArch64][AsmParser] Unify 'addVectorListOperands' functions.
Summary:
Merged 'addVectorList64Operands' and 'addVectorList128Operands' into a
generic 'addVectorListOperands', which can be easily extended to work
for SVE vectors.
This is patch [4/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329909
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Francis Visoiu Mistrih [Thu, 12 Apr 2018 12:59:50 +0000 (12:59 +0000)]
[CodeGen] Allow printing MachineMemOperands with less context in SDAGDumper
Don't assume SelectionDAG is non-null as the targets can use it with a
null pointer.
Differential Revision: https://reviews.llvm.org/D44611
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329908
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Sam Parker [Thu, 12 Apr 2018 12:49:40 +0000 (12:49 +0000)]
[IRCE] isKnownNonNegative helper function
Created a helper function to query for non negative SCEVs. Uses the
SGE predicate to catch constants that could be interpreted as
negative.
Differential Revision: https://reviews.llvm.org/D45481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329907
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Simon Pilgrim [Thu, 12 Apr 2018 12:43:49 +0000 (12:43 +0000)]
[X86] Remove remaining system/special schedule itineraries (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329906
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Simon Dardis [Thu, 12 Apr 2018 12:37:02 +0000 (12:37 +0000)]
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx.
Reviewers: atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D44436
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329905
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Simon Pilgrim [Thu, 12 Apr 2018 12:09:24 +0000 (12:09 +0000)]
[X86] Remove system/control schedule itineraries (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329903
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Roman Lebedev [Thu, 12 Apr 2018 12:04:57 +0000 (12:04 +0000)]
[InstCombine][NFC]: Add tests: foldSelectICmpAndAnd(): and is commutative
Summary:
The fold added in D45108 did not account for the fact that
the and instruction is commutative, and if the mask is a variable,
the mask variable and the fold variable may be swapped.
I have noticed this by accident when looking into [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]]
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45538
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329901
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Sander de Smalen [Thu, 12 Apr 2018 11:40:52 +0000 (11:40 +0000)]
[AArch64][AsmParser] Make parse function for VectorLists generic to other vector types.
Summary:
Added 'RegisterKind' to the VectorListOp structure, so that this operand
type can be reused for SVE vector lists in a later patch. It also
refactors the 'tryParseVectorList' function so it can be used directly
in the ParserMethod of an operand. The parsing can now parse multiple
kinds of vectors and recover if there is no match.
This is patch [3/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329900
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Shiva Chen [Thu, 12 Apr 2018 11:30:59 +0000 (11:30 +0000)]
[RISCV] Change function alignment to 4 bytes, and 2 bytes for RVC
Summary:
According RISC-V ELF psABI specification, base RV32 and RV64 ISAs only
allow 32-bit instruction alignment, but instruction allow to be aligned
to 16-bit boundaries for C-extension.
So we just align to 4 bytes and 2 bytes for C-extension is enough.
Reviewers: asb, apazos
Differential Revision: https://reviews.llvm.org/D45560
Patch by Kito Cheng.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329899
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Simon Pilgrim [Thu, 12 Apr 2018 11:01:40 +0000 (11:01 +0000)]
[X86] Remove CMOV/SETCC schedule itineraries (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329898
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Simon Pilgrim [Thu, 12 Apr 2018 10:49:57 +0000 (10:49 +0000)]
[X86] Remove MMX/3DNow schedule itineraries (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329896
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Andrea Di Biagio [Thu, 12 Apr 2018 10:49:40 +0000 (10:49 +0000)]
[llvm-mca] Removed unused argument from cycleEvent. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329895
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Simon Pilgrim [Thu, 12 Apr 2018 10:27:37 +0000 (10:27 +0000)]
[X86] Remove X87 schedule itineraries (PR37093)
First of a number of commits to remove x86 schedule itineraries entirely - approved off-line with @craig.topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329893
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Petar Jovanovic [Thu, 12 Apr 2018 09:12:29 +0000 (09:12 +0000)]
[MIPS GlobalISel] minor update to MIR tests added in r329819
Remove 'registers' section, as suggested (D. Sanders) at code review
https://reviews.llvm.org/D44304
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329888
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Jonas Paulsson [Thu, 12 Apr 2018 08:08:42 +0000 (08:08 +0000)]
[SystemZ] Use ResourceCycles=30 for FPd unit (NFC).
This is better than listing FPd 30 times :-)
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329887
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Jonas Paulsson [Thu, 12 Apr 2018 08:06:04 +0000 (08:06 +0000)]
[SystemZ] Remove FullInstRWOverlapCheck from SchedMachineModels.
This is NFC, even though it caught just a few cases of overlapping regular
expressions.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329886
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Jonas Paulsson [Thu, 12 Apr 2018 07:39:33 +0000 (07:39 +0000)]
[HexagonMachineScheduler] Remove local (copied) getWeakLeft().
Since the common code getWeakLeft() is now available, there should not
be a local copy of this function in target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329885
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Jonas Paulsson [Thu, 12 Apr 2018 07:21:39 +0000 (07:21 +0000)]
[MachineScheduler] NFC refactoring
This patch makes tryCandidate() virtual and some utility functions like
tryLess(), tryGreater(), ... externally available (used to be static).
This makes it possible for a target to derive a new MachineSchedStrategy from
GenericScheduler and reuse most parts.
It was necessary to wrap functions with the same names in
AMDGPU/SIMachineScheduler in a local namespace.
Review: Andy Trick, Florian Hahn
https://reviews.llvm.org/D43329
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329884
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Craig Topper [Thu, 12 Apr 2018 06:51:58 +0000 (06:51 +0000)]
[LegalizeTypes] Remove unnecessary type action check on the type of operand 0 when promoting shift result type. NFC
Operand 0 should have the same type of the result. So if the result type needs to be promoted, operand 0 needs to be promoted unconditionally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329883
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Hiroshi Inoue [Thu, 12 Apr 2018 05:53:20 +0000 (05:53 +0000)]
[NFC] fix trivial typos in documents and comments
"is is" -> "is", "if if" -> "if", "or or" -> "or"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329878
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Alex Bradbury [Thu, 12 Apr 2018 05:50:06 +0000 (05:50 +0000)]
[RISCV] Codegen support for RV32D floating point comparison operations
Also add double-prevoius-failure.ll which captures a test case that at one
point triggered a compiler crash, while developing calling convention support
for f64 on RV32D with soft-float ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329877
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Alex Bradbury [Thu, 12 Apr 2018 05:47:15 +0000 (05:47 +0000)]
[RISCV] Codegen support for RV32D floating point conversion operations
This also includes support and a test for truncating stores, which are now
possible thanks to the fpround pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329876
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Alex Bradbury [Thu, 12 Apr 2018 05:42:42 +0000 (05:42 +0000)]
[RISCV] Add codegen support for RV32D floating point arithmetic operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329874
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Alex Bradbury [Thu, 12 Apr 2018 05:36:44 +0000 (05:36 +0000)]
[RISCV] Add tests missed in r329871
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329872
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Alex Bradbury [Thu, 12 Apr 2018 05:34:25 +0000 (05:34 +0000)]
[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv
fadd.d is required in order to force floating point registers to be used in
test code, as parameters are passed in integer registers in the soft float
ABI.
Much of this patch is concerned with support for passing f64 on RV32D with a
soft-float ABI. Similar to Mips, introduce pseudoinstructions to build an f64
out of a pair of i32 and to split an f64 to a pair of i32. BUILD_PAIR and
EXTRACT_ELEMENT can't be used, as a BITCAST to i64 would be necessary, but i64
is not a legal type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329871
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Yan Luo [Thu, 12 Apr 2018 04:26:49 +0000 (04:26 +0000)]
Test commit access
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329870
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George Burgess IV [Thu, 12 Apr 2018 02:06:01 +0000 (02:06 +0000)]
[DeadArgElim] Remove allocsize attributes on callsites
We're already removing allocsize attributes from Functions that we
remove args from, since removing arguments from a function may make the
allocsize attribute incorrect. It appears we forgot to also remove them
from callsites.
Without this, I get verifier errors on `@Test2`.
It probably wouldn't be too hard to make DAE properly update allocsize
attributes instead of dropping them, but I can't think of a scenario
where that'd be useful in practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329868
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Jake Ehrlich [Thu, 12 Apr 2018 00:40:50 +0000 (00:40 +0000)]
Revert "[llvm-objcopy] Switch over to using TableGen for parsing arguments"
TableGen seems to work differently on windows. I'll need to revert this
This reverts commit
7a153ddea067b24da59f6a66c733d79205969501.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329867
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Michael Zolotukhin [Wed, 11 Apr 2018 23:37:53 +0000 (23:37 +0000)]
Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time.
This reapplies commit r329644.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329865
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Michael Zolotukhin [Wed, 11 Apr 2018 23:37:37 +0000 (23:37 +0000)]
[SSAUpdaterBulk] Fix linux bootstrap/sanitizer failures: explicitly specify order of evaluation.
The standard says that the order of evaluation of an expression
s[x] = foo()
is unspecified. In our case, we first create an empty entry in the map,
then call foo(), then store its return value to the created entry. The
problem is that foo uses the map as a cache, so if it finds that there
is an entry in the map, it stops computation. This change explicitly
sets the order, thus fixing this heisenbug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329864
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Jake Ehrlich [Wed, 11 Apr 2018 23:37:03 +0000 (23:37 +0000)]
[llvm-objcopy] Switch over to using TableGen for parsing arguments
Swithces from using the command line library to using TableGen. This will allow
llvm-strip to exist and allow refinements of the command line syntax.
Differential Revision: https://reviews.llvm.org/D44236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329863
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Simon Pilgrim [Wed, 11 Apr 2018 23:24:38 +0000 (23:24 +0000)]
[X86] Remove unused itinerary argument from FMA3/FMA4/XOP instructions. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329862
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Weiming Zhao [Wed, 11 Apr 2018 23:09:20 +0000 (23:09 +0000)]
Add missing vtable anchors
Summary: This patch adds anchor() for MemoryBuffer, raw_fd_ostream, RTDyldMemoryManager, SectionMemoryManager, etc.
Reviewers: jlebar, eli.friedman, dblaikie
Reviewed By: dblaikie
Subscribers: mehdi_amini, mgorny, dblaikie, weimingz, llvm-commits
Differential Revision: https://reviews.llvm.org/D45244
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329861
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Simon Pilgrim [Wed, 11 Apr 2018 23:08:30 +0000 (23:08 +0000)]
X86FoldTableEntry - avoid unnecessary std::string creation. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329860
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whitequark [Wed, 11 Apr 2018 22:40:42 +0000 (22:40 +0000)]
[LLVM-C] Add LLVMGetHostCPU{Name,Features}.
Without these functions it's hard to create a TargetMachine for
Orc JIT that creates efficient native code.
It's not sufficient to just expose LLVMGetHostCPUName(), because
for some CPUs there's fewer features actually available than
the CPU name indicates (e.g. AVX might be missing on some CPUs
identified as Skylake).
Differential Revision: https://reviews.llvm.org/D44861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329856
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Simon Pilgrim [Wed, 11 Apr 2018 22:24:48 +0000 (22:24 +0000)]
Don't repeatedly evaluate size() in the for loop. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329853
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Nemanja Ivanovic [Wed, 11 Apr 2018 21:25:44 +0000 (21:25 +0000)]
[PowerPC] Fix condition for 64-bit rotate when replacing r+r instr with r+i
This patch fixes https://bugs.llvm.org/show_bug.cgi?id=37039
The condition only covers one of the two 64-bit rotate instructions. This just
adds the second (RLDICLo).
Patch by Josh Stone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329852
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Puyan Lotfi [Wed, 11 Apr 2018 20:29:32 +0000 (20:29 +0000)]
Attempting to work around a non-determinism issue.
The main thing that matters with this test is that the COPYs
are moved together not where the REG_SEQUENCES are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329850
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Yonghong Song [Wed, 11 Apr 2018 20:24:52 +0000 (20:24 +0000)]
bpf: signal error instead of silent drop for certain invalid asm insn
Currently, an invalid asm insn, either in an asm file or
in an inline asm format, might be silently dropped. This patch
fixed two places where this may happen by
signaling the error so user knows what goes wrong.
The following is an example to demonstrate error messages:
-bash-4.2$ cat t.c
int test(void *ctx) {
#if defined(NO_ERROR)
asm volatile("r0 = *(u16 *)skb[%0]" : : "i"(2));
#elif defined(ERROR_1)
asm volatile("r20 = *(u16 *)skb[%0]" : : "i"(2));
#elif defined(ERROR_2)
asm volatile("r0 = *(u16 *)(r1 + ?)" : :);
#endif
return 0;
}
-bash-4.2$ cat run.sh
for macro in NO_ERROR ERROR_1 ERROR_2; do
echo "===== compile for macro" $macro
clang -D${macro} -O2 -target bpf -emit-llvm -S t.c
echo "==llc=="
llc -march=bpf -filetype=obj t.ll
done
-bash-4.2$ ./run.sh
===== compile for macro NO_ERROR
==llc==
===== compile for macro ERROR_1
==llc==
<inline asm>:1:2: error: invalid register/token name
r20 = *(u16 *)skb[2]
^
note: !srcloc = 135
===== compile for macro ERROR_2
==llc==
<inline asm>:1:21: error: unexpected token
r0 = *(u16 *)(r1 + ?)
^
note: !srcloc = 210
-bash-4.2$
Acked-by: Alexei Starovoitov <ast@kernel.org>
Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329849
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Gabor Buella [Wed, 11 Apr 2018 20:01:57 +0000 (20:01 +0000)]
[X86] Describe wbnoinvd instruction
Similar to the wbinvd instruction, except this
one does not invalidate caches. Ring 0 only.
The encoding matches a wbinvd instruction with
an F3 prefix.
Reviewers: craig.topper, zvi, ashlykov
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D43816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329847
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Daniel Neilson [Wed, 11 Apr 2018 19:46:02 +0000 (19:46 +0000)]
[DSE] Add tests for atomic memory intrinsics (NFC)
Summary:
These tests show that DSE currently does nothing with the atomic memory
intrinsics. Future work will teach DSE how to simplify these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329845
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David Blaikie [Wed, 11 Apr 2018 18:49:37 +0000 (18:49 +0000)]
Rename *CommandFlags.def to *CommandFlags.inc
These aren't the .def style files used in LLVM that require a macro
defined before their inclusion - they're just basic non-modular includes
to stamp out command line flag variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329840
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Daniel Neilson [Wed, 11 Apr 2018 18:43:10 +0000 (18:43 +0000)]
[DSE] Regenerate tests with update_test_checks.py (NFC)
Summary:
In preparation for a future commit, this regenerates the test checks for
test/Transforms/DeadStoreElimination/OverwriteStoreBegin.ll
test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329839
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Peter Collingbourne [Wed, 11 Apr 2018 18:24:03 +0000 (18:24 +0000)]
CodeGen: Don't try to canonicalize Unix-style paths in CodeView debug info.
Most importantly, we should not replace slashes with backslashes
because that would invalidate the path.
Differential Revision: https://reviews.llvm.org/D45473
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329838
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Simon Pilgrim [Wed, 11 Apr 2018 18:23:01 +0000 (18:23 +0000)]
[X86][Atom] Convert Atom scheduler model to SchedRW (PR32431)
Atom is the only x86 target that still uses schedule itineraries, if we can remove this then we can begin the work on removing x86 itineraries. I've also found that it will help with PR36550.
I've focussed on matching the existing model as closely as possible (relying on the schedule tests), PR36895 indicated a lot of these were incorrect but we can just as easily fix these after this patch as before. Hopefully we can get llvm-exegesis to help here,
There are a few instructions that rely on itinerary scheduling (mainly push/pop/return) of multiple resource stages, but I don't think any of these are show stoppers.
There are also a few codegen changes that seem related to the post-ra scheduler acting a little differently, I haven't tracked these down but they don't seem critical.
NOTE: I don't have access to any Atom hardware, so this hasn't been tested in the wild.
Differential Revision: https://reviews.llvm.org/D45486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329837
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Andrea Di Biagio [Wed, 11 Apr 2018 18:05:23 +0000 (18:05 +0000)]
[llvm-mca] Let the Scheduler notify dispatch stall events caused by the lack of scheduling resources.
This patch moves part of the logic that notifies dispatch stall events from the
DispatchUnit to the Scheduler.
The main goal of this patch is to remove (yet another) dependency between the
DispatchUnit and the Scheduler. Before this patch, the DispatchUnit had to know
about `Scheduler::Event` and how to classify stalls due to the lack of scheduling
resources. This patch removes that knowledge and simplifies the logic in
DispatchUnit::checkScheduler.
This is another change done in preparation for the work to fix PR36663.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329835
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Simon Pilgrim [Wed, 11 Apr 2018 18:05:17 +0000 (18:05 +0000)]
[X86] Generalize X86PadShortFunction to work with TargetSchedModel
Pre-commit for D45486, don't rely on itinerary scheduler model to determine latencies for padding, use the generic TargetSchedModel::computeInstrLatency call.
Also, replace hard coded (atom specific) 2*uop creation per padding cycle with a version based on the scheduler model's issue width.
Differential Revision: https://reviews.llvm.org/D45486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329834
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Artem Belevich [Wed, 11 Apr 2018 17:51:33 +0000 (17:51 +0000)]
[NVPTX] Removed 'satom' feature which is no longer used.
Differential Revision: https://reviews.llvm.org/D45061
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329830
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Artem Belevich [Wed, 11 Apr 2018 17:51:19 +0000 (17:51 +0000)]
[NVPTX, CUDA] Improved feature constraints on NVPTX target builtins.
When NVPTX TARGET_BUILTIN specifies sm_XX or ptxYY as required feature,
consider those features available if we're compiling for GPU >= sm_XX or have
enabled PTX version >= ptxYY.
Differential Revision: https://reviews.llvm.org/D45061
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329829
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Tim Renouf [Wed, 11 Apr 2018 17:18:36 +0000 (17:18 +0000)]
[AMDGPU] Ensure there are enough registers for wave dispatch
Summary:
This fixes the number of SGPRs and VGPRs in the *_RSRC1 register to
allow for registers set up in wave dispatch, even if those registers are
not used in the shader.
Re-landed after noticing that the buildbot failure from 329808 seemed to
be unrelated.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45503
Change-Id: I6575f0e0d2a528d1319d0b289f0ebe4510fa5771
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329826
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Daniel Neilson [Wed, 11 Apr 2018 16:50:04 +0000 (16:50 +0000)]
[DSE] Regenerate tests with update_test_checks.py (NFC)
Summary:
In preparation for a future commit, this regenerates the test checks for
test/Transforms/DeadStoreElimination/simple.ll
test/Transforms/DeadStoreElimination/memintrinsics.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329824
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Reid Kleckner [Wed, 11 Apr 2018 16:03:07 +0000 (16:03 +0000)]
[FastISel] Disable local value sinking by default
This is causing compilation timeouts on code with long sequences of
local values and calls (i.e. foo(1); foo(2); foo(3); ...). It turns out
that code coverage instrumentation is a great way to create sequences
like this, which how our users ran into the issue in practice.
Intel has a tool that detects these kinds of non-linear compile time
issues, and Andy Kaylor reported it as PR37010.
The current sinking code scans the whole basic block once per local
value sink, which happens before emitting each call. In theory, local
values should only be introduced to be used by instructions between the
current flush point and the last flush point, so we should only need to
scan those instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329822
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Sanjay Patel [Wed, 11 Apr 2018 15:57:18 +0000 (15:57 +0000)]
[InstCombine] limit X - (cast(-Y) --> X + cast(Y) with hasOneUse()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329821
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Paul Robinson [Wed, 11 Apr 2018 15:14:05 +0000 (15:14 +0000)]
[DWARFv5] Fuss with asm syntax for conveying MD5 checksum.
Previously the MD5 option of the .file directive provided the checksum
as a quoted hex string; now it's a normal hex number with 0x prefix,
same as the .octa directive accepts.
Differential Revision: https://reviews.llvm.org/D45459
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329820
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Petar Jovanovic [Wed, 11 Apr 2018 15:12:32 +0000 (15:12 +0000)]
[MIPS GlobalISel] Select add i32, i32
Add the minimal support necessary to lower a function that returns the
sum of two i32 values.
Support argument/return lowering of i32 values through registers only.
Add tablegen for regbankselect and instructionselect.
Patch by Petar Avramovic.
Differential Revision: https://reviews.llvm.org/D44304
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329819
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Haicheng Wu [Wed, 11 Apr 2018 15:09:49 +0000 (15:09 +0000)]
[SLP] update a test case. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329818
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Yaxun Liu [Wed, 11 Apr 2018 14:46:15 +0000 (14:46 +0000)]
[AMDGPU] Fix lowering enqueue_kernel
Two issues were fixed:
runtime has difficulty to allocate memory for an external symbol of a
kernel and set the address of the external symbol, therefore make the runtime
handle of an enqueued kernel an ordinary global variable. Runtime only needs
to store the address of the loaded kernel to the handle and has verified
that this approach works.
handle the situation where __enqueue_kernel* gets inlined therefore
the enqueued kernel may be used through a constant expr instead
of an instruction.
Differential Revision: https://reviews.llvm.org/D45187
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329815
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Andrea Di Biagio [Wed, 11 Apr 2018 14:35:23 +0000 (14:35 +0000)]
Revert "[llvm-mca][CMake] Remove unused libraries from set LLVM_LINK_COMPONENTS"
It caused a buildbot failure (clang-ppc64le-linux-multistage - build #6424)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329812
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Tim Renouf [Wed, 11 Apr 2018 14:27:41 +0000 (14:27 +0000)]
Revert "[AMDGPU] Ensure there are enough registers for wave dispatch"
This reverts 329808. That change caused a report of a failure in
test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir that I didn't see. I suspect
it is an expensive-check-only error.
Change-Id: I8133f26f15e7d5ec2b09c687c12cd70e918461b0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329811
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Sander de Smalen [Wed, 11 Apr 2018 14:10:37 +0000 (14:10 +0000)]
[AArch64][AsmParser] Split index parsing from vector list.
Summary:
Place parsing of a vector index into a separate function to reduce
duplication, since the code is duplicated in both the parsing of a
Neon vector register operand and a Neon vector list.
This is patch [2/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329809
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Tim Renouf [Wed, 11 Apr 2018 14:02:41 +0000 (14:02 +0000)]
[AMDGPU] Ensure there are enough registers for wave dispatch
Summary:
This fixes the number of SGPRs and VGPRs in the *_RSRC1 register to
allow for registers set up in wave dispatch, even if those registers are
not used in the shader.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45503
Change-Id: I6575f0e0d2a528d1319d0b289f0ebe4510fa5771
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329808
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Andrea Di Biagio [Wed, 11 Apr 2018 13:52:42 +0000 (13:52 +0000)]
[llvm-mca][CMake] Remove unused libraries from set LLVM_LINK_COMPONENTS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329807
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Simon Pilgrim [Wed, 11 Apr 2018 13:49:19 +0000 (13:49 +0000)]
[X86] Add variable shuffle schedule classes
Split variable index shuffles from immediate index shuffles
WriteFVarShuffle - variable 'in-lane' shuffles (VPERMILPS/VPERMIL2PS etc.)
WriteVarShuffle - variable 'in-lane' shuffles (PSHUFB/VPPERM etc.)
WriteFVarShuffle256 - variable 'cross-lane' shuffles (VPERMPS etc.)
WriteVarShuffle256 - variable 'cross-lane' shuffles (VPERMD etc.)
Differential Revision: https://reviews.llvm.org/D45404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329806
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Francis Visoiu Mistrih [Wed, 11 Apr 2018 13:37:25 +0000 (13:37 +0000)]
[AArch64] Add test case for r329797
Forgot to add a test case in the previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329805
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Simon Pilgrim [Wed, 11 Apr 2018 13:15:36 +0000 (13:15 +0000)]
[X86][SSE] Tweak cmpps schedule test so that it works properly with just sse1
movhps/movlps test are still broken so we can't disable sse2 yet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329802
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Dmitry Preobrazhensky [Wed, 11 Apr 2018 13:13:30 +0000 (13:13 +0000)]
[AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32
See bug 36845: https://bugs.llvm.org/show_bug.cgi?id=36845
Differential Revision: https://reviews.llvm.org/D45443
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329801
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Francis Visoiu Mistrih [Wed, 11 Apr 2018 12:36:55 +0000 (12:36 +0000)]
[AArch64] Fix regression after r329691
In r329691, we would choose FP even if the offset wouldn't fit, just
because the offset is smaller than the one from BP. This made many
accesses through FP need to scavenge a register, which resulted in
slower and bigger code for no good reason.
This patch now always picks the offset that fits first, even if FP is
preferred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329797
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Andrea Di Biagio [Wed, 11 Apr 2018 12:31:44 +0000 (12:31 +0000)]
[llvm-mca] Minor code cleanup. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329796
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Andrea Di Biagio [Wed, 11 Apr 2018 12:12:53 +0000 (12:12 +0000)]
[llvm-mca] Renamed BackendStatistics to RetireControlUnitStatistics.
Also, removed flag -verbose in favor of flag -retire-stats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329794
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Andrea Di Biagio [Wed, 11 Apr 2018 11:37:46 +0000 (11:37 +0000)]
[llvm-mca] Move the logic that prints scheduler statistics from BackendStatistics to its own view.
Added flag -scheduler-stats to print scheduler related statistics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329792
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Artur Gainullin [Wed, 11 Apr 2018 10:29:37 +0000 (10:29 +0000)]
Eliminate a bitwise 'not' op of 'not' min/max by inverting the min/max.
Bitwise 'not' of the min/max could be eliminated in the pattern:
%notx = xor i32 %x, -1
%cmp1 = icmp sgt[slt/ugt/ult] i32 %notx, %y
%smax = select i1 %cmp1, i32 %notx, i32 %y
%res = xor i32 %smax, -1
https://rise4fun.com/Alive/lCN
Reviewers: spatel
Reviewed by: spatel
Subscribers: a.elovikov, llvm-commits
Differential Revision: https://reviews.llvm.org/D45317
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329791
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Sjoerd Meijer [Wed, 11 Apr 2018 09:28:04 +0000 (09:28 +0000)]
[ARM] FP16 VSEL codegen
This is a follow up of rL327695 to instruction select more variants of VSELGT
and VSELGE, for which it is necessary to custom lower SELECT.
More work is required in this area, which will be addressed soon:
- more variants need to be regression tested, but this depends on the next point.
- first LowerConstantFP need to be adjusted for fp16 values.
Differential Revision: https://reviews.llvm.org/D45205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329788
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Clement Courbet [Wed, 11 Apr 2018 07:39:00 +0000 (07:39 +0000)]
[Build][NFC] Split off libpfm detection to a separate module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329783
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Sander de Smalen [Wed, 11 Apr 2018 07:36:10 +0000 (07:36 +0000)]
[AArch64][AsmParser] Unify code for parsing Neon/SVE vectors.
Summary:
Merged 'tryMatchVectorRegister' (specific to Neon) and
'tryParseSVERegister' into a single 'tryParseVectorRegister' function, and
created a generic 'parseVectorKind()' function that returns the #Elements
and ElementWidth of a vector suffix. This reduces the duplication of
this functionality between two the vector implementations.
This is patch [1/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: fhahn
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329782
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Clement Courbet [Wed, 11 Apr 2018 07:32:43 +0000 (07:32 +0000)]
[llvm-exegesis] Add a flag to disable libpfm even if present.
Summary: Fixes PR37053.
Reviewers: uabelho, gchatelet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D45436
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329781
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Petr Hosek [Wed, 11 Apr 2018 05:18:03 +0000 (05:18 +0000)]
[CMake][runtimes] Process common options in runtimes build
This was removed in D39932 but turned out this is actually needed
because runtimes such as compiler-rt and libc++ rely on common options
processing for setting certain flags such as -ffunction-sections and
-fdata-sections.
Differential Revision: https://reviews.llvm.org/D45507
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329778
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Craig Topper [Wed, 11 Apr 2018 04:55:04 +0000 (04:55 +0000)]
[X86] Remove 128/256-bit masked pmaddubsw and pmaddwd intrinsics. Replace 512-bit masked intrinsic with unmasked intrinsic and a select.
The 128/256-bit versions were no longer used by clang. It uses the legacy SSE/AVX2 version and a select. The 512-bit was changed to the same for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329774
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Craig Topper [Wed, 11 Apr 2018 01:09:10 +0000 (01:09 +0000)]
[X86] In X86FlagsCopyLowering, when rewriting a memory setcc we need to emit an explicit MOV8mr instruction.
Previously the code only knew how to handle setcc to a register.
This should fix a crash in the chromium build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329771
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Craig Topper [Wed, 11 Apr 2018 01:05:32 +0000 (01:05 +0000)]
[X86] Switch a test from grep to FileCheck. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329769
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Sriraman Tallam [Tue, 10 Apr 2018 23:32:36 +0000 (23:32 +0000)]
Simplification of libcall like printf->puts must check for RtLibUseGOT metadata.
With -fno-plt, for example, calls to printf when getting converted to puts
still use the PLT. This patch checks for the metadata "RtLibUseGOT" and
annotates the declaration with the right attributes.
Differential Revision: https://reviews.llvm.org/D45180
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329768
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Rui Ueyama [Tue, 10 Apr 2018 22:58:08 +0000 (22:58 +0000)]
Use contains_lower() instead of find_lower() != StringRef::npos. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329767
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Sriraman Tallam [Tue, 10 Apr 2018 22:50:05 +0000 (22:50 +0000)]
GOTPCREL references must always use RIP.
With -fno-plt, global value references can use GOTPCREL and RIP must be used.
Differential Revision: https://reviews.llvm.org/D45460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329765
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Marek Olsak [Tue, 10 Apr 2018 22:48:23 +0000 (22:48 +0000)]
AMDGPU: enable 128-bit for local addr space under an option
Author: Samuel Pitoiset
ds_read_b128 and ds_write_b128 have been recently enabled
under the amdgpu-ds128 option because the performance benefit
is unclear.
Though, using 128-bit loads/stores for the local address space
appears to introduce regressions in tessellation shaders. Not
sure what is broken, but as ds_read_b128/ds_write_b128 are not
enabled by default, just introduce a global option and enable
128-bit only if requested (until it's fixed/used correctly).
v2: - fix regressions in merge-stores.ll and multiple_tails.ll
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329764
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Galina Kistanova [Tue, 10 Apr 2018 22:07:29 +0000 (22:07 +0000)]
Disable flaky tests till they get fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329763
91177308-0d34-0410-b5e6-
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Geoff Berry [Tue, 10 Apr 2018 21:43:03 +0000 (21:43 +0000)]
[AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass.
Summary:
When inserting MOVs to avoid Falkor HWPF collisions, the non-base
register operand of load instructions (e.g. a register offset) was not
being considered live, so it could potentially have been used as a
scratch register, clobbering the actual offset value.
Reviewers: mcrosier
Subscribers: rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329761
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Sanjay Patel [Tue, 10 Apr 2018 20:42:39 +0000 (20:42 +0000)]
[CVP] simplify phi with constant incoming values that match common variable edge values
This is based on an example that was recently posted on llvm-dev:
void *propagate_null(void* b, int* g) {
if (!b) {
return 0;
}
(*g)++;
return b;
}
https://godbolt.org/g/xYk3qG
The original code or constant propagation in other passes has obscured the fact
that the phi can be removed completely.
Differential Revision: https://reviews.llvm.org/D45448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329755
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Daniel Neilson [Tue, 10 Apr 2018 20:23:50 +0000 (20:23 +0000)]
[Verifier] Refactor duplicate code for atomic mem intrinsic verification (NFC)
Summary:
The verification rules for the intrinsics for atomic memcpy, atomic memmove,
and atomic memset are basically code clones. This change merges their verification
rules into a single block to remove duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329753
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Steven Wu [Tue, 10 Apr 2018 20:16:35 +0000 (20:16 +0000)]
[MachO] Emit Weak ReadOnlyWithRel to ConstDataSection
Summary:
Darwin dynamic linker can handle weak symbols in ConstDataSection.
ReadonReadOnlyWithRel symbols should be emitted in ConstDataSection
instead of normal DataSection.
rdar://problem/
39298457
Reviewers: dexonsmith, kledzik
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329752
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Daniel Neilson [Tue, 10 Apr 2018 19:51:44 +0000 (19:51 +0000)]
[IR] Refactor memset inst classes (NFC)
Summary:
A simple refactor to remove duplicate code in the definitions of
MemSetInst, AtomicMemSetInst, and AnyMemSetInst. Introduce a
templated base class that contains all of the methods unique to
a memset intrinsic, and derive these three classes from that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329747
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Jessica Paquette [Tue, 10 Apr 2018 19:46:43 +0000 (19:46 +0000)]
Recommit r329716 "Add missing nullptr check before getSection() to AArch64MachObjectWriter::recordRelocation"
This commit fixes the bot failures that were coming up before with r329716.
The fix was to move the check for "isInSection()" inside of the if condition
and emit the error there instead of waiting to get past the unreachable statement.
This should work in debug and release builds now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329746
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