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Rafael Espindola [Mon, 24 Nov 2014 20:53:26 +0000 (20:53 +0000)]
Remove the unused FindUsedTypes pass.
It was dead since r134829.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222684
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Rafael Espindola [Mon, 24 Nov 2014 20:44:36 +0000 (20:44 +0000)]
Add and use Type::subtypes. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222682
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Rafael Espindola [Mon, 24 Nov 2014 20:35:59 +0000 (20:35 +0000)]
Pass the .ll files to llvm-link directly. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222681
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Sergey Dmitrouk [Mon, 24 Nov 2014 19:40:07 +0000 (19:40 +0000)]
Correct path to regression tests in ExtendingLLVM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222678
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Chad Rosier [Mon, 24 Nov 2014 18:57:58 +0000 (18:57 +0000)]
[AArch64] Fix clobber computation in A57LoadBalancing pass.
Extremely difficult to reproduce, so no test case included.
PR21637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222677
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Colin LeMahieu [Mon, 24 Nov 2014 18:55:32 +0000 (18:55 +0000)]
Removing unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222676
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Kostya Serebryany [Mon, 24 Nov 2014 18:49:53 +0000 (18:49 +0000)]
[asan/coverage] change the way asan coverage instrumentation is done: instead of setting the guard to 1 in the generated code, pass the pointer to guard to __sanitizer_cov and set it there. No user-visible functionality change expected
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222675
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Ulrich Weigand [Mon, 24 Nov 2014 18:09:47 +0000 (18:09 +0000)]
[PowerPC] Fix PR 21652 - copy st_other bits on symbol assignment
When processing an assignment in the integrated assembler that sets
a symbol to the value of another symbol, we need to copy the st_other
bits that encode the local entry point offset.
Modeled after MipsTargetELFStreamer::emitAssignment handling of the
ELF::STO_MIPS_MICROMIPS flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222672
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Paul Robinson [Mon, 24 Nov 2014 18:05:29 +0000 (18:05 +0000)]
More long path name support on Windows, this time in program execution.
Allows long paths for the executable and redirected stdin/stdout/stderr.
Addresses PR21563.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222671
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Colin LeMahieu [Mon, 24 Nov 2014 18:04:42 +0000 (18:04 +0000)]
[Hexagon] Adding asrh instruction, removing unused multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222670
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Colin LeMahieu [Mon, 24 Nov 2014 17:44:19 +0000 (17:44 +0000)]
[Hexagon] Adding aslh instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222668
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Colin LeMahieu [Mon, 24 Nov 2014 17:11:34 +0000 (17:11 +0000)]
[Hexagon] Adding zxth instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222662
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Colin LeMahieu [Mon, 24 Nov 2014 16:50:40 +0000 (16:50 +0000)]
Adding const iterator to MCInst. reviews.llvm.org/D6359
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222661
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Colin LeMahieu [Mon, 24 Nov 2014 16:48:43 +0000 (16:48 +0000)]
[Hexagon] Adding zxtb instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222660
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David Majnemer [Mon, 24 Nov 2014 16:41:13 +0000 (16:41 +0000)]
InstCombine: Don't create an unused instruction
We would create an instruction but not inserting it.
Not inserting the unused instruction would lead us to verification
failure.
This fixes PR21653.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222659
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Jozef Kolek [Mon, 24 Nov 2014 16:14:10 +0000 (16:14 +0000)]
[mips][microMIPS] Fix JRADDIUSP instruction
Fix JRADDIUSP instruction, remove delay slot flag because this instruction
doesn't have delay slot.
Differential Revision: http://reviews.llvm.org/D6365
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222658
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Yaron Keren [Mon, 24 Nov 2014 14:51:41 +0000 (14:51 +0000)]
Added comment about llvm_execute_on_thread waiting for thread to complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222654
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Jozef Kolek [Mon, 24 Nov 2014 14:39:13 +0000 (14:39 +0000)]
[mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions
Differential Revision: http://reviews.llvm.org/D5122
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222653
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Jozef Kolek [Mon, 24 Nov 2014 14:25:53 +0000 (14:25 +0000)]
[mips][microMIPS] Implement 16-bit instructions registers including ZERO instead of S0
Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17.
Differential Revision: http://reviews.llvm.org/D5780
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222652
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Simon Atanasyan [Mon, 24 Nov 2014 14:17:33 +0000 (14:17 +0000)]
[Mips] Update MIPS relocations list
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222651
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Craig Topper [Mon, 24 Nov 2014 14:09:52 +0000 (14:09 +0000)]
Replace a comment that says 'unreachable' with llvm_unreachable in TableGen AsmWriter output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222650
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Aaron Ballman [Mon, 24 Nov 2014 14:03:16 +0000 (14:03 +0000)]
Removing a variable that is initialized but never read. The original author has been alerted to the warning, in case this variable is meant to be used. Fixes -Werror builds in the meantime.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222649
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Jozef Kolek [Mon, 24 Nov 2014 13:29:59 +0000 (13:29 +0000)]
[mips][microMIPS] Implement disassembler support for 16-bit instructions
With the help of new method readInstruction16() two bytes are read and
decodeInstruction() is called with DecoderTableMicroMips16, if this fails
four bytes are read and decodeInstruction() is called with
DecoderTableMicroMips32.
Differential Revision: http://reviews.llvm.org/D6149
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222648
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Andrea Di Biagio [Mon, 24 Nov 2014 12:23:15 +0000 (12:23 +0000)]
[X86] Improved target specific combine on VSELECT dag nodes.
This patch teaches function 'transformVSELECTtoBlendVECTOR_SHUFFLE' how to
convert VSELECT dag nodes to shuffles on targets that do not have SSE4.1.
On pre-SSE4.1 targets, we can still perform blend operations using movss/movsd.
Also, removed a target specific combine that performed a premature lowering of
VSELECT nodes to target specific MOVSS/MOVSD nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222647
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David Majnemer [Mon, 24 Nov 2014 07:26:20 +0000 (07:26 +0000)]
InstCombine: Don't assume DataLayout is always available
We tried to get the result of DataLayout::getLargestLegalIntTypeSize but
we didn't have a DataLayout. This resulted in opt crashing.
This fixes PR21651.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222645
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Duncan P. N. Exon Smith [Mon, 24 Nov 2014 03:13:02 +0000 (03:13 +0000)]
Support: Add *cast_or_null<> for pointer wrappers
Fill in omission of `cast_or_null<>` and `dyn_cast_or_null<>` for types
that wrap pointers (e.g., smart pointers).
Type traits need to be slightly stricter than for `cast<>` and
`dyn_cast<>` to resolve ambiguities with simple types.
There didn't seem to be any unit tests for pointer wrappers, so I tested
`isa<>`, `cast<>`, and `dyn_cast<>` while I was in there.
This only supports pointer wrappers with a conversion to `bool` to check
for null. If in the future it's useful to support wrappers without such
a conversion, it should be a straightforward incremental step to use the
`simplify_type` machinery for the null check. In that case, the unit
tests should be updated to remove the `operator bool()` from the
`pointer_wrappers::PTy`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222644
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Craig Topper [Mon, 24 Nov 2014 02:08:35 +0000 (02:08 +0000)]
Detect best type for some static index tables instead of just using uint32_t to reduce total data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222643
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Elena Demikhovsky [Sun, 23 Nov 2014 15:21:53 +0000 (15:21 +0000)]
Converted back to Unix format (after my last commit 222632)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222636
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Michael Kuperstein [Sun, 23 Nov 2014 13:09:06 +0000 (13:09 +0000)]
[X86] Fixes bug in build_vector v4x32 lowering
r222375 made some improvements to build_vector lowering of v4x32 and v4xf32 into an insertps, but it missed a case where:
1. A single extracted element is used twice.
2. The lower of the two non-zero indexes should be preserved, and the higher should be used for the dest mask.
This caused a crash, since the source value for the insertps ends-up uninitialized.
Differential Revision: http://reviews.llvm.org/D6377
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222635
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Craig Topper [Sun, 23 Nov 2014 09:40:13 +0000 (09:40 +0000)]
Add missing override keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222634
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Craig Topper [Sun, 23 Nov 2014 09:40:10 +0000 (09:40 +0000)]
Tablegen output formatting fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222633
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Elena Demikhovsky [Sun, 23 Nov 2014 08:07:43 +0000 (08:07 +0000)]
Masked Vector Load and Store Intrinsics.
Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores.
Added SDNodes for masked operations and lowering patterns for X86 code generator.
Examples:
<16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask)
declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask)
Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch.
http://reviews.llvm.org/D6191
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222632
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Matt Arsenault [Sun, 23 Nov 2014 02:57:54 +0000 (02:57 +0000)]
R600: Fix extloads of i1 on R600/Evergreen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222631
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Matt Arsenault [Sun, 23 Nov 2014 02:57:52 +0000 (02:57 +0000)]
R600: Fix assert on copy of an i1 on pre-SI
i1 is not a legal type on Evergreen, so this combine proceeded
and tried to produce a bitcast between i1 and i8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222630
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Matt Arsenault [Sun, 23 Nov 2014 02:57:50 +0000 (02:57 +0000)]
R600/SI: Add additional tests for i1 loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222629
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Matt Arsenault [Sun, 23 Nov 2014 02:57:49 +0000 (02:57 +0000)]
R600/SI: Fix broken check lines and modernize prefixes
Use -LABEL and remove -CHECK
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222628
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Matt Arsenault [Sun, 23 Nov 2014 02:57:47 +0000 (02:57 +0000)]
R600/SI: Fix missing -verify-machineinstrs on a test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222627
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David Majnemer [Sat, 22 Nov 2014 20:00:41 +0000 (20:00 +0000)]
InstCombine: Propagate exact for (sdiv X, Pow2) -> (udiv X, Pow2)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222625
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David Majnemer [Sat, 22 Nov 2014 20:00:38 +0000 (20:00 +0000)]
InstCombine: Propagate exact for (sdiv X, Y) -> (udiv X, Y)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222624
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David Majnemer [Sat, 22 Nov 2014 20:00:34 +0000 (20:00 +0000)]
InstCombine: Propagate exact for (sdiv -X, C) -> (sdiv X, -C)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222623
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Simon Pilgrim [Sat, 22 Nov 2014 19:12:10 +0000 (19:12 +0000)]
Tidied up target triple OS detection. NFC
Use Triple::isOS*() helper functions where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222622
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Craig Topper [Sat, 22 Nov 2014 18:30:18 +0000 (18:30 +0000)]
Reduce size of some tables in tablegen register info output.
Primarily done by using SequenceToOffsetTable to reduce the register pressure set tables and then sizing the indices into the tables appropriately. Size a few other table entries based on content as well. Reduces X86RegisterInfo.o by ~9k.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222621
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David Majnemer [Sat, 22 Nov 2014 18:16:54 +0000 (18:16 +0000)]
InstCombine: Propagate exact in (udiv (lshr X,C1),C2) -> (udiv x,C1<<C2)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222620
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Chandler Carruth [Sat, 22 Nov 2014 09:18:53 +0000 (09:18 +0000)]
[x86] Teach the vector shuffle yet another step of canonicalization.
No functionality changed yet, but this will prevent subsequent patches
from having to handle permutations of various interleaved shuffle
patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222614
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David Majnemer [Sat, 22 Nov 2014 08:57:02 +0000 (08:57 +0000)]
InstCombine: Propagate NSW/NUW for X*(1<<Y) -> X<<Y
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222613
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David Majnemer [Sat, 22 Nov 2014 07:25:19 +0000 (07:25 +0000)]
InstCombine: Propagate NSW for -X * -Y -> X * Y
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222612
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David Majnemer [Sat, 22 Nov 2014 07:15:16 +0000 (07:15 +0000)]
InstSimplify: Simplify (sub 0, X) -> X if it's NUW
This is a generalization of the X - (0 - Y) -> X transform.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222611
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David Majnemer [Sat, 22 Nov 2014 06:09:28 +0000 (06:09 +0000)]
InstCombine: Silence a parenthesis warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222609
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Chandler Carruth [Sat, 22 Nov 2014 05:44:43 +0000 (05:44 +0000)]
[x86] Add some tests for a common unpack pattern of vector shuffle that
has a remarkably unique and efficient lowering.
While we get this some of the time already, we miss a few cases and
there wasn't a principled reason we got it. We should at least test
this. v8 already has tests for this pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222607
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David Majnemer [Sat, 22 Nov 2014 04:52:55 +0000 (04:52 +0000)]
InstCombine: Preserve nsw when folding X*(2^C) -> X << C
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222606
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David Majnemer [Sat, 22 Nov 2014 04:52:52 +0000 (04:52 +0000)]
InstCombine: Preserve nsw/nuw for ((X << C2)*C1) -> (X * (C1 << C2))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222605
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David Majnemer [Sat, 22 Nov 2014 04:52:38 +0000 (04:52 +0000)]
InstCombine: Preserve nsw for (mul %V, -1) -> (sub 0, %V)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222604
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Gerolf Hoflehner [Fri, 21 Nov 2014 23:36:44 +0000 (23:36 +0000)]
[InstCombine] Re-commit of r218721 (Optimize icmp-select-icmp sequence)
Fixes the self-host fail. Note that this commit activates dominator
analysis in the combiner by default (like the original commit did).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222590
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Joerg Sonnenberger [Fri, 21 Nov 2014 22:39:34 +0000 (22:39 +0000)]
Fix transformation of add with pc argument to adr for non-immediate
arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222587
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Kostya Serebryany [Fri, 21 Nov 2014 22:34:29 +0000 (22:34 +0000)]
[asan] remove old experimental code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222586
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Tom Stellard [Fri, 21 Nov 2014 22:31:47 +0000 (22:31 +0000)]
R600/SI: Add a failing test case for offset order in ds_read2 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222585
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Tom Stellard [Fri, 21 Nov 2014 22:31:46 +0000 (22:31 +0000)]
R600/SI: Add an s_mov_b32 to patterns which use the M0RegClass
We need to use a s_mov_b32 rather than a copy, so that CSE will
eliminate redundant moves to the m0 register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222584
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Tom Stellard [Fri, 21 Nov 2014 22:31:44 +0000 (22:31 +0000)]
R600/SI: Emit s_mov_b32 m0, -1 before every DS instruction
This s_mov_b32 will write to a virtual register from the M0Reg
class and all the ds instructions now take an extra M0Reg explicit
argument.
This change is necessary to prevent issues with the scheduler
mixing together instructions that expect different values in the m0
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222583
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Tom Stellard [Fri, 21 Nov 2014 22:06:37 +0000 (22:06 +0000)]
R600/SI: Add SIFoldOperands pass
This pass attempts to fold the source operands of mov and copy
instructions into their uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222581
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Jozef Kolek [Fri, 21 Nov 2014 22:04:35 +0000 (22:04 +0000)]
[mips][microMIPS] This patch implements functionality in MIPS delay slot
filler such as if delay slot filler have to put NOP instruction into the
delay slot of microMIPS BEQ or BNE instruction which uses the register $0,
then instead of emitting NOP this instruction is replaced by the corresponding
microMIPS compact branch instruction, i.e. BEQZC or BNEZC.
Differential Revision: http://reviews.llvm.org/D3566
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222580
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Tom Stellard [Fri, 21 Nov 2014 22:00:16 +0000 (22:00 +0000)]
R600/SI: Mark s_mov_b32 and s_mov_b64 as rematerializable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222579
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Tom Stellard [Fri, 21 Nov 2014 22:00:13 +0000 (22:00 +0000)]
R600/SI: Use hex notation for constant in test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222578
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Colin LeMahieu [Fri, 21 Nov 2014 21:54:59 +0000 (21:54 +0000)]
[Hexagon] Adding sxth instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222577
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Colin LeMahieu [Fri, 21 Nov 2014 21:35:52 +0000 (21:35 +0000)]
[Hexagon] Adding sxtb instruction. Renaming some identically named classes that will be removed after converting referencing defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222575
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Kostya Serebryany [Fri, 21 Nov 2014 21:25:18 +0000 (21:25 +0000)]
[asan] add statistic counter to dynamic alloca instrumentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222573
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Colin LeMahieu [Fri, 21 Nov 2014 21:19:18 +0000 (21:19 +0000)]
[Hexagon] Removing SUB_rr and replacing with A2_sub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222571
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Tim Northover [Fri, 21 Nov 2014 20:16:09 +0000 (20:16 +0000)]
Remove duplication of relocation names in lib/Object/ELFYAML.cpp
We can now use the ELF relocation .def files to create the mapping
of relocation numbers to names and avoid having to duplicate the
list of relocations.
Patch by Will Newton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222567
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Tim Northover [Fri, 21 Nov 2014 20:16:07 +0000 (20:16 +0000)]
Remove duplication of relocation names in lib/Object/ELF.cpp
We can now use the ELF relocation .def files to create the mapping
of relocation numbers to names and avoid having to duplicate the
list of relocations.
Patch by Will Newton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222566
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Tim Northover [Fri, 21 Nov 2014 20:16:02 +0000 (20:16 +0000)]
Split ELF relocation defintions into per-architecture .def files
This should allow the list of relocations for a particular
architecture to be kept in a single header rather than duplicated
whenever we need to enumerate all the relocations.
Patch by Will Newton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222565
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Manman Ren [Fri, 21 Nov 2014 19:55:23 +0000 (19:55 +0000)]
Debug Info: revert r222195, r222210 and r222239.
This is no longer needed after David's fix at r222377 + r222485.
rdar://
18958417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222563
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Roman Divacky [Fri, 21 Nov 2014 19:53:24 +0000 (19:53 +0000)]
Disable header duplication at -Oz in loop-rotate pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222562
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Manman Ren [Fri, 21 Nov 2014 19:47:48 +0000 (19:47 +0000)]
Debug Info: add an assertion that the context field of a global variable can not
be a DIType with identifier.
This makes sure that there is no need to use DIScopeRef for global variable's
context.
rdar://
18958417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222561
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Manman Ren [Fri, 21 Nov 2014 19:24:55 +0000 (19:24 +0000)]
[Objective-C] Support a new special module flag that will be put into the
objc_imageinfo struct.
rdar://
17954668
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222558
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Hans Wennborg [Fri, 21 Nov 2014 19:07:46 +0000 (19:07 +0000)]
LazyValueInfo: range'ify some for-loops. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222557
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Rafael Espindola [Fri, 21 Nov 2014 19:03:35 +0000 (19:03 +0000)]
Add params() to FunctionType. NFC.
While at it, also use makeArrayRef in elements().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222556
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Sanjay Patel [Fri, 21 Nov 2014 18:58:38 +0000 (18:58 +0000)]
Don't repeat class/function/variable names in comments. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222555
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Hans Wennborg [Fri, 21 Nov 2014 18:58:23 +0000 (18:58 +0000)]
LazyValueInfo: fix some typos and indentation, etc. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222554
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Rafael Espindola [Fri, 21 Nov 2014 18:53:05 +0000 (18:53 +0000)]
Add and use a helper elements() to StructType. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222553
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Matthias Braun [Fri, 21 Nov 2014 18:06:09 +0000 (18:06 +0000)]
Allow multiple -debug-only args
Debug output is shown if any of the -debug-only arguments match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222547
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Sanjay Patel [Fri, 21 Nov 2014 18:05:59 +0000 (18:05 +0000)]
Less space; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222546
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Rafael Espindola [Fri, 21 Nov 2014 18:05:55 +0000 (18:05 +0000)]
Fix formatting. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222545
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Sanjay Patel [Fri, 21 Nov 2014 17:40:04 +0000 (17:40 +0000)]
Add a feature flag for slow 32-byte unaligned memory accesses [x86].
This patch adds a feature flag to avoid unaligned 32-byte load/store AVX codegen
for Sandy Bridge and Ivy Bridge. There is no functionality change intended for
those chips. Previously, the absence of AVX2 was being used as a proxy to detect
this feature. But that hindered codegen for AVX-enabled AMD chips such as btver2
that do not have the 32-byte unaligned access slowdown.
Performance measurements are included in PR21541 ( http://llvm.org/bugs/show_bug.cgi?id=21541 ).
Differential Revision: http://reviews.llvm.org/D6355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222544
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Duncan P. N. Exon Smith [Fri, 21 Nov 2014 17:21:18 +0000 (17:21 +0000)]
Revert "Allow FDE references outside the +/-2GB range supported by PC relative offsets for code models other than small/medium. For JIT application, memory layout is less controlled and can result in truncations otherwise."
This reverts commit r222538.
It's causing test failures for CFI, at least on Darwin:
http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental/1189/
http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_check/1391/
Note that the previous incremental build was on r222537, and the CFI
tests weren't failing:
http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental/1188/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222542
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Chandler Carruth [Fri, 21 Nov 2014 14:53:03 +0000 (14:53 +0000)]
[x86] Restructure the checking patterns for v16 and v32 avx2 vector
shuffle lowering to allow much better blend matching.
Specifically, with the new structure the code seems clearer to me and we
correctly can hit the cases where merging two 128-bit lanes is a clear
win and can be shuffled cheaply afterward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222539
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Joerg Sonnenberger [Fri, 21 Nov 2014 14:42:43 +0000 (14:42 +0000)]
Allow FDE references outside the +/-2GB range supported by PC relative
offsets for code models other than small/medium. For JIT application,
memory layout is less controlled and can result in truncations
otherwise.
Patch from Akos Kiss.
Differential Revision: http://reviews.llvm.org/D6079
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222538
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Chandler Carruth [Fri, 21 Nov 2014 14:33:24 +0000 (14:33 +0000)]
[x86] Make the previous logic significantly less conservative and get
a bunch more improvements.
Non-lane-crossing is fine, the key is that lane merging only makes sense
for single-input shuffles. Not sure why I got so turned around here. The
code all works, I was just using the wrong model for it.
This only updates v4 and v8 lowering. The v16 and v32 lowering requires
restructuring the entire check sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222537
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Andrea Di Biagio [Fri, 21 Nov 2014 14:32:06 +0000 (14:32 +0000)]
[DAG] Teach how to turn a build_vector into a shuffle if some of the operands are zero.
Before this patch, the DAGCombiner only tried to convert build_vector dag nodes
into shuffles if all operands were either extract_vector_elt or undef.
This patch improves that logic and teaches the DAGCombiner how to deal with
build_vector dag nodes where one or more operands are zero. A build_vector
dag node with some zero operands is turned into a shuffle only if the resulting
shuffle mask is legal for the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222536
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Chandler Carruth [Fri, 21 Nov 2014 13:56:05 +0000 (13:56 +0000)]
[x86] Teach the x86 vector shuffle lowering to detect mergable 128-bit
lanes.
By special casing these we can often either reduce the total number of
shuffles significantly or reduce the number of (high latency on Haswell)
AVX2 shuffles that potentially cross 128-bit lanes. Even when these
don't actually cross lanes, they have much higher latency to support
that. Doing two of them and a blend is worse than doing a single insert
across the 128-bit lanes to blend and then doing a single interleaved
shuffle.
While this seems like a narrow case, it kept cropping up on me and the
difference is *huge* as you can see in many of the test cases. I first
hit this trying to perfectly fix the interleaving shuffle patterns used
by Halide for AVX2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222533
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Chandler Carruth [Fri, 21 Nov 2014 12:33:46 +0000 (12:33 +0000)]
[x86] Remove more windows line endings that slipped into this file...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222528
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Chandler Carruth [Fri, 21 Nov 2014 12:17:50 +0000 (12:17 +0000)]
[x86] Add a bunch of test cases to 256-bit shuffles that exercise
merging 128-bit subvectors and also shuffling all the elements of those
subvectors. Currently we generate pretty bad code for many of these, but
I'm testing a patch that should dramatically improve this in addition to
making the shuffle lowering robust to other changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222525
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Andrea Di Biagio [Fri, 21 Nov 2014 11:33:07 +0000 (11:33 +0000)]
[DAG] Refactor the shuffle combining logic in DAGCombiner. NFC.
This patch simplifies the logic that combines a pair of shuffle nodes into
a single shuffle if there is a legal mask. Also added comments to better
describe the algorithm. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222522
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Alexey Volkov [Fri, 21 Nov 2014 11:19:34 +0000 (11:19 +0000)]
[X86] For Silvermont CPU use 16-bit division instead of 64-bit for small positive numbers
Differential Revision: http://reviews.llvm.org/D5938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222521
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Yury Gribov [Fri, 21 Nov 2014 10:29:50 +0000 (10:29 +0000)]
[asan] Add new hidden compile-time flag asan-instrument-allocas to sanitize variable-sized dynamic allocas. Patch by Max Ostapenko.
Reviewed at http://reviews.llvm.org/D6055
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222519
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NAKAMURA Takumi [Fri, 21 Nov 2014 09:14:45 +0000 (09:14 +0000)]
Add LLVMScalarOpts to LLVMPowerPCCodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222516
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Hao Liu [Fri, 21 Nov 2014 06:39:58 +0000 (06:39 +0000)]
DAGCombiner: Allow the DAGCombiner to combine multiple FDIVs with the same divisor info FMULs by the reciprocal.
E.g., ( a / D; b / D ) -> ( recip = 1.0 / D; a * recip; b * recip)
A hook is added to allow the target to control whether it needs to do such combine.
Reviewed in http://reviews.llvm.org/D6334
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222510
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Craig Topper [Fri, 21 Nov 2014 05:58:21 +0000 (05:58 +0000)]
Remove a bunch of unnecessary typecasts to 'const TargetRegisterClass *'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222509
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Craig Topper [Fri, 21 Nov 2014 05:58:14 +0000 (05:58 +0000)]
Add extra new line and remove some trailing whitespace from tablegen RegisterInfo output file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222508
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Rafael Espindola [Fri, 21 Nov 2014 05:15:41 +0000 (05:15 +0000)]
Fix a silly bug in StreamingMemoryObject.cpp.
The logic for detecting EOF was wrong and would fail if we ever requested
more than 16k past the last read position.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222505
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Hal Finkel [Fri, 21 Nov 2014 04:35:51 +0000 (04:35 +0000)]
[PPC] Use SeparateConstOffsetFromGEP
This mirrors r222331, which enabled SeparateConstOffsetFromGEP on AArch64, in
the PowerPC backend. Yields, on a POWER7 machine, a 30% speedup on
SingleSource/Benchmarks/Shootout/nestedloop (this might just be from LICM,
there is a store moved out of the inner loop) and a potential speedup on
MultiSource/Benchmarks/mediabench/mpeg2/mpeg2dec/mpeg2decode. Regardless, it
makes some code look cleaner, and synchronizing the backends in this regard
seems like a generally good thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222504
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Richard Trieu [Fri, 21 Nov 2014 02:42:08 +0000 (02:42 +0000)]
Add accessor marcos to ConstantPlaceHolder, similar to those in the base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222502
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