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Tim Northover [Mon, 20 Mar 2017 16:52:08 +0000 (16:52 +0000)]
GlobalISel: allow quad-precision values to be dumped.
Otherwise the fallback path fails with an assertion on AAPCS AArch64 targets,
when "long double" is encountered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298273
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Peter Collingbourne [Mon, 20 Mar 2017 16:41:57 +0000 (16:41 +0000)]
Support, LTO: When pruning a directory, ignore files matching a prefix.
This is a safeguard against data loss if the user specifies a directory
that is not a cache directory. Teach the existing cache pruning clients
to create files with appropriate names.
Differential Revision: https://reviews.llvm.org/D31109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298271
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Dehao Chen [Mon, 20 Mar 2017 16:40:44 +0000 (16:40 +0000)]
Updates branch_weights annotation for call instructions during inlining.
Summary: Inliner should update the branch_weights annotation to scale it to proper value.
Reviewers: davidxl, eraman
Reviewed By: eraman
Subscribers: zzheng, llvm-commits
Differential Revision: https://reviews.llvm.org/D30767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298270
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Adrian Prantl [Mon, 20 Mar 2017 16:39:41 +0000 (16:39 +0000)]
Use isa<> instead of dyn_cast<> (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298268
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David Blaikie [Mon, 20 Mar 2017 16:35:33 +0000 (16:35 +0000)]
Avoid potential ADL ambiguity between llvm::make_unique and std::make_unique (when building as C++14+)
Patch by Moritz Kiefer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298266
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Dmitry Preobrazhensky [Mon, 20 Mar 2017 16:33:20 +0000 (16:33 +0000)]
[AMDGPU][MC] Fix for Bugs 28201, 28199, 28170 + LIT tests
This fix enables sp3 abs modifier with constants
Reviewers: artem.tamazov
Differential Revision: https://reviews.llvm.org/D30825
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298265
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Craig Topper [Mon, 20 Mar 2017 16:31:14 +0000 (16:31 +0000)]
[InstCombine] Print a debug message when we constant fold an operand during worklist creation
InstCombine tries to constant fold instruction operands during worklist building, but we don't print that we're doing this.
We also set a change flag here that causes us to rebuild and rerun the worklist one more time even if processing the worklist itself created no additional changes. So in the log I saw two inst combine runs that visited all instructions without printing that anything was changed. I may be submitting another patch to remove the change flag unless I can find some reason why we should be doing that.
Differential Revision: https://reviews.llvm.org/D31091
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298264
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Jessica Paquette [Mon, 20 Mar 2017 16:25:04 +0000 (16:25 +0000)]
[Outliner] ACTUALLY remove the errs output
I don't know how to type. This fixes the last commit which would have made all
of the overflows legal, and kept the screaming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298263
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Daniel Berlin [Mon, 20 Mar 2017 16:08:29 +0000 (16:08 +0000)]
Templatize parts of VNCoercion, and add constant-only versions of the functions to be used in NewGVN.
NFCI.
Summary:
This is ground work for the changes to enable coercion in NewGVN.
GVN doesn't care if they end up constant because it eliminates as it goes.
NewGVN cares.
IRBuilder and ConstantFolder deliberately present the same interface,
so we use this to our advantage to templatize our functions to make
them either constant only or not.
Reviewers: davide
Subscribers: llvm-commits, Prazek
Differential Revision: https://reviews.llvm.org/D30928
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298262
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Jessica Paquette [Mon, 20 Mar 2017 15:51:45 +0000 (15:51 +0000)]
[Outliner] Remove output for offset range check
Forgot to remove some output before committing last time. (Instruction fixups
don't actually overflow anywhere in the test suite so far, so I missed it).
To prevent the outliner from screaming "Overflow!" in the event that that
does happen, this commit removes that output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298260
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Daniel Sanders [Mon, 20 Mar 2017 15:20:42 +0000 (15:20 +0000)]
[tablegen][globalisel] Capture instructions into locals and related infrastructure for multiple instructions matches.
Summary:
Prepare the way for nested instruction matching support by having actions
like CopyRenderer look up operands in the RuleMatcher rather than a
specific InstructionMatcher. This allows actions to reference any operand
from any matched instruction.
It works by checking the 'shape' of the match and capturing
each matched instruction to a local variable. If the shape is wrong
(not enough operands, leaf nodes where non-leafs are expected, etc.), then
the rule exits early without checking the predicates. Once we've captured
the instructions, we then test the predicates as before (except using the
local variables). If the match is successful, then we render the new
instruction as before using the local variables.
It's not noticable in this patch but by the time we support multiple
instruction matching, this patch will also cause a significant improvement
to readability of the emitted code since
MRI.getVRegDef(I->getOperand(0).getReg()) will simply be MI1 after
emitCxxCaptureStmts().
This isn't quite NFC because I've also fixed a bug that I'm surprised we
haven't encountered yet. It now checks there are at least the expected
number of operands before accessing them with getOperand().
Depends on D30531
Reviewers: t.p.northover, qcolombet, aditya_nandakumar, ab, rovka
Reviewed By: rovka
Subscribers: dberris, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D30535
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298257
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Dmitry Preobrazhensky [Mon, 20 Mar 2017 14:50:35 +0000 (14:50 +0000)]
[AMDGPU][MC] Fix for Bugs 28200, 28202 + LIT tests
Fixed several related issues with VOP3 fp modifiers.
Reviewers: artem.tamazov
Differential Revision: https://reviews.llvm.org/D30821
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298255
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Diana Picus [Mon, 20 Mar 2017 14:40:18 +0000 (14:40 +0000)]
[GlobalISel] Use the correct calling conv for calls
This commit adds a parameter that lets us pass in the calling convention
of the call to CallLowering::lowerCall. This allows us to handle
situations where the calling convetion of the callee is different from
that of the caller.
Differential Revision: https://reviews.llvm.org/D31039
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298254
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Simon Pilgrim [Mon, 20 Mar 2017 14:40:12 +0000 (14:40 +0000)]
Use MutableArrayRef for APFloat::convertToInteger
As discussed on D31074, use MutableArrayRef for destination integer buffers to help assert before stack overflows happen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298253
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Maxim Ostapenko [Mon, 20 Mar 2017 14:06:04 +0000 (14:06 +0000)]
[sancov] Fix broken links and displaced coloring in coverage-report-server.py
This patch fixes two issues:
* Fixed relative links to source files
* Enumeration of lines in source files starts from 1 instead of 0 to
align with .symcov files generated by sancov -symbolize
Patch by Dmitiriy Nikiforov.
Differential Revision: https://reviews.llvm.org/D31038
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298250
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Simon Pilgrim [Mon, 20 Mar 2017 13:55:35 +0000 (13:55 +0000)]
Strip trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298249
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Simon Pilgrim [Mon, 20 Mar 2017 13:54:44 +0000 (13:54 +0000)]
Strip trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298248
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Simon Pilgrim [Mon, 20 Mar 2017 13:53:59 +0000 (13:53 +0000)]
Strip trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298247
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Konstantin Zhuravlyov [Mon, 20 Mar 2017 09:26:08 +0000 (09:26 +0000)]
Revert "[AMDGPU] Run always inliner early in opt"
This reverts commit r297958, it breaks device-libs build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298239
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Craig Topper [Mon, 20 Mar 2017 06:40:39 +0000 (06:40 +0000)]
[IR] Move a few static functions in Instruction class inline.
They just check for certain opcodes and opcode enums are available in Instruction.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298237
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Michael Zolotukhin [Mon, 20 Mar 2017 06:33:07 +0000 (06:33 +0000)]
[ConstantRange] Add setSizeSmallerThanOf method.
Summary:
ConstantRange class currently has a method getSetSize, which is mostly used to
compare set sizes of two constant ranges (there is only one spot where it's used
in a slightly different scenario). This patch introduces setSizeSmallerThanOf
method, which does such comparison in a more efficient way. In the original
method we have to extend our types to (BitWidth+1), which can result it using
slow case of APInt, extra memory allocations, etc.
The change is supposed to not change any functionality, but it slightly improves
compile time. Here is compile time improvements that I observed on CTMark:
* tramp3d-v4 -2.02%
* pairlocalalign -1.82%
* lencod -1.67%
Reviewers: sanjoy, atrick, pete
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31104
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298236
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Craig Topper [Mon, 20 Mar 2017 05:08:41 +0000 (05:08 +0000)]
[IR] Remove some unneeded includes from Operator.h and fix cpp files that were transitively depending on it. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298235
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Craig Topper [Mon, 20 Mar 2017 05:08:38 +0000 (05:08 +0000)]
[IR] Add missing copyright header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298234
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Craig Topper [Mon, 20 Mar 2017 01:29:52 +0000 (01:29 +0000)]
[APInt] Don't initialize VAL to 0 in APInt constructors. Push it down to the initSlowCase and other init methods.
I'm not sure if zeroing VAL before writing pVal is really necessary, but at least one other place did it in code.
But by taking the store out of line, this reduces the opt binary by about 20k on my local x86-64 build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298233
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Xin Tong [Mon, 20 Mar 2017 00:30:19 +0000 (00:30 +0000)]
Remove unnecessary IDom check
Summary: This Idom check seems unnecessary. The immediate children of a node on the Dominator Tree should always be the IDom of its immediate children in this case.
Reviewers: hfinkel, majnemer, dberlin
Reviewed By: dberlin
Subscribers: dberlin, davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D26954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298232
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Craig Topper [Sun, 19 Mar 2017 21:45:57 +0000 (21:45 +0000)]
[InstCombine] Remove duplicate code in SimplifyDemandedUseBits for URem. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298231
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Craig Topper [Sun, 19 Mar 2017 17:11:09 +0000 (17:11 +0000)]
[AVX-512] Handle kor/kand/kandn/kxor/kxnor/knot intrinsics at lowering time instead of isel
Summary:
Currently we handle these intrinsics at isel with special patterns. But as they just map to normal logic operations, we should just handle them at lowering. This will expose them to DAG combine optimizations. Right now the kor-sequence test generates a bunch of regclass copies between GR16 and VK16 that the peephole optimizer and/or register coallescing are removing to keep everything in the mask domain. By handling the logic op intrinsics earlier, these copies become bitcasts in the DAG and get removed by DAG combine which seems more robust.
This should help enable my plan to stop copying between K registers and GR8/GR16. The peephole optimizer can't remove a chain of copies between K and GR32 with insert_subreg/extract_subreg present in the chain so the kor-sequence test break. But this patch should dodge the problem entirely.
Reviewers: zvi, delena, RKSimon, igorb
Reviewed By: igorb
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298228
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Craig Topper [Sun, 19 Mar 2017 17:04:52 +0000 (17:04 +0000)]
[InstCombine] Use update_test_checks.py to regenerate a test. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298227
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Simon Pilgrim [Sun, 19 Mar 2017 16:50:25 +0000 (16:50 +0000)]
Fix constant folding of fp2int to large integers
We make the assumption in most of our constant folding code that a fp2int will target an integer of 128-bits or less, calling the APFloat::convertToInteger with only uint64_t[2] of raw bits for the result.
Fuzz testing (PR24662) showed that we don't handle other cases at all, resulting in stack overflows and all sorts of crashes.
This patch uses the APSInt version of APFloat::convertToInteger instead to better handle such cases.
Differential Revision: https://reviews.llvm.org/D31074
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298226
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Simon Pilgrim [Sun, 19 Mar 2017 16:39:04 +0000 (16:39 +0000)]
Fix MSVC warning: "switch statement contains 'default' but no 'case' labels". NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298225
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Ahmed Bougacha [Sun, 19 Mar 2017 16:13:00 +0000 (16:13 +0000)]
[GlobalISel] Don't select trivially dead instructions.
Folding instructions when selecting can cause them to become dead.
Don't select these dead instructions (if they don't have other side
effects, and don't define physical registers).
Preserve existing tests by adding COPYs.
In some tests, the G_CONSTANT vregs never get constrained to a class:
the only use of the vreg was folded into another instruction, so the
G_CONSTANT, now dead, never gets selected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298224
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Ahmed Bougacha [Sun, 19 Mar 2017 16:12:53 +0000 (16:12 +0000)]
[GlobalISel][AArch64] Add DBG_VALUE select test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298223
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Ahmed Bougacha [Sun, 19 Mar 2017 16:12:51 +0000 (16:12 +0000)]
[GlobalISel][AArch64] Split out cast select tests. NFC.
And remove some redundant bitcast tests.
Also split the test functions themselves: it makes it obvious to see
what's tested where and what isn't, it makes the tests much easier to
read and manually update, and, most importantly, it makes them almost
trivial to update using tooling. Yes, it's obnoxiously verbose, but
said tooling helps upgrade to better MIR syntax whenever available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298222
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Ahmed Bougacha [Sun, 19 Mar 2017 16:12:48 +0000 (16:12 +0000)]
[GlobalISel] Move method definition to the proper file. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298221
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Ahmed Bougacha [Sun, 19 Mar 2017 16:12:45 +0000 (16:12 +0000)]
[CodeGen] Update hasSideEffects comment. NFC.
We used to have 3 side effect flags, but as of r222809, we only have
hasSideEffects. Change the comment to reflect that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298220
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Xin Tong [Sun, 19 Mar 2017 15:41:46 +0000 (15:41 +0000)]
Correct a rebase mistake.
Left out AA in jumpthreading SimplifyPartiallyRedundantLoad
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298219
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Xin Tong [Sun, 19 Mar 2017 15:31:16 +0000 (15:31 +0000)]
Remove unused arguments. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298218
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Xin Tong [Sun, 19 Mar 2017 15:30:53 +0000 (15:30 +0000)]
[JumpThreading] Perform phi-translation in SimplifyPartiallyRedundantLoad.
Summary:
In case we are loading on a phi-load in SimplifyPartiallyRedundantLoad.
Try to phi translate it into incoming values in the predecessors before
we search for available loads.
This needs https://reviews.llvm.org/D30524
Reviewers: davide, sanjoy, efriedma, dberlin, rengolin
Reviewed By: dberlin
Subscribers: junbuml, llvm-commits
Differential Revision: https://reviews.llvm.org/D30543
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298217
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Xin Tong [Sun, 19 Mar 2017 15:27:52 +0000 (15:27 +0000)]
Extract FindAvailablePtrLoadStore out of FindAvailableLoadedValue. NFCI
Summary:
Extract FindAvailablePtrLoadStore out of FindAvailableLoadedValue.
Prepare for upcoming change which will do phi-translation for load on
phi pointer in jump threading SimplifyPartiallyRedundantLoad.
This is in preparation for https://reviews.llvm.org/D30543
Reviewers: efriedma, sanjoy, davide, dberlin
Reviewed By: davide
Subscribers: junbuml, davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D30524
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298216
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Teresa Johnson [Sun, 19 Mar 2017 13:54:57 +0000 (13:54 +0000)]
Enable stripping of multiple DILocation on !llvm.loop metadata
Summary:
I found that stripDebugInfo was still leaving significant amounts of
debug info due to !llvm.loop that contained DILocation after stripping.
The support for stripping debug info on !llvm.loop added in r293377 only
removes a single DILocation. Enhance that to remove all DILocation from
!llvm.loop.
Reviewers: hfinkel, aprantl, dsanders
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298213
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Oren Ben Simhon [Sun, 19 Mar 2017 13:23:20 +0000 (13:23 +0000)]
[MIR] Test assumes x64 windows calling convention upon printing/parsing MIR output/input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298212
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Benjamin Kramer [Sun, 19 Mar 2017 13:04:35 +0000 (13:04 +0000)]
[MIR] Add triple to test that assumes it runs on windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298211
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Oren Ben Simhon [Sun, 19 Mar 2017 11:18:09 +0000 (11:18 +0000)]
CalleeSavedRegister was removed from MIR and is recalculated upon MIR parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298210
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Oren Ben Simhon [Sun, 19 Mar 2017 08:53:42 +0000 (08:53 +0000)]
Moving the test to x86 because other architectures do not suport regcall calling convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298209
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Oren Ben Simhon [Sun, 19 Mar 2017 08:14:18 +0000 (08:14 +0000)]
[MIR] Support Customed Register Mask and CSRs
The MIR printer dumps a string that describe the register mask of a function.
A static predefined list of register masks matches a static list of strings.
However when the register mask is not from the static predefined list, there is no descriptor string and the printer fails.
This patch adds support to custom register mask printing and dumping.
Also the list of callee saved registers (describing the registers that must be preserved for the caller) might be dynamic.
As such this data needs to be dumped and parsed back to the Machine Register Info.
Differential Revision: https://reviews.llvm.org/D30971
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298207
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Craig Topper [Sun, 19 Mar 2017 05:49:16 +0000 (05:49 +0000)]
[InstCombine] Use setHighBits/setLowBits/setBitsFrom in place of getLowBitsSet/getHighBitsSet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298204
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Brian Gesiak [Sun, 19 Mar 2017 04:40:42 +0000 (04:40 +0000)]
[Analysis] bitreverse(undef) returns undef
Summary:
The reverse of an artbitrary bitpattern is also an arbitrary
bitpattern.
Reviewers: trentxintong, arsenm, majnemer
Reviewed By: majnemer
Subscribers: majnemer, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D31118
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298201
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Daniel Berlin [Sun, 19 Mar 2017 00:07:32 +0000 (00:07 +0000)]
NewGVN: Now that we have a better verifier, we can prove that we can erase the predicateuser set each time we mark it touched
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298199
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Daniel Berlin [Sun, 19 Mar 2017 00:07:27 +0000 (00:07 +0000)]
NewGVN: Remove dead code (for now)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298198
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Craig Topper [Sat, 18 Mar 2017 18:24:41 +0000 (18:24 +0000)]
[GVN] Fix accidental double storage of the function BasicBlock list in iterateOnFunction
Summary:
iterateOnFunction creates a ReversePostOrderTraversal object which does a post order traversal in its constructor and stores the results in an internal vector. Iteration over it just reads from the internal vector in reverse order.
The GVN code seems to be unaware of this and iterates over ReversePostOrderTraversal object and makes a copy of the vector into a local vector. (I think at one point in time we used a DFS here instead which would have required the local vector).
The net affect of this is that we have two vectors containing the basic block list. As I didn't want to expose the implementation detail of ReversePostOrderTraversal's constructor to GVN, I've changed the code to do an explicit post order traversal storing into the local vector and then reverse iterate over that.
I've also removed the reserve(256) since the ReversePostOrderTraversal wasn't doing that. I can add it back if we thinks it important. Though it seemed weird that it wasn't based on the size of the function.
Reviewers: davide, anemet, dberlin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298191
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Craig Topper [Sat, 18 Mar 2017 18:21:46 +0000 (18:21 +0000)]
[ValueTracking] Remove deadish code from computeKnownBitsAddSub.
The code assigned to KnownZero, but later code unconditionally assigned over it. I'm pretty sure the later code can handle the same cases and more equally well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298190
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Daniel Berlin [Sat, 18 Mar 2017 15:41:40 +0000 (15:41 +0000)]
NewGVN: Greatly enhance the ability of the NewGVN verifier to detect
issues, subsuming previous verifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298188
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Daniel Berlin [Sat, 18 Mar 2017 15:41:36 +0000 (15:41 +0000)]
NewGVN: Fix PHI evaluation bug exposed by new verifier. We were checking whether the incoming block was reachable instead of whether the specific edge was reachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298187
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Daniel Berlin [Sat, 18 Mar 2017 15:41:13 +0000 (15:41 +0000)]
DebugCounters: Add API for setting/unsetting programatically.
This is required so we can re-set the counter state for verifiers,
etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298186
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Matthias Braun [Sat, 18 Mar 2017 05:08:58 +0000 (05:08 +0000)]
ExecutionDepsFix: Let targets specialize the pass; NFC
Let targets specialize the pass with the register class so we can get a
parameterless default constructor and can put the pass into the pass
registry to enable testing with -run-pass=.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298184
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Matthias Braun [Sat, 18 Mar 2017 05:05:40 +0000 (05:05 +0000)]
ExecutionDepsFix: Normalize names; NFC
Normalize ExeDepsFix, execution-fix, ExecutionDependencyFix and
ExecutionDepsFix to the last one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298183
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Matthias Braun [Sat, 18 Mar 2017 05:05:32 +0000 (05:05 +0000)]
CodeGen.cpp: Sort alphabetically; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298182
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Matthias Braun [Sat, 18 Mar 2017 05:05:29 +0000 (05:05 +0000)]
InitializePasses.h: Cleanup; NFC
- Sort alphabetically
- Normalize spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298181
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Craig Topper [Sat, 18 Mar 2017 04:01:29 +0000 (04:01 +0000)]
[ValueTracking] Add APInt::setSignBit and use it to replace ORing with getSignBit which will malloc if the bit width is larger than 64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298180
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Nirav Dave [Sat, 18 Mar 2017 00:44:07 +0000 (00:44 +0000)]
Make library calls sensitive to regparm module flag (Fixes PR3997).
Reviewers: mkuper, rnk
Subscribers: mehdi_amini, jyknight, aemerson, llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D27050
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298179
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Nirav Dave [Sat, 18 Mar 2017 00:43:57 +0000 (00:43 +0000)]
Capitalize ArgListEntry fields. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298178
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Bruno Cardoso Lopes [Sat, 18 Mar 2017 00:32:34 +0000 (00:32 +0000)]
[LockFileManager] Reduce lock timeout
Go back to behavior pre-r231309 and reduce the timeout from 8 to ~1.5
min now that we have (a) PCMCache mechanism (r298165) and (b) timeout
that doesn't cause a failure, but actually build the module (r298175).
rdar://problem/
30297862
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298176
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Stanislav Mekhanoshin [Fri, 17 Mar 2017 23:56:58 +0000 (23:56 +0000)]
[AMDGPU] Add address space based alias analysis pass
This is direct port of HSAILAliasAnalysis pass, just cleaned for
style and renamed.
Differential Revision: https://reviews.llvm.org/D31103
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298172
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Craig Topper [Fri, 17 Mar 2017 23:48:02 +0000 (23:48 +0000)]
[BuildLibCalls] emitPutChar should infer function attributes for putchar
When InstCombine calls into SimplifyLibCalls and it createa putChar calls, we don't infer the attributes. And since SimplifyLibCalls doesn't use InstCombine's IRBuilder the calls doesn't end up in the worklist on this iteration of InstCombine. So it gets picked up on the next iteration where it causes an IR change. This of course causes InstCombine to run another iteration.
So this patch just gets the attributes right the first time. We already did this for puts and some other libcalls.
Differential Revision: https://reviews.llvm.org/D31094
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298171
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Sanjay Patel [Fri, 17 Mar 2017 23:04:18 +0000 (23:04 +0000)]
[x86] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298166
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Sanjay Patel [Fri, 17 Mar 2017 22:47:21 +0000 (22:47 +0000)]
[x86] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298164
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Evgeniy Stepanov [Fri, 17 Mar 2017 22:31:13 +0000 (22:31 +0000)]
Fix docs-llvm-html build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298163
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Jessica Paquette [Fri, 17 Mar 2017 22:26:55 +0000 (22:26 +0000)]
[Outliner] Add outliner for AArch64
This commit adds the necessary target hooks for outlining in AArch64. It also
refactors the switch statement used in `getMemOpBaseRegImmOfsWidth` into a
more general function, `getMemOpInfo`. This allows the outliner to share that
code without copying and pasting it.
The AArch64 outliner can be run using -mllvm -enable-machine-outliner, as with
the X86-64 outliner.
The test for this pass verifies that the outliner does, in fact outline
functions, fixes up the stack accesses properly, and can correctly generate a
tail call. In the future, this test should be replaced with a MIR test, so that
we can properly test immediate offset overflows in fixed-up instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298162
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Eli Friedman [Fri, 17 Mar 2017 22:19:52 +0000 (22:19 +0000)]
[SCEV] Use const Loop *L instead of Loop *L. NFC
Use const pointer in the trip count and trip multiple calculations.
Patch by Huihui Zhang <huihuiz@codeaurora.org>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298161
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Evgeniy Stepanov [Fri, 17 Mar 2017 22:17:29 +0000 (22:17 +0000)]
[asan] Fix dead stripping of globals on Linux.
Use a combination of !associated, comdat, @llvm.compiler.used and
custom sections to allow dead stripping of globals and their asan
metadata. Sometimes.
Currently this works on LLD, which supports SHF_LINK_ORDER with
sh_link pointing to the associated section.
This also works on BFD, which seems to treat comdats as
all-or-nothing with respect to linker GC. There is a weird quirk
where the "first" global in each link is never GC-ed because of the
section symbols.
At this moment it does not work on Gold (as in the globals are never
stripped).
Differential Revision: https://reviews.llvm.org/D30121
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298158
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Evgeniy Stepanov [Fri, 17 Mar 2017 22:17:24 +0000 (22:17 +0000)]
Add !associated metadata.
This is an ELF-specific thing that adds SHF_LINK_ORDER to the global's section
pointing to the metadata argument's section. The effect of that is a reverse dependency
between sections for the linker GC.
!associated does not change the behavior of global-dce. The global
may also need to be added to llvm.compiler.used.
Since SHF_LINK_ORDER is per-section, !associated effectively enables
fdata-sections for the affected globals, the same as comdats do.
Differential Revision: https://reviews.llvm.org/D29104
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298157
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Eli Friedman [Fri, 17 Mar 2017 22:15:50 +0000 (22:15 +0000)]
[SelectionDAG] Remove redundant stores more aggressively.
Handle TokenFactors more aggressively in
SDValue::reachesChainWithoutSideEffects. This isn't really a
very effective change anymore because of other changes to
chain handling, but it's a cheap check, and the expanded
comments are still useful.
It might be possible to loosen the hasOneUse() requirement with a
deeper analysis, but a naive implementation of that check would be
expensive.
Differential Revision: https://reviews.llvm.org/D29845
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298156
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Peter Collingbourne [Fri, 17 Mar 2017 21:49:09 +0000 (21:49 +0000)]
LTO: Work around libstdc++ version mismatch bug, see D31063 review thread.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298127
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Matt Arsenault [Fri, 17 Mar 2017 21:36:28 +0000 (21:36 +0000)]
AMDGPU: Fix broken condition in hazard recognizer
Fixes bug 32248.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298125
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Vassil Vassilev [Fri, 17 Mar 2017 20:58:08 +0000 (20:58 +0000)]
[coverity] Fix uninit variable.
Patch by John Harvey!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298122
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Matt Arsenault [Fri, 17 Mar 2017 20:52:21 +0000 (20:52 +0000)]
AMDGPU: Fix handling of constant phi input loop conditions
If the loop condition was an i1 phi with a constantexpr input, this
would add a loop intrinsic fed by a phi dependent on a call to
if.break in the same block. Insert the call in the loop header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298121
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Rong Xu [Fri, 17 Mar 2017 20:51:44 +0000 (20:51 +0000)]
[PGO] Change the internal options description. nfc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298120
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Matt Arsenault [Fri, 17 Mar 2017 20:41:45 +0000 (20:41 +0000)]
AMDGPU: Cleanup control flow intrinsics
Move backend internal intrinsics along with the rest of the
normal intrinsics, and use the Intrinsic::getDeclaration
API instead of manually constructing the type list.
It's surprising this was working before. fdiv.fast had
the wrong number of parameters. The control flow intrinsic
declaration attributes were not being applied, and
their types were inconsistent. The actual IR use types
did not match the declaration, and were closer to the
types used for the patterns. The brcond lowering
was changing the types, so introduce new nodes for those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298119
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Sanjay Patel [Fri, 17 Mar 2017 20:29:40 +0000 (20:29 +0000)]
[x86] clean up setcc with negated operand transform and add missing test; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298118
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Reid Kleckner [Fri, 17 Mar 2017 20:25:49 +0000 (20:25 +0000)]
[X86] Emit fewer instructions to allocate >16GB stack frames
Summary:
Use this code pattern when RAX is live, instead of emitting up to 2
billion adjustments:
pushq %rax
movabsq +-$Offset+-8, %rax
addq %rsp, %rax
xchg %rax, (%rsp)
movq (%rsp), %rsp
Try to clean this code up a bit while I'm here. In particular, hoist the
logic that handles the entire adjustment with `movabsq $imm, %rax` out
of the loop.
This negates the offset in the prologue and uses ADD because X86 only
has a two operand subtract which always subtracts from the destination
register, which can no longer be RSP.
Fixes PR31962
Reviewers: majnemer, sdardis
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30052
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298116
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Rong Xu [Fri, 17 Mar 2017 20:05:13 +0000 (20:05 +0000)]
[PGO] Add omitted test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298115
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Jun Bum Lim [Fri, 17 Mar 2017 19:05:21 +0000 (19:05 +0000)]
[CodeGenPrep]Restructure promoting Ext to form ExtLoad
Summary:
Instead of just looking for a load which is mergable with Ext to form ExtLoad, trying to promote Exts as long as the cost is acceptable. This change is not a NFC as it continue promoting Exts even after finding a load during promotions; the change in arm64-codegen-prepare-extload.ll described in 2.b might show the case.
This change was motivated from D26524. Based on this change, I will move the transformation performed in aarch64-type-promotion into CGP.
Reviewers: jmolloy, qcolombet, mcrosier, javed.absar
Reviewed By: qcolombet
Subscribers: rengolin, llvm-commits, aemerson
Differential Revision: https://reviews.llvm.org/D27853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298114
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Rong Xu [Fri, 17 Mar 2017 18:07:26 +0000 (18:07 +0000)]
[PGO] Value profile for size of memory intrinsic calls
This patch annotates the valuesites profile to memory intrinsics.
Differential Revision: http://reviews.llvm.org/D31002
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298110
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Vedant Kumar [Fri, 17 Mar 2017 17:53:26 +0000 (17:53 +0000)]
[Bitcode] Add compatibility test for the 4.0 release
Fork off compatibility.ll for the 4.0 release. The *.bc file in this
commit was produced using a Release build of the release_40 branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298109
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Simon Pilgrim [Fri, 17 Mar 2017 17:45:36 +0000 (17:45 +0000)]
[SelectionDAG] Add SelectionDAG.computeKnownBits test support for ISD::ABS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298108
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Sanjay Patel [Fri, 17 Mar 2017 17:27:31 +0000 (17:27 +0000)]
[x86] avoid adc/sbb assert when both sides of add are zexted (PR32316)
As noted in the comment, we might want to account for this case,
but I didn't look at what that would mean for the asm.
I'm also not sure why this only reproduces with avx512, but I'm
putting a conservative fix in for now to avoid the crash.
Also, if both sides of an add are zexted, shouldn't we shrink that add?
https://bugs.llvm.org/show_bug.cgi?id=32316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298107
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Reid Kleckner [Fri, 17 Mar 2017 17:24:03 +0000 (17:24 +0000)]
Fix wasm build after arg_begin iterator type change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298106
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Reid Kleckner [Fri, 17 Mar 2017 17:16:39 +0000 (17:16 +0000)]
Store Arguments in a flat array instead of an iplist
This saves two pointers from Argument and eliminates some extra
allocations.
Arguments cannot be inserted or removed from a Function because that
would require changing its Type, which LLVM does not allow. Instead,
passes that change prototypes, like DeadArgElim, create a new Function
and copy over argument names and attributes. The primary benefit of
iplist is O(1) random insertion and removal. We just don't need that for
arguments, so don't use it.
Reviewed By: chandlerc
Subscribers: dlj, inglorion, llvm-commits
Differential Revision: https://reviews.llvm.org/D31058
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298105
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Stanislav Mekhanoshin [Fri, 17 Mar 2017 17:13:41 +0000 (17:13 +0000)]
Only unswitch loops with uniform conditions
Loop unswitching can be extremely harmful for a SIMT target. In case
if hoisted condition is not uniform a SIMT machine will execute both
clones of a loop sequentially. Therefor LoopUnswitch checks if the
condition is non-divergent.
Since DivergenceAnalysis adds an expensive PostDominatorTree analysis
not needed for non-SIMT targets a new option is added to avoid unneded
analysis initialization. The method getAnalysisUsage is called when
TargetTransformInfo is not yet available and we cannot use it here.
For that reason a new field DivergentTarget is added to PassManagerBuilder
to control the behavior and set this field from a target.
Differential Revision: https://reviews.llvm.org/D30796
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298104
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Simon Pilgrim [Fri, 17 Mar 2017 16:58:15 +0000 (16:58 +0000)]
[X86] Add SelectionDAG.computeKnownBits test showing inability to handle ISD::ABS
We have to be careful as abs(INT_MIN) == INT_MIN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298103
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Chad Rosier [Fri, 17 Mar 2017 14:19:55 +0000 (14:19 +0000)]
[AArch64] Use alias analysis in the load/store optimization pass.
This allows the optimization to rearrange loads and stores more aggressively.
Differential Revision: http://reviews.llvm.org/D30903
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298092
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Oliver Stannard [Fri, 17 Mar 2017 11:10:17 +0000 (11:10 +0000)]
[Asm] Don't list '@<type>' in diag when '@' is a comment
This fixes https://bugs.llvm.org//show_bug.cgi?id=31280
Differential revision: https://reviews.llvm.org/D31026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298067
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Andre Vieira [Fri, 17 Mar 2017 09:37:10 +0000 (09:37 +0000)]
[ARM] Fix triple format in test branch disassemble test
Fixing triple format in the tests added for the branch label fix for Thumb
Targets. Also recommitting previously approved patch, see
https://reviews.llvm.org/D30943.
Reviewed by: samparker
Differential Revision: https://reviews.llvm.org/D30987
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298056
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Craig Topper [Fri, 17 Mar 2017 07:37:31 +0000 (07:37 +0000)]
[AVX-512] Make VEX encoded FMA instructions available when AVX512 is enabled regardless of whether +fma was added on the command line.
We weren't able to handle isel of the 128/256-bit FMA instructions when AVX512F was enabled but VLX and FMA weren't.
I didn't mask FeatureAVX512 imply FeatureFMA as I wasn't sure I wanted disabling FMA to also disable AVX512. Instead we just can't prevent FMA instructions if AVX512 is enabled.
Another option would be to promote 128/256-bit to 512-bit, do the operation and extract it. But that requires a lot of extra isel patterns. Since no CPUs exist that support AVX512, but not FMA just using the VEX instructions seems better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298051
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Craig Topper [Fri, 17 Mar 2017 07:37:27 +0000 (07:37 +0000)]
[X86] Remove unused predicate. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298050
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Jonas Paulsson [Fri, 17 Mar 2017 07:11:46 +0000 (07:11 +0000)]
[SystemZ] New CodeGen tests for vector compare / select.
New SystemZ tests for the improved codegen of vector compare and select,
including cases with a logical combination of two compares.
Review: Ulrich Weigand.
https://reviews.llvm.org/D29489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298049
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Jonas Paulsson [Fri, 17 Mar 2017 07:11:42 +0000 (07:11 +0000)]
Add SystemZ to utils/update_llc_test_checks.py.
Extend script for auto-generating CHECK lines so that it works for SystemZ.
This is a pre-commit for the new tests resulting from
https://reviews.llvm.org/D29489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298048
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Jonas Paulsson [Fri, 17 Mar 2017 06:47:08 +0000 (06:47 +0000)]
[SystemZ] Add use of super-reg in splitMove()
If one of the subregs of the 128 bit reg is undefined when splitMove() splits
a store into two instructions, a use of an undefined physical register
results.
To remedy this, an implicit use of the super register is added onto both new
instructions, along with propagated kill and undef flags.
This was discovered with llvm-stress, and that test case is attached as
test/CodeGen/SystemZ/splitMove_undefReg_mverifier.ll
Thanks to Matthias Braun for helping with a nice explanation.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298047
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Craig Topper [Fri, 17 Mar 2017 06:10:37 +0000 (06:10 +0000)]
[AVX-512] Give priority to EVEX encoded scalar FMA instructions when we have FMA, AVX512 and no VLX.
We were giving priority if VLX was enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298046
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Craig Topper [Fri, 17 Mar 2017 06:00:01 +0000 (06:00 +0000)]
[X86] Use update_llc_test_checks.py to regenerate a test and add command lines to demonstrate that we don't pick EVEX encoded instruction when AVX512 and FMA3 are both enabled.
This bug only exists on the scalar llvm.fma instrinsics. Looks like we don't test the llvm.fma intrinsics very thoroughly. In fact I don't see any tests for the vector versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298045
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