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Hiroshi Inoue [Mon, 5 Feb 2018 12:25:29 +0000 (12:25 +0000)]
[PowerPC] Check hot loop exit edge in PPCCTRLoops
PPCCTRLoops transform loops using mtctr/bdnz instructions if loop trip count is known and big enough to compensate for the cost of mtctr.
But if there is a loop exit edge which is known to be frequently taken (by builtin_expect or by PGO), we should not transform the loop to avoid the cost of mtctr instruction. Here is an example of a loop with hot exit edge:
for (unsigned i = 0; i < TripCount; i++) {
// do something
if (__builtin_expect(check(), 1))
break;
// do something
}
Differential Revision: https://reviews.llvm.org/D42637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324229
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Clement Courbet [Mon, 5 Feb 2018 12:23:51 +0000 (12:23 +0000)]
[CodeGenSchedule][NFC] Always emit ProcResourceUnits.
Summary:
Right now only the ProcResourceUnits that are directly referenced by
instructions are emitted. This change emits all of them, so that
analysis passes can use the information.
This has no functional impact. It typically adds a few entries (e.g. 4
for X86/haswell) to the generated ProcRes table.
Reviewers: gchatelet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42903
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324228
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Igor Laevsky [Mon, 5 Feb 2018 11:05:47 +0000 (11:05 +0000)]
[llvm-opt-fuzzer] Avoid adding incorrect inputs to the fuzzer corpus
Differential Revision: https://reviews.llvm.org/D42414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324225
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James Henderson [Mon, 5 Feb 2018 10:47:13 +0000 (10:47 +0000)]
Fix more print format specifiers in debug_rnglists dumping
See also r324096.
I have made the assumption that DWARF64 is not an issue for the time
being with these fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324223
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Serguei Katkov [Mon, 5 Feb 2018 09:05:43 +0000 (09:05 +0000)]
Revert [SimplifyCFG] Relax restriction for folding unconditional branches
The patch causes the failure of the test
compiler-rt/test/profile/Linux/counter_promo_nest.c
To unblock buildbot, revert the patch while investigation is in progress.
Differential Revision: https://reviews.llvm.org/D42691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324214
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Craig Topper [Mon, 5 Feb 2018 08:37:37 +0000 (08:37 +0000)]
[X86] Add isel patterns for selecting masked SUBV_BROADCAST with bitcasts. Remove combineBitcastForMaskedOp.
Add test cases for the merge masked versions to make sure we have all those covered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324210
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Max Kazantsev [Mon, 5 Feb 2018 08:09:49 +0000 (08:09 +0000)]
[NFC] Add tests for PR35743
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324209
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Serguei Katkov [Mon, 5 Feb 2018 07:56:43 +0000 (07:56 +0000)]
[SimplifyCFG] Relax restriction for folding unconditional branches
The commit rL308422 introduces a restriction for folding unconditional
branches. Specifically if empty block with unconditional branch leads to
header of the loop then elimination of this basic block is prohibited.
However it seems this condition is redundantly strict.
If elimination of this basic block does not introduce more back edges
then we can eliminate this block.
The patch implements this relax of restriction.
Reviewers: efriedma, mcrosier, pacxx, hsung, davidxl
Reviewed By: pacxx
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324208
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Craig Topper [Mon, 5 Feb 2018 06:56:33 +0000 (06:56 +0000)]
[X86] Remove unused lambda. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324206
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Craig Topper [Mon, 5 Feb 2018 06:00:23 +0000 (06:00 +0000)]
[X86] Remove X86ISD::SHUF128 from combineBitcastForMaskedOp. Use isel patterns instead.
We always created X86ISD::SHUF128 with a 64-bit element type so we can use isel patterns to detect a bitconvert to 32-bit to handle masking.
The test changes are because we also match the bitconvert even if there is no masking. This leads to unnecessary isel pattern, but it requires more multiclass hackery in tablegen to get rid of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324205
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Serguei Katkov [Mon, 5 Feb 2018 05:49:47 +0000 (05:49 +0000)]
Re-apply [SCEV] Fix isLoopEntryGuardedByCond usage
ScalarEvolution::isKnownPredicate invokes isLoopEntryGuardedByCond without check
that SCEV is available at entry point of the loop. It is incorrect and fixed by patch.
To bugs additionally fixed:
assert is moved after the check whether loop is not a nullptr.
Usage of isLoopEntryGuardedByCond in ScalarEvolution::isImpliedCondOperandsViaNoOverflow
is guarded by isAvailableAtLoopEntry.
Reviewers: sanjoy, mkazantsev, anna, dorit, reames
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324204
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Craig Topper [Sun, 4 Feb 2018 23:48:51 +0000 (23:48 +0000)]
[X86] Auto-generate full checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324202
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Zvi Rackover [Sun, 4 Feb 2018 19:31:14 +0000 (19:31 +0000)]
X86 Tests: Add shuffle that can be improved by widening elements. NFC
To be improved by D42044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324200
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Florian Hahn [Sun, 4 Feb 2018 18:40:24 +0000 (18:40 +0000)]
[PartialInliner] Update test (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324199
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Florian Hahn [Sun, 4 Feb 2018 18:27:47 +0000 (18:27 +0000)]
[InlineFunction] Set arg attrs even if there only are VarArg attrs.
When using the partial inliner, we might have attributes for forwarded
varargs, but the CodeExtractor does not create an empty argument
attribute set for regular arguments in that case, because it does not know
of the additional arguments. So in case we have attributes for VarArgs, we
also have to make sure we create (empty) attributes for all regular arguments.
This fixes PR36210.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324197
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Sander de Smalen [Sun, 4 Feb 2018 16:24:17 +0000 (16:24 +0000)]
[TableGen][AsmMatcherEmitter] Fix tied-constraint checking for InstAliases
Summary:
This is a bit of a reimplementation the work done in
https://reviews.llvm.org/D41446, since that patch only really works for
tied operands of instructions, not aliases.
Instead of checking the constraints based on the matched instruction's opcode,
this patch uses the match-info's convert function to check the operand
constraints for that specific instruction/alias.
This is based on the matched operands for the instruction, not the
resulting opcode of the MCInst.
This patch adds the following enum/table to the *GenAsmMatcher.inc file:
enum {
Tie0_1_1,
Tie0_1_2,
Tie0_1_5,
...
};
const char TiedAsmOperandTable[][3] = {
/* Tie0_1_1 */ { 0, 1, 1 },
/* Tie0_1_2 */ { 0, 1, 2 },
/* Tie0_1_5 */ { 0, 1, 5 },
...
};
And it is referenced directly in the ConversionTable, like this:
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][13] = {
...
{ CVT_95_addRegOperands, 1,
CVT_95_addRegOperands, 2,
CVT_Tied, Tie0_1_5,
CVT_95_addRegOperands, 6, CVT_Done },
...
The Tie0_1_5 (and corresponding table) encodes that:
* Result operand 0 is the operand to copy (which is e.g. done when
building up the operands to the MCInst in convertToMCInst())
* Asm operands 1 and 5 should be the same operands (which is checked
in checkAsmTiedOperandConstraints()).
Reviewers: olista01, rengolin, fhahn, craig.topper, echristo, apazos, dsanders
Reviewed By: olista01
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42293
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324196
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Chad Rosier [Sun, 4 Feb 2018 15:42:24 +0000 (15:42 +0000)]
[LV] Use Demanded Bits and ValueTracking for reduction type-shrinking
The type-shrinking logic in reduction detection, although narrow in scope, is
also rather ad-hoc, which has led to bugs (e.g., PR35734). This patch modifies
the approach to rely on the demanded bits and value tracking analyses, if
available. We currently perform type-shrinking separately for reductions and
other instructions in the loop. Long-term, we should probably think about
computing minimal bit widths in a more complete way for the loops we want to
vectorize.
PR35734
Differential Revision: https://reviews.llvm.org/D42309
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324195
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Craig Topper [Sun, 4 Feb 2018 01:43:48 +0000 (01:43 +0000)]
[X86] Add DAG combine to turn (bitcast (and/or/xor (bitcast X), Y)) -> (and/or/xor X, (bitcast Y)) when casting between GPRs and mask operations.
This reduces the number of transitions between k-registers and GPRs, reducing the number of instructions.
There's still some room for improvement to remove more transitions, but this is a good start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324184
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Craig Topper [Sun, 4 Feb 2018 01:43:44 +0000 (01:43 +0000)]
[X86] Remove unused function argument. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324183
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Craig Topper [Sat, 3 Feb 2018 23:00:31 +0000 (23:00 +0000)]
[DAGCombiner] When folding fold (sext/zext (and/or/xor (sextload/zextload x), cst)) -> (and/or/xor (sextload/zextload x), (sext/zext cst)) make sure we check the legality of the full extended load.
Summary:
If the load is already an extended load we should be using the memory VT for the legality check, not just the VT of the current extension.
I don't have a test case, just noticed it while investigating some load extension improvements.
Reviewers: RKSimon, spatel, niravd
Reviewed By: niravd
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42783
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324181
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Simon Pilgrim [Sat, 3 Feb 2018 22:11:22 +0000 (22:11 +0000)]
[MIPS] Regenerate vector tests with update script
Hopefully help make this a lot more maintainable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324180
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Simon Pilgrim [Sat, 3 Feb 2018 21:34:42 +0000 (21:34 +0000)]
[SelectionDAG] Don't use simple VT in generic shuffle code
Better to assume that any value type may be commuted, not just MVTs.
No test case right now, but discovered while investigating possible shuffle combines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324179
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Simon Pilgrim [Sat, 3 Feb 2018 21:20:19 +0000 (21:20 +0000)]
[X86][SSE] Don't chain shuffles together in schedule tests
This is necessary to prevent the shuffles from being combined/simplified in an upcoming patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324178
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Craig Topper [Sat, 3 Feb 2018 20:18:25 +0000 (20:18 +0000)]
[X86] Remove and autoupgrade kand/kandn/kor/kxor/kxnor/knot intrinsics.
Clang already stopped using these a couple months ago.
The test cases aren't great as there is nothing forcing the operations to stay in k-registers so some of them moved back to scalar ops due to the bitcasts being moved around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324177
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David Green [Sat, 3 Feb 2018 17:33:50 +0000 (17:33 +0000)]
Remove unneeded -debug argument from new test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324176
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Lang Hames [Sat, 3 Feb 2018 16:52:48 +0000 (16:52 +0000)]
[ORC] Rename NullResolver to NullLegacyResolver.
This resolver conforms to the LegacyJITSymbolResolver interface, and will be
replaced with a null-returning resolver conforming to the newer
orc::SymbolResolver interface in the near future. This patch renames the class
to avoid a clash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324175
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David Green [Sat, 3 Feb 2018 16:51:03 +0000 (16:51 +0000)]
[InstCombine] Allow common type conversions to i8/i16/i32
This, in instcombine, allows conversions to i8/i16/i32 (very
common cases) even if the resulting type is not legal according
to the data layout. This can often open up extra combine
opportunities.
Differential Revision: https://reviews.llvm.org/D42424
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324174
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Alex Bradbury [Sat, 3 Feb 2018 13:02:30 +0000 (13:02 +0000)]
[RISCV] Update two RISCV codegen tests after rL323991
From the discussion in D41835 it looks possible the change will be backed out,
but for now let's fix the RISCV tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324172
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Simon Pilgrim [Sat, 3 Feb 2018 12:38:56 +0000 (12:38 +0000)]
Fix MSVC signed/unsigned comparison warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324171
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Richard Smith [Fri, 2 Feb 2018 22:29:54 +0000 (22:29 +0000)]
Fix incorrect usage of std::is_assignable.
We want to check that we can assign to an lvalue here, not a prvalue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324152
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Daniel Neilson [Fri, 2 Feb 2018 22:03:03 +0000 (22:03 +0000)]
[InstCombine] Use getDestAlignment in SimplifyMemSet (NFC)
Summary:
Small NFC change to change the name of the function used getting and setting
the alignment of a memset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324148
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Craig Topper [Fri, 2 Feb 2018 21:59:46 +0000 (21:59 +0000)]
[X86] Prefer to create a ISD::SETCC over X86ISD::PCMPEQ in combineVectorSizedSetCCEquality.
This is running pre-legalize, we should try to use target independent nodes. This will give the best opportunity for target independent optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324147
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Sanjay Patel [Fri, 2 Feb 2018 21:40:54 +0000 (21:40 +0000)]
[InstCombine] make sure tests are providing coverage for the stated pattern; NFC
Without extra instructions and uses, swapMayExposeCSEOpportunities() would change
the icmp (as seen in the check lines), so we were not actually testing patterns
that should be handled by D41480.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324143
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Craig Topper [Fri, 2 Feb 2018 20:32:00 +0000 (20:32 +0000)]
[X86] Pass SDLoc by const reference in a few more places in X86ISelLowering.cpp. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324135
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Craig Topper [Fri, 2 Feb 2018 20:12:45 +0000 (20:12 +0000)]
[X86] Add avx512 command line to ptest.ll to demonstrate that 512-bit vectors are not handled by LowerVectorAllZeroTest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324130
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Craig Topper [Fri, 2 Feb 2018 20:12:44 +0000 (20:12 +0000)]
Partially revert r324124 [X86] Add tests for missed opportunities to use ptest for all ones comparison.
Turns out I misunderstood the flag behavior of PTEST because I read the documentation for KORTEST which is different than PTEST/KTEST and made a bad assumption.
Keep the test rename though cause that's useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324129
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Aditya Nandakumar [Fri, 2 Feb 2018 19:42:07 +0000 (19:42 +0000)]
[GISel][NFC]: Move RegisterBankInfo::getSizeInBits into TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324125
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Craig Topper [Fri, 2 Feb 2018 19:34:10 +0000 (19:34 +0000)]
[X86] Add tests for missed opportunities to use ptest for all ones comparison.
Also rename the test from pr12312.ll to ptest.ll so its more recognizable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324124
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Alex Denisov [Fri, 2 Feb 2018 19:20:37 +0000 (19:20 +0000)]
Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324123
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Sanjay Patel [Fri, 2 Feb 2018 19:08:12 +0000 (19:08 +0000)]
[InstCombine] simplify logic for swapMayExposeCSEOpportunities; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324122
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Sanjay Patel [Fri, 2 Feb 2018 18:39:05 +0000 (18:39 +0000)]
[InstCombine] fix typos, formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324118
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Amara Emerson [Fri, 2 Feb 2018 18:03:30 +0000 (18:03 +0000)]
[AArch64][GlobalISel] Use getRegClassForTypeOnBank() in selectCopy.
Differential Revision: https://reviews.llvm.org/D42832
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324110
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Sanjay Patel [Fri, 2 Feb 2018 17:43:16 +0000 (17:43 +0000)]
[InstCombine] add baseline tests for unsigned saturated sub (D41480); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324109
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Craig Topper [Fri, 2 Feb 2018 17:02:58 +0000 (17:02 +0000)]
[X86] Remove checks for FeatureAVX512 from the X86 assembly parser. Remove mcpu/mattr from assembly test command lines.
Summary:
We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode.
I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features.
Fixes PR36202
Reviewers: RKSimon, echristo, bkramer
Reviewed By: echristo
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42824
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324106
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Fangrui Song [Fri, 2 Feb 2018 16:41:07 +0000 (16:41 +0000)]
Make utils/UpdateTestChecks/common.py Python 2/3 compatible and fix print statements.
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324104
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Yaxun Liu [Fri, 2 Feb 2018 16:07:16 +0000 (16:07 +0000)]
[AMDGPU] Switch to the new addr space mapping by default
This requires corresponding clang change.
Differential Revision: https://reviews.llvm.org/D40955
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324101
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Clement Courbet [Fri, 2 Feb 2018 15:54:17 +0000 (15:54 +0000)]
Add llc tests for comparison chains.
See https://reviews.llvm.org/D42793#996098 for context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324099
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James Henderson [Fri, 2 Feb 2018 15:09:31 +0000 (15:09 +0000)]
Fix type sizes that were causing incorrect string formatting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324096
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George Rimar [Fri, 2 Feb 2018 15:06:09 +0000 (15:06 +0000)]
[ThinLTO] - Add comment. NFC.
Was requested during review of D42798.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324095
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Simon Pilgrim [Fri, 2 Feb 2018 14:55:20 +0000 (14:55 +0000)]
[X86][SSE] Force double domain for SHUFPD stack folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324094
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Ivan A. Kosarev [Fri, 2 Feb 2018 14:09:22 +0000 (14:09 +0000)]
[Analysis] Support aggregate access types in TBAA
This patch implements analysis for new-format TBAA access tags
with aggregate types as their final access types.
Differential Revision: https://reviews.llvm.org/D41501
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324092
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James Henderson [Fri, 2 Feb 2018 12:45:57 +0000 (12:45 +0000)]
Add missing new files from r324077
Differential Revision: https://reviews.llvm.org/D42481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324078
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James Henderson [Fri, 2 Feb 2018 12:35:52 +0000 (12:35 +0000)]
[DWARF v5] Add limited support for dumping .debug_rnglists
This change adds support to llvm-dwarfdump for dumping DWARF5
.debug_rnglists sections in regular ELF files.
It is not complete, in that several DW_RLE_* encodings are currently
not supported, but does dump the headert and the basic ranges for
DW_RLE_start_length and DW_RLE_start_end encodings.
Obvious next steps are to add verbose dumping that dumps the raw
encodings, rather than the interpreted contents, to add -verify support
of the section (e.g. to show that the correct number of offsets are
specified), add dumping of .debug_rnglists.dwo, and to add support for
other encodings.
Reviewed by: dblaikie, JDevlieghere
Differential Revision: https://reviews.llvm.org/D42481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324077
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George Rimar [Fri, 2 Feb 2018 12:21:26 +0000 (12:21 +0000)]
[LTO] - Simplify. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324076
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George Rimar [Fri, 2 Feb 2018 12:17:33 +0000 (12:17 +0000)]
[ThinLTO] - Fix for "ThinLTO inlines variables that should be discarded".
This fixes PR36187.
Patch teaches ThinLTO to drop non-prevailing variables,
just like we recently did for functions (in r323633).
Differential revision: https://reviews.llvm.org/D42798
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324075
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Sjoerd Meijer [Fri, 2 Feb 2018 11:51:06 +0000 (11:51 +0000)]
[ARM] fixed some tabs/whitespaces in test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324074
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Mikael Holmen [Fri, 2 Feb 2018 10:34:13 +0000 (10:34 +0000)]
[GlobalOpt] Include padding in debug fragments
Summary:
When creating the debug fragments for a SRA'd variable, use the types'
allocation sizes. This fixes issues where the pass would emit too small
fragments, placed at the wrong offset, for padded types.
An example of this is long double on x86. The type is represented using
x86_fp80, which is 10 bytes, but the value is aligned to 12/16 bytes.
The padding is included in the type's DW_AT_byte_size attribute;
therefore, the fragments should also include that. Newer GCC releases
(I tested 7.2.0) emit 12/16-byte pieces for long double. Earlier
releases, e.g. GCC 5.5.0, behaved as LLVM did, i.e. by emitting a
10-byte piece, followed by an empty 2/6-byte piece for the padding.
Failing to cover all `DW_AT_byte_size' bytes of a value with non-empty
pieces results in the value being printed as <optimized out> by GDB.
Patch by: David Stenberg
Reviewers: aprantl, JDevlieghere
Reviewed By: aprantl, JDevlieghere
Subscribers: llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D42807
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324066
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Jonas Paulsson [Fri, 2 Feb 2018 08:48:02 +0000 (08:48 +0000)]
[SelectionDAG] Consider endianness in scalarizeVectorStore().
When handling vectors with non byte-sized elements, reverse the order of the
elements in the built integer if the target is Big-Endian.
SystemZ tests updated.
Review: Eli Friedman, Ulrich Weigand.
https://reviews.llvm.org/D42786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324063
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Jonas Paulsson [Fri, 2 Feb 2018 08:21:53 +0000 (08:21 +0000)]
[SelectionDAG] Add an assert in getNode() for EXTRACT_VECTOR_ELT.
When getNode() is called to create an EXTRACT_VECTOR_ELT, assert that
the result VT is at least as wide as the vector element type.
Review: Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324061
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Jonas Paulsson [Fri, 2 Feb 2018 07:52:02 +0000 (07:52 +0000)]
[SystemZ] Update test case (NFC)
test/CodeGen/SystemZ/vec-trunc-to-i1.ll was marked as a temporary
FAIL when it was previously updated when it needed one more COPY.
This was however wrong, since the loop body had been reduced
significantly, and it was actually an improvement.
Review: Ulrich Weigand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324060
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Shiva Chen [Fri, 2 Feb 2018 06:01:02 +0000 (06:01 +0000)]
[RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get RISCV target feature
llvm-objdump could get C feature by ELF::EF_RISCV_RVC e_flag,
so then we don't have to add -mattr=+c on the command line.
Differential Revision: https://reviews.llvm.org/D42629
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324058
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Craig Topper [Fri, 2 Feb 2018 05:59:33 +0000 (05:59 +0000)]
[X86] Legalize (v64i1 (bitcast (i64 X))) on 32-bit targets by extracting 32-bit halves from i32, bitcasting each to v32i1, and concatenating.
This prevents the scalarization that would otherwise occur.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324057
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Craig Topper [Fri, 2 Feb 2018 05:59:31 +0000 (05:59 +0000)]
[X86] Legalize (i64 (bitcast (v64i1 X))) on 32-bit targets by extracting to v32i1 and bitcasting to i32.
This saves a trip through memory and seems to open up other combining opportunities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324056
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Shiva Chen [Fri, 2 Feb 2018 02:43:23 +0000 (02:43 +0000)]
[RISCV] Fix c.addi and c.addi16sp immediate constraints which should be non-zero
Differential Revision: https://reviews.llvm.org/D42782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324055
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Shiva Chen [Fri, 2 Feb 2018 02:43:18 +0000 (02:43 +0000)]
[RISCV] Define getSetCCResultType for setting vector setCC type
To avoid trigger "No default SetCC type for vectors!" Assertion
Differential Revision: https://reviews.llvm.org/D42675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324054
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Amara Emerson [Fri, 2 Feb 2018 02:14:42 +0000 (02:14 +0000)]
[AArch64][GlobalISel] Fix old use of % sigil in test.
My rebase had missed the new $ sigil we're using.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324051
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Amara Emerson [Fri, 2 Feb 2018 01:49:59 +0000 (01:49 +0000)]
Fix debug spelling in ResetMachineFunction pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324048
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Amara Emerson [Fri, 2 Feb 2018 01:44:43 +0000 (01:44 +0000)]
[GlobalISel] Constrain the dest reg of IMPLICT_DEF.
This fixes a crash where the user is a COPY, which deliberately does not
constrain its source operands, resulting in a vreg without a reg class escaping
selection.
Differential Revision: https://reviews.llvm.org/D42697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324047
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David Blaikie [Fri, 2 Feb 2018 00:33:50 +0000 (00:33 +0000)]
Remove non-modular header containing static utility functions
The one place that uses these functions isn't particularly
long/complicated, so it's easier to just have these inline at that
location than trying to split it out into a true header. (in part also
because of the use of the DEBUG macros, which make this not really a
standalone header even if the static functions were made inline instead)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324044
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David Blaikie [Fri, 2 Feb 2018 00:11:09 +0000 (00:11 +0000)]
Add missing includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324040
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Matthias Braun [Fri, 2 Feb 2018 00:08:19 +0000 (00:08 +0000)]
SplitKit: Fix liveness recomputation in some remat cases.
Example situation:
```
BB0:
%0 = ...
use %0
; ...
condjump BB1
jmp BB2
BB1:
%0 = ... ; rematerialized def from above (from earlier split step)
jmp BB2
BB2:
; ...
use %0
```
%0 will have a live interval with 3 value numbers (for the BB0, BB1 and
BB2 parts). Now SplitKit tries and succeeds in rematerializing the value
number in BB2 (This only works because it is a secondary split so
SplitKit is can trace this back to a single original def).
We need to recompute all live ranges affected by a value number that we
rematerialize. The case that we missed before is that when the value
that is rematerialized is at a join (Phi VNI) then we also have to
recompute liveness for the predecessor VNIs.
rdar://
35699130
Differential Revision: https://reviews.llvm.org/D42667
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324039
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Vlad Tsyrklevich [Fri, 2 Feb 2018 00:07:14 +0000 (00:07 +0000)]
Fix broken builds due to mismatched min/max types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324038
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Vlad Tsyrklevich [Thu, 1 Feb 2018 23:45:18 +0000 (23:45 +0000)]
[cfi-verify] Add blame context printing, and improved print format.
Summary:
This update now allows users to specify `--blame-context` and `--blame-context-all` to print source file blame information for the source of the blame.
Also updates the inline printing to correctly identify the top of the inlining stack for blame information.
Patch by Mitch Phillips!
Reviewers: vlad.tsyrklevich
Subscribers: llvm-commits, kcc, pcc
Differential Revision: https://reviews.llvm.org/D40111
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324035
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Craig Topper [Thu, 1 Feb 2018 23:21:20 +0000 (23:21 +0000)]
[X86] Separate the call to LowerVectorAllZeroTest from EmitTest. NFCI
Every instruction that has the word TEST in its name seems to have been buried into EmitTest. But that code is largely concerned with trying to reuse the flags from instructions that update flags in a pretty normal way.
PTEST/TESTP/KTEST do not update flags in a normal way. They only update Z and C and the C flag update is non-standard. Rather than try to bend EmitTest's already complex logic to accomodate this, just move the call up to LowerSETCC and replicate the few pre-checks that are needed.
While there add a FIXME for using the C flag for checking for all 1s which we definitely couldn't do from EmitTEST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324029
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Amara Emerson [Thu, 1 Feb 2018 23:10:57 +0000 (23:10 +0000)]
[GlobalISel][Legalizer] Relax a legalization loop detecting assert.
Legalizing vectors may keep the element type the same but change the number of
elements, the assert didn't take this into account.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324028
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Simon Pilgrim [Thu, 1 Feb 2018 22:32:41 +0000 (22:32 +0000)]
Fix check-prefixes typo and line endings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324024
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Simon Pilgrim [Thu, 1 Feb 2018 22:05:44 +0000 (22:05 +0000)]
[X86][SSE] Add SSE41 to variable permute tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324017
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Simon Pilgrim [Thu, 1 Feb 2018 21:57:37 +0000 (21:57 +0000)]
[X86][XOP] Add XOP to variable permute tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324015
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Sanjay Patel [Thu, 1 Feb 2018 21:55:53 +0000 (21:55 +0000)]
[InstCombine] allow multi-use values in canEvaluate* if all uses are in 1 inst
This is the enhancement suggested in D42536 to fix a shortcoming in
regular InstCombine's canEvaluate* functionality.
When we have multiple uses of a value, but they're all in one instruction, we can
allow that expression to be narrowed or widened for the same cost as a single-use
value.
AFAICT, this can only matter for multiply: sub/and/or/xor/select would be simplified
away if the operands are the same value; add becomes shl; shifts with a variable shift
amount aren't handled.
Differential Revision: https://reviews.llvm.org/D42739
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324014
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Nemanja Ivanovic [Thu, 1 Feb 2018 21:09:04 +0000 (21:09 +0000)]
[PowerPC] Tell VSX swap removal that scalar conversions are lane-sensitive
This is a rather non-controversial change. We were missing these instructions
from the list of instructions that are lane-sensitive. These two put the result
into lane 0 (BE) or 3 (LE) regardless of the input. This patch fixes PR36068.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324005
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David Blaikie [Thu, 1 Feb 2018 21:03:35 +0000 (21:03 +0000)]
Coding Standards: Document library layering requirements & header isolation.
(I suppose these two pieces could be separated - but seemed related
enough)
As discussed on llvm-dev, this documents the general expectation of how
library layering should be handled. There are a few existing cases where
these constraints are not met, but as with most style guide things -
this is forward looking and provides guidance when cleaning up existing
code, it doesn't immediately require that all previous code be cleaned
up to match. (see: naming conventions, etc)
Differential Revision: https://reviews.llvm.org/D42771
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324004
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Craig Topper [Thu, 1 Feb 2018 20:48:50 +0000 (20:48 +0000)]
[DAGCombiner] When folding (insert_subvector undef, (bitcast (extract_subvector N1, Idx)), Idx) -> (bitcast N1) make sure that N1 has the same total size as the original output
We were only checking the element count, but not the total width. This could cause illegal bitcasts to be created if for example the output was 512-bits, but N1 is 256 bits, and the extraction size was 128-bits.
Fixes PR36199
Differential Revision: https://reviews.llvm.org/D42809
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324002
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Amara Emerson [Thu, 1 Feb 2018 20:47:03 +0000 (20:47 +0000)]
[GlobalISel] Fix assert failure when legalizing non-power-2 loads.
Until we support extending loads properly we're going to fall back for these.
We already handle stores in the same way, so this is just being consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324001
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Brock Wyma [Thu, 1 Feb 2018 20:37:38 +0000 (20:37 +0000)]
[CodeView] Class record member counts should include base classes and ...
Increment the field list member count for base classes and virtual base
classes.
Differential Revision: https://reviews.llvm.org/D41874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324000
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Benjamin Kramer [Thu, 1 Feb 2018 20:28:33 +0000 (20:28 +0000)]
[ADT] Replace sys::MemoryFence with standard atomics.
This is a bit faster in theory, in practice it's cold code that's only
active in !NDEBUG, so it probably doesn't make a difference. This is one
of the last users of our homegrown Atomic.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323999
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Sanjay Patel [Thu, 1 Feb 2018 19:59:33 +0000 (19:59 +0000)]
[AArch64] remove bogus comment; NFC
I added this comment with D42323, but as discussed in D42806, the architecture
does the right thing for denorms. We don't even need the select on 0.0 here?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323996
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Easwaran Raman [Thu, 1 Feb 2018 19:40:35 +0000 (19:40 +0000)]
Remove CallGraphTraits and use equivalent methods in GraphTraits
Summary:
D42698 adds child_edge_{begin|end} and children_edges to GraphTraits
which are used here. The reason for this change is to make it easy to
use count propagation on ModulesummaryIndex. As it stands,
CallGraphTraits is in Analysis while ModuleSummaryIndex is in IR.
Reviewers: davidxl, dberlin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42703
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323994
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Geoff Berry [Thu, 1 Feb 2018 18:54:01 +0000 (18:54 +0000)]
[MachineCopyPropagation] Extend pass to do COPY source forwarding
Summary:
This change extends MachineCopyPropagation to do COPY source forwarding
and adds an additional run of the pass to the default pass pipeline just
after register allocation.
This version of this patch uses the newly added
MachineOperand::isRenamable bit to avoid forwarding registers is such a
way as to violate constraints that aren't captured in the
Machine IR (e.g. ABI or ISA constraints).
This change is a continuation of the work started in D30751.
Reviewers: qcolombet, javed.absar, MatzeB, jonpa, tstellar
Subscribers: tpr, mgorny, mcrosier, nhaehnle, nemanjai, jyknight, hfinkel, arsenm, inouehrs, eraman, sdardis, guyblank, fedor.sergeev, aheejin, dschuff, jfb, myatsina, llvm-commits
Differential Revision: https://reviews.llvm.org/D41835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323991
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Easwaran Raman [Thu, 1 Feb 2018 18:53:23 +0000 (18:53 +0000)]
[GraphTraits] Add support for iterating over children edges.
Summary:
This change is mostly adding comments to GraphTraits describing
interfaces to iterate over children edges of a node. These will
have to be implemented by specializations of GraphTraits. The
non-comment change is the addition of children_edges template
function that returns an iterator range.
The motivation for this is to use it in synthetic count propagation
algorithm and remove the CallGraphTraits class that provide similar
interfaces.
Reviewers: dberlin, davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42698
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323990
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Changpeng Fang [Thu, 1 Feb 2018 18:41:33 +0000 (18:41 +0000)]
AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature.
Reviewers:
Matt and Brian
Differential Revision:
https://reviews.llvm.org/D42548
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323988
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Simon Pilgrim [Thu, 1 Feb 2018 18:10:30 +0000 (18:10 +0000)]
[X86][SSE] LowerBUILD_VECTORAsVariablePermute - add support for scaling index vectors
This allows us to use PSHUFB for v8i16/v4i32 and VPERMD/PERMPS for v4i64/v4f64 variable shuffles.
Differential Revision: https://reviews.llvm.org/D42487
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323987
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Sanjay Patel [Thu, 1 Feb 2018 17:57:45 +0000 (17:57 +0000)]
[AArch64] add tests with sqrt estimate and ieee denorms; NFC
As noted in D42323, we're not checking for denorms as we should.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323985
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Sanjay Patel [Thu, 1 Feb 2018 17:44:50 +0000 (17:44 +0000)]
[AArch64] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323984
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Craig Topper [Thu, 1 Feb 2018 17:08:41 +0000 (17:08 +0000)]
[X86] Remove custom lowering vXi1 extending loads and truncating stores.
Summary: Now that v2i1/v4i1 are legal without VLX. And v32i1 is legalized by splitting rather than widening. And isVectorLoadExtDesirable returns false for vXi1. It appears this handling is dead because the operations simply don't exist.
Reviewers: RKSimon, zvi, guyblank, delena, spatel
Reviewed By: delena
Subscribers: llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D42781
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323983
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Craig Topper [Thu, 1 Feb 2018 17:08:39 +0000 (17:08 +0000)]
[X86] Turn X86ISD::AND nodes that have no flag users back into ISD::AND just before isel to enable test instruction matching
Summary:
EmitTest sometimes creates X86ISD::AND specifically to hide the AND from DAG combine. But this prevents isel patterns that look for (cmp (and X, Y), 0) from being able to see it. So we end up with an AND and a TEST. The TEST gets removed by compare instruction optimization during the peephole pass.
This patch attempts to fix this by converting X86ISD::AND with no flag users back into ISD::AND during the DAG preprocessing just before isel.
In order to do this correctly I had to make the X86ISD::AND node created by EmitTest in this case really have a flag output. Which arguably it should have had anyway so that the number of operands would be consistent for the opcode in all cases. Then I had to modify the ReplaceAllUsesWith to understand that we might be looking at an instruction with 2 outputs. Though in this case there are no uses to replace since we just created the node, but that's what the code did before so I just made it keep working.
Reviewers: spatel, RKSimon, niravd, deadalnix
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42764
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323982
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Sanjay Patel [Thu, 1 Feb 2018 16:57:18 +0000 (16:57 +0000)]
[DAGCombiner] filter out denorm inputs when calculating sqrt estimate (PR34994)
As shown in the example in PR34994:
https://bugs.llvm.org/show_bug.cgi?id=34994
...we can return a very wrong answer (inf instead of 0.0) for square root when
using a reciprocal square root estimate instruction.
Here, I've conditionalized the filtering out of denorms based on the function
having "denormal-fp-math"="ieee" in its attributes. The other options for this
attribute are 'preserve-sign' and 'positive-zero'.
So we don't generate this extra code by default with just '-ffast-math' (because
then there's no denormal attribute string at all), but it works if you specify
'-ffast-math -fdenormal-fp-math=ieee' from clang.
As noted in the review, there may be other problems in clang that affect the
results depending on platform (Linux x86 at least), but this should allow
creating the desired codegen.
Differential Revision: https://reviews.llvm.org/D42323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323981
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Nirav Dave [Thu, 1 Feb 2018 16:11:59 +0000 (16:11 +0000)]
[SelectionDAG] Fix UpdateChains handling of TokenFactors
Summary:
In Instruction Selection UpdateChains replaces all matched Nodes'
chain references including interior token factors and deletes them.
This may allow nodes which depend on these interior nodes but are not
part of the set of matched nodes to be left with a dangling dependence.
Avoid this by doing the replacement for matched non-TokenFactor nodes.
Fixes PR36164.
Reviewers: jonpa, RKSimon, bogner
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D42754
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323977
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Simon Pilgrim [Thu, 1 Feb 2018 15:30:02 +0000 (15:30 +0000)]
[X86][SSE] Add PR26491 horizontal add test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323973
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Simon Pilgrim [Thu, 1 Feb 2018 14:44:50 +0000 (14:44 +0000)]
[X86][AVX512DQ] Add DQ var permute 256 tests as requested on D42487
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323970
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Sjoerd Meijer [Thu, 1 Feb 2018 13:48:40 +0000 (13:48 +0000)]
[ARM] FullFP16 LowerReturn Fix
Commit r323512 introduced an optimisation in LowerReturn for half-precision
return values. A missing check caused a crash when the return value is "undef"
(i.e. a node that has no operands).
Differential Revision: https://reviews.llvm.org/D42743
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323968
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