OSDN Git Service
Paul Robinson [Fri, 9 Nov 2018 19:06:09 +0000 (19:06 +0000)]
[DWARFv5] Emit normal type units in .debug_info comdats.
Differential Revision: https://reviews.llvm.org/D54282
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346540
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 9 Nov 2018 19:05:51 +0000 (19:05 +0000)]
[X86] Turn X86ISD::VSEXT into X86ISD::VZEXT if the upper bits aren't demanded.
This makes X86ISD::VSEXT more similar to ISD::SIGN_EXTEND and ISD::ZERO_EXTEND.
I'm hoping to replace X86ISD::VSEXT/VZEXT with target independent nodes. Making the target specific nodes similar to the target independent nodes helps minimize test diffs in that patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346539
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 9 Nov 2018 19:04:27 +0000 (19:04 +0000)]
[CostModel][X86] SK_ExtractSubvector is free if the subvector is at the start of the source vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346538
91177308-0d34-0410-b5e6-
96231b3b80d8
Jordan Rupprecht [Fri, 9 Nov 2018 18:54:27 +0000 (18:54 +0000)]
[Hexagon] Fix unused variable warning in release builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346537
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 9 Nov 2018 18:32:20 +0000 (18:32 +0000)]
[WebAssembly] Hotfix of WebAssemblyInstructionTableSize after rL346465
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346535
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 9 Nov 2018 18:30:59 +0000 (18:30 +0000)]
[TTI] Flip vector types in getShuffleCost SK_ExtractSubvector call
For SK_ExtractSubvector, the default 'Ty' type is the source operand type and 'SubTy' is the destination subvector type
I got this the wrong way around when I added rL346510
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346534
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Fri, 9 Nov 2018 18:23:39 +0000 (18:23 +0000)]
[AMDGPU] Cleanup optimize-if-exec-masking.mir test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346533
91177308-0d34-0410-b5e6-
96231b3b80d8
Brendon Cahoon [Fri, 9 Nov 2018 18:16:24 +0000 (18:16 +0000)]
[Hexagon] Implement noreturn optimization
Eliminate the stack frame in functions with the noreturn nounwind
attributes, and when the noreturn-stack-elim target feature is
enabled. This reduces the code and stack space needed for noreturn
functions.
Differential Revision: https://reviews.llvm.org/D54210
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346532
91177308-0d34-0410-b5e6-
96231b3b80d8
Greg Clayton [Fri, 9 Nov 2018 18:10:02 +0000 (18:10 +0000)]
Add total function byte size and inline function byte size to "llvm-dwarfdump --statistics"
Differential Revision: https://reviews.llvm.org/D54217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346531
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 9 Nov 2018 18:04:34 +0000 (18:04 +0000)]
[DAGCombiner][X86][Mips] Enable combineShuffleOfScalars to run between vector op legalization and DAG legalization. Fix bad one use check in combineShuffleOfScalars
It's possible for vector op legalization to generate a shuffle. If that happens we should give a chance for DAG combine to combine that with a build_vector input.
I also fixed a bug in combineShuffleOfScalars that was considering the number of uses on a undef input to a shuffle. We don't care how many times undef is used.
Differential Revision: https://reviews.llvm.org/D54283
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346530
91177308-0d34-0410-b5e6-
96231b3b80d8
Jordan Rupprecht [Fri, 9 Nov 2018 18:03:21 +0000 (18:03 +0000)]
[llvm-strings] Fix whitespaces to match strings output.
Summary:
The current implementation prepends a space on every line, making it difficult to compare against GNU strings.
The space appears to have come from handling --radix in rL292707. The space is for making sure there's a space between the radix and the value; however the space is still emitted even when there is no radix. This change fixes that so the space is only emitted when there is a radix.
Reviewers: jhenderson
Reviewed By: jhenderson
Subscribers: llvm-commits, compnerd
Differential Revision: https://reviews.llvm.org/D54238
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346529
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Fri, 9 Nov 2018 17:58:59 +0000 (17:58 +0000)]
[AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx
This only covers AMDGPU BE, hopefully all occurrences.
Differential Revision: https://reviews.llvm.org/D54235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346528
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Fri, 9 Nov 2018 17:31:22 +0000 (17:31 +0000)]
[Hexagon] Place globals with explicit .sdata section in small data
Both -fPIC and -G0 disable placement of globals in small data section,
but if a global has an explicit section assigmnent placing it in small
data, it should go there anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346523
91177308-0d34-0410-b5e6-
96231b3b80d8
Serge Guelton [Fri, 9 Nov 2018 17:19:45 +0000 (17:19 +0000)]
Type safe version of MachinePassRegistry
Previous version used type erasure through a `void* (*)()` pointer,
which triggered gcc warning and implied a lot of reinterpret_cast.
This version should make it harder to hit ourselves in the foot.
Differential revision: https://reviews.llvm.org/D54203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346522
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Fri, 9 Nov 2018 17:09:16 +0000 (17:09 +0000)]
[docs][statepoints] Reformulate open issues list
Some have been partially resolved, so update that. And restructure to make it easie to find and search.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346518
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 9 Nov 2018 16:45:37 +0000 (16:45 +0000)]
Fix -Wsign-compare warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346515
91177308-0d34-0410-b5e6-
96231b3b80d8
Max Moroz [Fri, 9 Nov 2018 16:44:36 +0000 (16:44 +0000)]
[llvm-cov] Remove "default:" label in the switch covering all enum values.
Summary:
Fixing the build breakage:
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/27309
Reviewers: vsk, allevato, Dor1s
Reviewed By: Dor1s
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D54323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346514
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Fri, 9 Nov 2018 16:40:34 +0000 (16:40 +0000)]
[docs][statepoint] Expand a bit on problems with mixing references and raw pointers since it keeps coming up in discussions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346513
91177308-0d34-0410-b5e6-
96231b3b80d8
Zaara Syeda [Fri, 9 Nov 2018 16:36:24 +0000 (16:36 +0000)]
[Power9] Allow gpr callee saved spills in prologue to vectors registers
Currently in llvm, CalleeSavedInfo can only assign a callee saved register to
stack frame index to be spilled in the prologue. We would like to enable
spilling gprs to vector registers. This patch adds the capability to spill to
other registers aside from just the stack. It also adds the changes for power9
to spill gprs to volatile vector registers when they are available.
This happens only for leaf functions when using the option
-ppc-enable-pe-vector-spills.
Differential Revision: https://reviews.llvm.org/D39386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346512
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 9 Nov 2018 16:28:19 +0000 (16:28 +0000)]
[CostModel] Add SK_ExtractSubvector handling to getInstructionThroughput (PR39368)
Add ShuffleVectorInst::isExtractSubvectorMask helper to match shuffle masks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346510
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Fri, 9 Nov 2018 16:27:04 +0000 (16:27 +0000)]
[docs][statepoint] tweak a title
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346509
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Fri, 9 Nov 2018 16:22:35 +0000 (16:22 +0000)]
Revert "[DEBUGINFO, NVPTX]DO not emit ',debug' option if no debug info or only debug directives are requested."
This reverts commit r345972. Need to update the description + possibly
to update the patch itself after discussion with Eric Christofer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346508
91177308-0d34-0410-b5e6-
96231b3b80d8
Max Moroz [Fri, 9 Nov 2018 16:10:44 +0000 (16:10 +0000)]
[llvm-cov] Add lcov tracefile export format.
Summary:
lcov tracefiles are used by various coverage reporting tools and build
systems (e.g., Bazel). It is a simple text-based format to parse and
more convenient to use than the JSON export format, which needs
additional processing to map regions/segments back to line numbers.
It's a little unfortunate that "text" format is now overloaded to refer
specifically to JSON for export, but I wanted to avoid making any
breaking changes to the UI of the llvm-cov tool at this time.
Patch by Tony Allevato (@allevato).
Reviewers: Dor1s, vsk
Reviewed By: Dor1s, vsk
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D54266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346506
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Paulsson [Fri, 9 Nov 2018 15:44:28 +0000 (15:44 +0000)]
[SystemZ] Avoid inserting same value after replication
A minor improvement of buildVector() that skips creating an
INSERT_VECTOR_ELT for a Value which has already been used for the
REPLICATE.
Review: Ulrich Weigand
https://reviews.llvm.org/D54315
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346504
91177308-0d34-0410-b5e6-
96231b3b80d8
Nicolai Haehnle [Fri, 9 Nov 2018 15:13:12 +0000 (15:13 +0000)]
AMDGPU: Add testcase to demonstrate a condition with pre-existing waitcnt
Relevant for https://reviews.llvm.org/D54226.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346501
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam McCall [Fri, 9 Nov 2018 15:11:34 +0000 (15:11 +0000)]
Revert "[VFS] Add "expand tilde" argument to getRealPath."
This reverts commit r346453.
This is a complex change to a widely-used interface, and was not reviewed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346500
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Parker [Fri, 9 Nov 2018 15:06:33 +0000 (15:06 +0000)]
[ARM] Don't promote i1 types in ARM CGP
Now that we have mixed type sizes, i1 values need to be explicitly
handled as we want to avoid promoting these values.
Differential Revision: https://reviews.llvm.org/D54308
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346499
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 9 Nov 2018 14:54:58 +0000 (14:54 +0000)]
[x86] try to form broadcast before widening shuffle elements
I noticed that we weren't generating broadcasts as much I thought we would with
D54271, and this is part of the problem.
Widening the shuffle elements means adding bitcasts and hiding the relationship
between a splatted scalar and the vector. If we can form a broadcast, do that
before going through the rest of the shuffle lowering because broadcasts should
be cheap and can often be load-folded.
Differential Revision: https://reviews.llvm.org/D54280
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346498
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Fri, 9 Nov 2018 14:47:36 +0000 (14:47 +0000)]
[RISCV] Avoid unnecessary XOR for seteq/setne 0
Differential Revision: https://reviews.llvm.org/D53492
Patch by James Clarke.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346497
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Fri, 9 Nov 2018 14:35:44 +0000 (14:35 +0000)]
[RISCV] Update test/CodeGen/RISCV/calling-conv.ll after rL346432
The DAGCombiner changes led to a different schedule.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346496
91177308-0d34-0410-b5e6-
96231b3b80d8
Petar Avramovic [Fri, 9 Nov 2018 14:21:16 +0000 (14:21 +0000)]
[MIPS GlobalISel] narrowScalar G_CONSTANT
Legalize s64 G_CONSTANT using narrowScalar on MIPS 32.
Differential Revision: https://reviews.llvm.org/D54255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346495
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Fri, 9 Nov 2018 14:17:27 +0000 (14:17 +0000)]
[Hexagon] Handle Hexagon's SHF_HEX_GPREL section flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346494
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Fri, 9 Nov 2018 14:08:29 +0000 (14:08 +0000)]
[llvm-exegesis] Fix unit tests on PowerPC/AArch64.
We were comparing char*s and not contents. Introduced in rL346489.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346493
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Fri, 9 Nov 2018 13:28:58 +0000 (13:28 +0000)]
Revert r346483: [CallSiteSplitting] Only record conditions up to the IDom(call site).
This cause a failure with EXPENSIVE_CHECKS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346492
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 9 Nov 2018 13:19:03 +0000 (13:19 +0000)]
[X86] Add Subtarget to more lowerVectorShuffle functions. NFCI.
This will be necessary for an update to D54267
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346490
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Fri, 9 Nov 2018 13:15:32 +0000 (13:15 +0000)]
[llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target.
Summary:
This simplifies the code and moves everything to tablegen for consistency. This
also prepares the ground for adding issue counters.
Reviewers: gchatelet, john.brawn, jsji
Subscribers: nemanjai, mgorny, javed.absar, kbarton, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D54297
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346489
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Fri, 9 Nov 2018 12:29:57 +0000 (12:29 +0000)]
[llvm-mca] Use a small vector for instructions in the EntryStage.
Use a simple SmallVector to track the lifetime of simulated instructions.
An ordered map was not needed because instructions are already picked in program
order. It is also much faster if we avoid searching for already retired
instructions at the end of every cycle.
The new policy only triggers a "garbage collection" when the number of retired
instructions becomes significantly big when compared with the total size of the
vector.
While working on this, I noticed that instructions were correctly retired, but
their internal state was not updated (i.e. there was no transition from the
EXECUTED state, to the RETIRED state). While this was not a problem for the
views, it prevented the EntryStage from correctly garbage collecting already
retired instructions. That was a bad oversight, and this patch fixes it.
The observed speedup on a debug build of llvm-mca after this patch is ~6%.
On a release build of llvm-mca, the observed speedup is ~%15%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346487
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Fri, 9 Nov 2018 11:52:27 +0000 (11:52 +0000)]
[IPSCCP,PM] Preserve DT in the new pass manager.
After D45330, Dominators are required for IPSCCP and can be preserved.
This patch preserves DominatorTreeAnalysis in the new pass manager. AFAIK the legacy pass manager cannot preserve function analysis required by a module analysis.
Reviewers: davide, dberlin, chandlerc, efriedma, kuhar, NutshellySima
Reviewed By: chandlerc, kuhar, NutshellySima
Differential Revision: https://reviews.llvm.org/D47259
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346486
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexandros Lamprineas [Fri, 9 Nov 2018 11:09:40 +0000 (11:09 +0000)]
[SelectionDAG] swap select_cc operands to enable folding
The DAGCombiner tries to SimplifySelectCC as follows:
select_cc(x, y, 16, 0, cc) -> shl(zext(set_cc(x, y, cc)), 4)
It can't cope with the situation of reordered operands:
select_cc(x, y, 0, 16, cc)
In that case we just need to swap the operands and invert the Condition Code:
select_cc(x, y, 16, 0, ~cc)
Differential Revision: https://reviews.llvm.org/D53236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346484
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Fri, 9 Nov 2018 10:23:46 +0000 (10:23 +0000)]
[CallSiteSplitting] Only record conditions up to the IDom(call site).
We can stop recording conditions once we reached the immediate dominator
for the block containing the call site. Conditions in predecessors of the
that node will be the same for all paths to the call site and splitting
is not beneficial.
This patch makes CallSiteSplitting dependent on the DT anlysis. because
the immediate dominators seem to be the easiest way of finding the node
to stop at.
I had to update some exiting tests, because they were checking for
conditions that were true/false on all paths to the call site. Those
should now be handled by instcombine/ipsccp.
Reviewers: davide, junbuml
Reviewed By: junbuml
Differential Revision: https://reviews.llvm.org/D44627
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346483
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Fri, 9 Nov 2018 09:49:06 +0000 (09:49 +0000)]
[X86] Fix VZEROUPPER scheduling info on SNB,HSW,BDW,SXL,SKX.
Summary:
Starting from SNB, VZEROUPPER is handled by the renamer and uses no proc resources.
After HSW, it also has zero latency.
This fixes PR35606.
To reproduce:
Uops:
llvm-exegesis -mode=uops -opcode-name=VZEROUPPER
Latency:
echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper' | /tmp/llvm-exegesis -mode=latency -snippets-file=-
echo -e '#LLVM-EXEGESIS-DEFREG XMM0 1\n#LLVM-EXEGESIS-DEFREG XMM1 1\nvzeroupper\naddps %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=latency -snippets-file=-
Reviewers: RKSimon, craig.topper, andreadb
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D54107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346482
91177308-0d34-0410-b5e6-
96231b3b80d8
Carlos Alberto Enciso [Fri, 9 Nov 2018 09:42:10 +0000 (09:42 +0000)]
[DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG.
In SimplifyCFG when given a conditional branch that goes to BB1 and BB2, the hoisted common terminator instruction in the two blocks, caused debug line records associated with subsequent select instructions to become ambiguous. It causes the debugger to display unreachable source lines.
Differential Revision: https://reviews.llvm.org/D53390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346481
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Parker [Fri, 9 Nov 2018 09:28:27 +0000 (09:28 +0000)]
[ARM] Enable mixed types in ARM CGP
Previously, during the search, all values had to have the same
'TypeSize', which is equal to number of bits of the integer type of
the icmp operand. All values in the tree had to match this size;
meaning that, if we searched from i16, we wouldn't accept i8s. A
change in type size requires zext and truncs to perform the casts so,
to allow mixed narrow types, the handling of these instructions is
now slightly different:
- we allow casts if their result or operand is <= TypeSize.
- zexts are sinks if their result > TypeSize.
- truncs are still sinks if their operand == TypeSize.
- truncs are still sources if their result == TypeSize.
The transformation bails on finding an icmp that operates on data
smaller than the current TypeSize.
Differential Revision: https://reviews.llvm.org/D54108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346480
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Parker [Fri, 9 Nov 2018 09:18:00 +0000 (09:18 +0000)]
[ARM] Small reorganisation in ARMParallelDSP
A few code movement things:
- AreSymmetrical is now a method of BinOpChain.
- Created a lambda in CreateParallelMACPairs to reduce loop nesting.
- A Reduction object now gets pasted in a couple of places instead,
including CreateParallelMACPairs so it doesn't need to return a
value.
I've also added RecordSequentialLoads, which is run before the
transformation begins, and caches the interesting loads. This can then
be queried later instead of cross checking many load values.
Differential Revision: https://reviews.llvm.org/D54254
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346479
91177308-0d34-0410-b5e6-
96231b3b80d8
Dean Michael Berris [Fri, 9 Nov 2018 06:26:48 +0000 (06:26 +0000)]
[XRay] Improve FDR trace handling and error messaging
Summary:
This change covers a number of things spanning LLVM and compiler-rt,
which are related in a non-trivial way.
In LLVM, we have a library that handles the FDR mode even log loading,
which uses C++'s runtime polymorphism feature to better faithfully
represent the events that are written down by the FDR mode runtime. We
do this by interpreting a trace that's serliased in a common format
agreed upon by both the trace loading library and the FDR mode runtime.
This library is under active development, which consists of features
allowing us to reconstitute a higher-level event log.
This event log is used by the conversion and visualisation tools we have
for interpreting XRay traces.
One of the tools we have is a diagnostic tool in llvm-xray called
`fdr-dump` which we've been using to debug our expectations of what the
FDR runtime should be writing and what the logical FDR event log
structures are. We use this fairly extensively to reason about why some
non-trivial traces we're generating with FDR mode runtimes fail to
convert or fail to parse correctly.
One of these failures we've found in manual debugging of some of the
traces we've seen involve an inconsistency between the buffer extents (a
record indicating how many bytes to follow are part of a logical
thread's event log) and the record of the bytes written into the log --
sometimes it turns out the data could be garbage, due to buffers being
recycled, but sometimes we're seeing the buffer extent indicating a log
is "shorter" than the actual records associated with the buffer. This
case happens particularly with function entry records with a call
argument.
This change for now updates the FDR mode runtime to write the bytes for
the function call and arg record before updating the buffer extents
atomically, allowing multiple threads to see a consistent view of the
data in the buffer using the atomic counter associated with a buffer.
What we're trying to prevent here is partial updates where we see the
intermediary updates to the buffer extents (function record size then
call argument record size) becoming observable from another thread, for
instance, one doing the serialization/flushing.
To do both diagnose this issue properly, we need to be able to honour
the extents being set in the `BufferExtents` records marking the
beginning of the logical buffers when reading an FDR trace. Since LLVM
doesn't use C++'s RTTI mechanism, we instead follow the advice in the
documentation for LLVM Style RTTI
(https://llvm.org/docs/HowToSetUpLLVMStyleRTTI.html). We then rely on
this RTTI feature to ensure that our file-based record producer (our
streaming "deserializer") can honour the extents of individual buffers
as we interpret traces.
This also sets us up to be able to eventually do smart
skipping/continuation of FDR logs, seeking instead to find BufferExtents
records in cases where we find potentially recoverable errors. In the
meantime, we make this change to operate in a strict mode when reading
logical buffers with extent records.
Reviewers: mboerger
Subscribers: hiraditya, llvm-commits, jfb
Differential Revision: https://reviews.llvm.org/D54201
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346473
91177308-0d34-0410-b5e6-
96231b3b80d8
Max Kazantsev [Fri, 9 Nov 2018 05:39:04 +0000 (05:39 +0000)]
[NFC] Add utility function for SafetyInfo updates for moveBefore
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346472
91177308-0d34-0410-b5e6-
96231b3b80d8
Petr Hosek [Fri, 9 Nov 2018 03:16:53 +0000 (03:16 +0000)]
[llvm-rc] Support joined or separate spelling for /fo flag
CMake invokes rc using the joined spelling which appears to be supported
by Microsoft's rc implementation, so we should support it as well.
Differential Revision: https://reviews.llvm.org/D54191
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346470
91177308-0d34-0410-b5e6-
96231b3b80d8
Mandeep Singh Grang [Fri, 9 Nov 2018 02:48:36 +0000 (02:48 +0000)]
[COFF, ARM64] Add support for MSVC buffer security check
Reviewers: rnk, mstorsjo, compnerd, efriedma, TomTan
Reviewed By: rnk
Subscribers: javed.absar, kristof.beyls, chrib, llvm-commits
Differential Revision: https://reviews.llvm.org/D54248
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346469
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Fri, 9 Nov 2018 01:57:00 +0000 (01:57 +0000)]
[WebAssembly] Read prefixed opcodes as ULEB128s
Summary: Depends on D54126.
Reviewers: aheejin, dschuff, aardappel
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D54138
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346465
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Fri, 9 Nov 2018 01:49:19 +0000 (01:49 +0000)]
[WebAssembly][NFC] Reorder SIMD section
Summary:
Reorders the sections in the SIMD tablegen file to roughly match the
new opcode ordering. Depends on D54126.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D54134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346464
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Fri, 9 Nov 2018 01:45:56 +0000 (01:45 +0000)]
[WebAssembly] Renumber and LEB128-encode SIMD opcodes
Reviewers: aheejin, dschuff, aardappel
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D54126
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346463
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Fri, 9 Nov 2018 01:38:44 +0000 (01:38 +0000)]
[WebAssembly] Lower select for vectors
Summary:
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346462
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Fri, 9 Nov 2018 01:17:22 +0000 (01:17 +0000)]
[not] Improve error reporting consistency.
Makes `not` use WithColor from Support so it prints 'error' in color
when applicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346460
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Fri, 9 Nov 2018 00:26:10 +0000 (00:26 +0000)]
[VFS] Add "expand tilde" argument to getRealPath.
Add an optional argument to expand tildes in the path to mirror llvm's
implementation of the corresponding function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346453
91177308-0d34-0410-b5e6-
96231b3b80d8
Petr Hosek [Thu, 8 Nov 2018 23:45:00 +0000 (23:45 +0000)]
[llvm-rc] Support absolute filenames in manifests
CMake generate manifests that contain absolute filenames and these
currently result in assertion error. This change ensures that we
handle these correctly.
Differential Revision: https://reviews.llvm.org/D54194
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346450
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Thu, 8 Nov 2018 23:20:40 +0000 (23:20 +0000)]
[docs][statepoint] Document explicitly provided stack slots
Functionality for this was added a while ago, though never documented or extensively tested. Document it with an explicit warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346448
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Thu, 8 Nov 2018 23:07:04 +0000 (23:07 +0000)]
[docs][statepoints] add a section spelling out simplifications for non-relocating GCs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346447
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Thu, 8 Nov 2018 22:56:41 +0000 (22:56 +0000)]
[docs] Add some subsections to make it possible to find portions of the statepoint overview
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346446
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Thu, 8 Nov 2018 22:56:26 +0000 (22:56 +0000)]
[WebAssembly] Fix LowerEmscriptenEHSjLj when there's only longjmp
Summary:
The pass incorrectly assumed if there's a longjmp declaration in the
module, there is also a setjmp function declaration. Fixed it, and now
the pass only converts longjmp and does not do any other transformation
when there's no setjmp declaration in the module.
Fixes PR39562.
Reviewers: jgravelle-google, sbc100
Subscribers: dschuff, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D54273
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346445
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Thu, 8 Nov 2018 21:20:52 +0000 (21:20 +0000)]
[ARM64] [Windows] Improve error reporting for unsupported SEH unwind.
Use report_fatal_error instead of crashing or miscompiling. (It's
currently easier than it should be to hit this case because we don't
reuse codes across epilogs.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346440
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Thu, 8 Nov 2018 20:44:19 +0000 (20:44 +0000)]
[LoopInterchange] Support reductions across inner and outer loop.
This patch adds logic to detect reductions across the inner and outer
loop by following the incoming values of PHI nodes in the outer loop. If
the incoming values take part in a reduction in the inner loop or come
from outside the outer loop, we found a reduction spanning across inner
and outer loop.
With this change, ~10% more loops are interchanged in the LLVM
test-suite + SPEC2006.
Fixes https://bugs.llvm.org/show_bug.cgi?id=30472
Reviewers: mcrosier, efriedma, karthikthecool, davide, hfinkel, dmgreen
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D43245
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346438
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 8 Nov 2018 20:29:17 +0000 (20:29 +0000)]
[SelectionDAG] Assert on the width of DemandedElts argument to computeKnownBits for all vector typed operations not just build_vector.
Fix AArch64 unit test that fails with the assertion added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346437
91177308-0d34-0410-b5e6-
96231b3b80d8
Pirama Arumuga Nainar [Thu, 8 Nov 2018 20:10:07 +0000 (20:10 +0000)]
[LTO] Drop non-prevailing definitions only if linkage is not local or appending
Summary:
This fixes PR 37422
In ELF, non-weak symbols can also be non-prevailing. In this particular
PR, the __llvm_profile_* symbols are non-prevailing but weren't getting
dropped - causing multiply-defined errors with lld.
Also add a test, strong_non_prevailing.ll, to ensure that multiple
copies of a strong symbol are dropped.
To fix the test regressions exposed by this fix,
- do not mark prevailing copies for symbols with 'appending' linkage.
There's no one prevailing copy for such symbols.
- fix the prevailing version in dead-strip-fulllto.ll
- explicitly pass exported symbols to llvm-lto in fumcimport.ll and
funcimport_var.ll
Reviewers: tejohnson, pcc
Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith,
dang, srhines, llvm-commits
Differential Revision: https://reviews.llvm.org/D54125
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346436
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 8 Nov 2018 19:42:11 +0000 (19:42 +0000)]
[X86] Regenerate loaduse test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346434
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 8 Nov 2018 19:16:27 +0000 (19:16 +0000)]
[x86] use shuffles for scalar insertion into high elements of a constant vector
As discussed in D54073, we have a potential regression from more aggressive vector narrowing here, so let's try to avoid that by changing build-vector lowering slightly.
Insert-vector-element lowering always does this since there's no "pinsr" for ymm/zmm:
// If the vector is wider than 128 bits, extract the 128-bit subvector, insert
// into that, and then insert the subvector back into the result.
...but we can sometimes do better for insert-into-constant-vector by using shuffle lowering.
Differential Revision: https://reviews.llvm.org/D54271
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346433
91177308-0d34-0410-b5e6-
96231b3b80d8
Nirav Dave [Thu, 8 Nov 2018 19:14:20 +0000 (19:14 +0000)]
[DAGCombine] Improve alias analysis for chain of independent stores.
FindBetterNeighborChains simulateanously improves the chain
dependencies of a chain of related stores avoiding the generation of
extra token factors. For chains longer than the GatherAllAliasDepths,
stores further down in the chain will necessarily fail, a potentially
significant waste and preventing otherwise trivial parallelization.
This patch directly parallelize the chains of stores before improving
each store. This generally improves DAG-level parallelism.
Reviewers: courbet, spatel, RKSimon, bogner, efriedma, craig.topper, rnk
Subscribers: sdardis, javed.absar, hiraditya, jrtc27, atanasyan, llvm-commits
Differential Revision: https://reviews.llvm.org/D53552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346432
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Thu, 8 Nov 2018 18:50:11 +0000 (18:50 +0000)]
[NativePDB] Higher fidelity reconstruction of AST from Debug Info.
In order to accurately put a type into the correct location in the AST
we construct from debug info, we need to be able to determine what
DeclContext (namespace, global, nested class, etc) that it goes into.
PDB doesn't contain this mapping. It does, however, contain the reverse
mapping. That is, for a given class type T, you can determine all
classes Q1, Q2, ..., Qn that are nested inside of T. We need to know,
for a given class type Q, what type T is it nested inside of.
This patch builds this map as a pre-processing step when we first
load the PDB by scanning every type. Initial tests show that while
this can be slow in debug builds of LLDB, it is quite fast in release
builds (less than 2 seconds for a ~1GB PDB, and it only needs to happen
once).
Furthermore, having this pre-processing step in place allows us to
repurpose it for building up other kinds of indexing to it down the
line. For the time being, this gives us very accurate reconstruction
of the DeclContext hierarchy.
Differential Revision: https://reviews.llvm.org/D54216
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346429
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 8 Nov 2018 18:18:20 +0000 (18:18 +0000)]
[x86] add RUNs for AVX1; NFC
Differences in splat-ability might be reason to differentiate some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346426
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Thu, 8 Nov 2018 18:15:58 +0000 (18:15 +0000)]
[NFC][BdVer2] Load and store throughput tests: also check sched stats (PR39465)
As noted by Andrea Di Biagio in https://bugs.llvm.org/show_bug.cgi?id=39465
both the loads and stores occupy both the store and load queues.
This is clearly wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346425
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Davis [Thu, 8 Nov 2018 18:08:43 +0000 (18:08 +0000)]
[llvm-mca] Partially revert r346417.
Restored the llvm:: namespace qualifier on make_unique.
This removes the ambiguity with make_unique.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346424
91177308-0d34-0410-b5e6-
96231b3b80d8
Nicolai Haehnle [Thu, 8 Nov 2018 18:01:38 +0000 (18:01 +0000)]
Add test case for the regression caused by r344696
(That change has since been reverted.)
Reduced from https://bugs.freedesktop.org/show_bug.cgi?id=108611
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346423
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Thu, 8 Nov 2018 17:57:57 +0000 (17:57 +0000)]
InstCombine: Avoid introducing poison values when lowering llvm.amdgcn.[us]bfe
Summary:
When the 3rd argument to these intrinsics is zero, lowering them
to shift instructions produces poison values, since we end up with
shift amounts equal to the number of bits in the shifted value. This
means we can only lower these intrinsics if we can prove that the
3rd argument is not zero.
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: bnieuwenhuizen, jvesely, wdng, nhaehnle, llvm-commits
Differential Revision: https://reviews.llvm.org/D53739
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346422
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Thu, 8 Nov 2018 17:57:09 +0000 (17:57 +0000)]
[CodeExtractor] Mark functions noreturn when applicable
This eliminates the outlining penalty for llvm.trap/unreachable, because
callers no longer have to emit cleanup/ret instructions after calling an
outlined `noreturn` function.
rdar://
45523626
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346421
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Thu, 8 Nov 2018 17:49:30 +0000 (17:49 +0000)]
[llvm-mca] PR39261: Rename FetchStage to EntryStage.
This fixes PR39261.
FetchStage is a misnomer. It causes confusion with the frontend fetch stage,
which we don't currently simulate. I decided to rename it into EntryStage
mainly because this is meant to be a "source" stage for all pipelines.
Differential Revision: https://reviews.llvm.org/D54268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346419
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Davis [Thu, 8 Nov 2018 17:32:45 +0000 (17:32 +0000)]
[llvm-mca] Remove unneeded namespace qualifier. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346417
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Thu, 8 Nov 2018 17:20:35 +0000 (17:20 +0000)]
[docs] Clarify ELF section naming for StackMaps and fix a typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346416
91177308-0d34-0410-b5e6-
96231b3b80d8
Adrian Prantl [Thu, 8 Nov 2018 16:54:59 +0000 (16:54 +0000)]
[dsymutil] Copy the LC_BUILD_VERSION load command into the companion binary.
LC_BUILD_VERSION contains platform information that is useful for LLDB
to match up dSYM bundles with binaries. This patch copies the load
command over into the dSYM.
rdar://problem/
44145175
rdar://problem/
45883463
Differential Revision: https://reviews.llvm.org/D54233
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346412
91177308-0d34-0410-b5e6-
96231b3b80d8
Jinsong Ji [Thu, 8 Nov 2018 16:51:42 +0000 (16:51 +0000)]
[PowerPC][llvm-exegesis] Add a PowerPC target
This is patch to add PowerPC target to llvm-exegesis.
The target does just enough to be able to run llvm-exegesis in latency mode for at least some opcodes.
Differential Revision: https://reviews.llvm.org/D54185
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346411
91177308-0d34-0410-b5e6-
96231b3b80d8
Davide Italiano [Thu, 8 Nov 2018 16:21:29 +0000 (16:21 +0000)]
Revert "[MSP430] Add MC layer"
This commit broke the module buildbots.
Error:
lib/Target/MSP430/MSP430GenAsmMatcher.inc:1027:1: error: redundant
namespace 'llvm' [-Wmodules-import-nested-redundant]
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346410
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Paulsson [Thu, 8 Nov 2018 15:29:48 +0000 (15:29 +0000)]
[SystemZ] Bugfix in shouldCoalesce()
It was discovered in randomized testing that the SystemZ implementation of
shouldCoalesce() could be caused to crash when subreg liveness was
enabled. This was because an undef use of the virtual register was copied
outside current MBB at the point of shouldCoalesce() being called. For more
details, see https://bugs.llvm.org/show_bug.cgi?id=39276.
This patch changes the check for MBB locality from livein/liveout checks to
do checks for all instructions of both intervals being inside MBB. This
avoids the cases with dead defs / undef uses outside MBB, which are not
affecting liveness in/out of MBB.
The original test case included as a reduced .mir test case.
Review: Ulrich Weigand
https://reviews.llvm.org/D54197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346406
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Thu, 8 Nov 2018 15:17:10 +0000 (15:17 +0000)]
[docs] Clarify expectations for stack map sections and AOT compilers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346405
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Thu, 8 Nov 2018 14:48:56 +0000 (14:48 +0000)]
[NFC][BdVer2] Tests for load and store throughput (PR39465)
During review it was noted that while it appears that
the Piledriver can do two [consecutive] loads per cycle,
it can only do one store per cycle. It was suggested
that the sched model incorrectly models that,
but it was opted to fix this afterwards.
These tests show that the two consecutive loads are
modelled correctly, and one consecutive stores is not
modelled incorrectly. Unless i'm missing the point.
https://bugs.llvm.org/show_bug.cgi?id=39465
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346404
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexandre Ganea [Thu, 8 Nov 2018 14:42:37 +0000 (14:42 +0000)]
[LLD] Fix Microsoft precompiled headers cross-compile on Linux
Differential revision: https://reviews.llvm.org/D54122
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346403
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 8 Nov 2018 14:07:17 +0000 (14:07 +0000)]
[X86][SSE] Add PR39387 shuffle test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346402
91177308-0d34-0410-b5e6-
96231b3b80d8
Petr Pavlu [Thu, 8 Nov 2018 13:02:10 +0000 (13:02 +0000)]
[ARM] Enable spilling of the hGPR register class in Thumb2
Generalize code in Thumb2InstrInfo::storeRegToStackSlot() and
loadRegToStackSlot() to allow the GPR class or any of its sub-classes
(including hGPR) to be stored/loaded by ARM::t2STRi12/ARM::t2LDRi12.
Differential Revision: https://reviews.llvm.org/D51927
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346401
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Thu, 8 Nov 2018 12:37:56 +0000 (12:37 +0000)]
[llvm-exegesis][NFC] Add missing header guard + cosmetics.
Reviewers: gchatelet
Reviewed By: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D54252
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346400
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 8 Nov 2018 12:14:10 +0000 (12:14 +0000)]
[X86][AVX] Tidyup prefixes and regenerate interleaved tests
Share common AVX prefix and split off AVX2OR512 prefix instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346399
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Thu, 8 Nov 2018 12:09:45 +0000 (12:09 +0000)]
Revert "[llvm-exegesis] Add a snippet generator to generate snippets to compute ROB sizes."
This reverts accidental commit rL346394.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346398
91177308-0d34-0410-b5e6-
96231b3b80d8
Max Kazantsev [Thu, 8 Nov 2018 11:54:35 +0000 (11:54 +0000)]
Return "[IndVars] Smart hard uses detection"
The patch has been reverted because it ended up prohibiting propagation
of a constant to exit value. For such values, we should skip all checks
related to hard uses because propagating a constant is always profitable.
Differential Revision: https://reviews.llvm.org/D53691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346397
91177308-0d34-0410-b5e6-
96231b3b80d8
Renato Golin [Thu, 8 Nov 2018 11:51:27 +0000 (11:51 +0000)]
Adding Yvan as release test backup for Diana
Thanks for offering to help, Yvan! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346396
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Thu, 8 Nov 2018 11:45:14 +0000 (11:45 +0000)]
[llvm-exegesis] Add a snippet generator to generate snippets to compute ROB sizes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346394
91177308-0d34-0410-b5e6-
96231b3b80d8
Anton Korobeynikov [Thu, 8 Nov 2018 10:17:52 +0000 (10:17 +0000)]
[MSP430] Fix encodeInstruction() for big endian hosts
Reviewers: asl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D54251
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346391
91177308-0d34-0410-b5e6-
96231b3b80d8
Gil Rapaport [Thu, 8 Nov 2018 09:01:19 +0000 (09:01 +0000)]
[LSR] Combine unfolded offset into invariant register
LSR reassociates constants as unfolded offsets when the constants fit as
immediate add operands, which currently prevents such constants from being
combined later with loop invariant registers.
This patch modifies GenerateCombinations() to generate a second formula which
includes the unfolded offset in the combined loop-invariant register.
This commit fixes a bug in the original patch (committed at r345114, reverted
at r345123).
Differential Revision: https://reviews.llvm.org/D51861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346390
91177308-0d34-0410-b5e6-
96231b3b80d8
Max Kazantsev [Thu, 8 Nov 2018 05:07:58 +0000 (05:07 +0000)]
[SCEV][NFC] Verify IR in isLoop[Entry,Backedge]GuardedByCond
We have a lot of various bugs that are caused by misuse of SCEV (in particular in LV),
all of them can simply be described as "we ask SCEV to prove some fact on invalid IR".
Some of examples of those are PR36311, PR37221, PR39160.
The problem is that these failues manifest differently (what we saw was failure of various
asserts across SCEV, but there can also be miscompiles). This patch adds an assert into two
SCEV methods that strongly rely on correctness of the IR and are involved in known failues.
This will at least allow us to have a clear indication of what was wrong in this case.
This patch also fixes a unit test with incorrect IR that fails this verification.
Differential Revision: https://reviews.llvm.org/D52930
Reviewed By: fhahn
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346389
91177308-0d34-0410-b5e6-
96231b3b80d8
whitequark [Thu, 8 Nov 2018 04:04:04 +0000 (04:04 +0000)]
[bindings/go] Add Go bindings to LLVMGetIndices
Summary: This instruction is useful for inspecting extractvalue/insertvalue in IR. Unlike most other operations, indices cannot be inspected using the generic Value.Opcode() function so a specialized function needs to be added.
Reviewers: whitequark, pcc
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53883
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346388
91177308-0d34-0410-b5e6-
96231b3b80d8
whitequark [Thu, 8 Nov 2018 04:00:18 +0000 (04:00 +0000)]
[OCaml] Fix incorrect use of CAMLlocal in nested blocks
Summary:
The OCaml manual states:
> Local variables of type value must be declared with one of the
> CAMLlocal macros. [...] These macros must be used at the beginning
> of the function, not in a nested block.
This patch moves several instances of CAMLlocal macros from nested
blocks to the function beginning.
Reviewers: whitequark
Reviewed By: whitequark
Subscribers: CodaFi, llvm-commits
Differential Revision: https://reviews.llvm.org/D53841
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346387
91177308-0d34-0410-b5e6-
96231b3b80d8
whitequark [Thu, 8 Nov 2018 03:58:01 +0000 (03:58 +0000)]
[MergeFuncs] Improve ordering of equal functions
Summary:
MergeFunctions currently tries to process strong functions before
weak functions, because weak functions can simply call strong
functions, while a strong/weak function cannot call a weak function
(a backing strong function is needed).
This patch additionally tries to process external functions before
local functions, because we definitely have to keep the external
function, but may be able to drop the local one (and definitely
can if it is also unnamed_addr).
Unfortunately, this exposes an existing bug in the implementation:
The FnTree and FNodesInTree structures can currently go out of
sync in the case where two weak functions are merged, because the
function in FnTree/FNodesInTree is RAUWed. This leaves it behind in
FnTree (this is intended, as it is the strong backing function which
should be used for further merges), while it is replaced in
FNodesInTree (this is not intended).
This is fixed by switching FNodesInTree from using a ValueMap to
using a DenseMap of AssertingVH.
This exposes another minor issue: Currently FNodesInTree is not
cleared after MergeFunctions finishes running. Currently, this is
potentially dangerous (e.g. if something else wants to RAUW a function
with a non-function), but at the very least it is unnecessary/inefficient.
After the change to use AssertingVH it becomes more problematic,
because there are certainly passes that remove functions.
This issue is fixed by clearing FNodesInTree at the end of the pass.
Reviewers: jfb, whitequark
Reviewed By: whitequark
Subscribers: rkruppe, llvm-commits
Differential Revision: https://reviews.llvm.org/D53271
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346386
91177308-0d34-0410-b5e6-
96231b3b80d8
whitequark [Thu, 8 Nov 2018 03:57:55 +0000 (03:57 +0000)]
[MergeFuncs] Call removeUsers() prior to unnamed_addr RAUW
Summary:
For unnamed_addr functions we RAUW instead of only replacing direct callers. However, functions in which replacements were performed currently are not added back to the worklist, resulting in missed merging opportunities.
Fix this by calling removeUsers() prior to RAUW.
Reviewers: jfb, whitequark
Reviewed By: whitequark
Subscribers: rkruppe, llvm-commits
Differential Revision: https://reviews.llvm.org/D53262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346385
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Thu, 8 Nov 2018 02:35:28 +0000 (02:35 +0000)]
[WebAssembly] Add V128 to WebAssemblyInstrInfo::copyPhysReg
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53872
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346384
91177308-0d34-0410-b5e6-
96231b3b80d8
Nathan Lanza [Thu, 8 Nov 2018 01:10:24 +0000 (01:10 +0000)]
Revert "Reorder FindPythonInterp so that config-ix can use PYTHON_EXECUTABLE"
This reverts commit rL346367 due to test error in compiler-rt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346383
91177308-0d34-0410-b5e6-
96231b3b80d8