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Sam Clegg [Thu, 14 Jun 2018 17:11:19 +0000 (17:11 +0000)]
Revert "[MC] Factor MCObjectStreamer::addFragmentAtoms out of MachO streamer."
This reverts rL331412. We didn't up using fragment atoms
in the wasm object writer after all.
Differential Revision: https://reviews.llvm.org/D48173
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334734
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Tony Tye [Thu, 14 Jun 2018 16:40:10 +0000 (16:40 +0000)]
[AMDGPU] Document the AMDGPU LLVM attributes
Differential Revision: https://reviews.llvm.org/D48101
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334733
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Bjorn Pettersson [Thu, 14 Jun 2018 16:08:22 +0000 (16:08 +0000)]
Revert rL334704: "[DebugInfo] Check size of variable in ConvertDebugDeclareToDebugValue"
This reverts commit r334704.
Buildbots detected an assertion in "test tsan in debug compiler-rt build".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334732
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Nirav Dave [Thu, 14 Jun 2018 15:55:15 +0000 (15:55 +0000)]
Avoid unused variable in non-assert builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334731
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Andrea Di Biagio [Thu, 14 Jun 2018 15:54:34 +0000 (15:54 +0000)]
[llvm-mca] Add another test for partial register stalls.
This test checks that a physical register is correctly allocated for the partial
write to register BX.
The ADD instruction has to wait for the write to RBX (and BX) before being
executed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334730
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Nirav Dave [Thu, 14 Jun 2018 15:46:23 +0000 (15:46 +0000)]
[DAG] Avoid needing to walk out legalization tables. NFCI.
To avoid redundant work, during DAG legalization we keep tables
mapping pre-legalized SDValues to post-legalized SDValues and a
SDValue-to-SDValue map to enable fast node replacements. However, as
the keys are nodes which may be reused it is possible that an entry in
a table refers to a now deleted node N (that should have been renamed
by the value replacement map) while a new node N' exists. If N' is
then replaced that entry would be wrong. Previously we avoided this by
when potentially violating this property, walking every table and
updating all node pointers. This is very expensive but hopefully rare
occurance.
This patch assigns each instance of a SDValue used in legalization a
unique id and uses these ids in the legalization tables. This avoids
any such aliasing issue, avoiding the full table search and allowing
more aggressive incremental table pruning.
In some cases this is a 1000x speedup to compilation.
Reviewers: jyknight, echristo, bogner, tra
Reviewed By: bogner
Subscribers: dberris, grandinj, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D47959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334729
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Craig Topper [Thu, 14 Jun 2018 15:40:31 +0000 (15:40 +0000)]
[X86] Add more vector instructions to the memory folding table using the autogenerated table as a guide.
The test cahnge is because we now fold stack reload into RNDSCALE and RNDSCALE can be turned into ROUND by EVEX->VEX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334728
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Craig Topper [Thu, 14 Jun 2018 15:40:30 +0000 (15:40 +0000)]
[X86] Remove '128' from the internal name of some scalar FP instructions to be consistent with other scalar instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334727
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Craig Topper [Thu, 14 Jun 2018 15:40:29 +0000 (15:40 +0000)]
[X86] Disable load unfolding for a bunch of instruction where unfolding would increase the size of the load.
Found by an audit of the manual table vs the autogenerated table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334726
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Craig Topper [Thu, 14 Jun 2018 15:40:27 +0000 (15:40 +0000)]
[X86] Remove NotMemoryFoldable from some AVX/AVX512 scalar instructions.
Some of these instructions are already in the manual folding table so we should have them in the auto table too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334725
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Lang Hames [Thu, 14 Jun 2018 15:32:59 +0000 (15:32 +0000)]
[ORC] Filter out self-dependencies in VSO::addDependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334724
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Lang Hames [Thu, 14 Jun 2018 15:32:59 +0000 (15:32 +0000)]
[ORC] Assert that the query argument to VSO::lookup must be non-null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334723
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Lang Hames [Thu, 14 Jun 2018 15:32:58 +0000 (15:32 +0000)]
[ORC] Add a WaitUntilReady argument to blockingLookup.
If WaitUntilReady is set to true then blockingLookup will return once all
requested symbols are ready. If WaitUntilReady is set to false then
blockingLookup will return as soon as all requested symbols have been
resolved. In the latter case, if any error occurs in finalizing the symbols it
will be reported to the ExecutionSession, rather than returned by
blockingLookup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334722
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Lang Hames [Thu, 14 Jun 2018 15:32:56 +0000 (15:32 +0000)]
[ORC] Strip the Materializing flag off finalized symbols in VSOs.
Finalized symbols are no longer in the materializing state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334721
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Simon Dardis [Thu, 14 Jun 2018 15:16:37 +0000 (15:16 +0000)]
[docs] Update CompilerWriterInfo.rst for MIPS
Update the URL of where the documentation can be found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334720
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Simon Pilgrim [Thu, 14 Jun 2018 14:22:03 +0000 (14:22 +0000)]
[EarlyCSE] Fix MSVC build. NFCI.
MSVC doesn't let you assign different lambdas through a ternary operator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334715
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Simon Pilgrim [Thu, 14 Jun 2018 14:20:20 +0000 (14:20 +0000)]
[CostModel][AArch64] Add cost tests for ALTERNATE/SELECT style shuffle masks
Precursor to fixing a regression with SLP vectorizer for supporting SELECT shuffles (vs the current ALTERNATE)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334714
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Sam Clegg [Thu, 14 Jun 2018 14:04:23 +0000 (14:04 +0000)]
[MC] Move MCAssembler::dump into the correct cpp file. NFC
Differential Revision: https://reviews.llvm.org/D46556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334713
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Paul Robinson [Thu, 14 Jun 2018 13:38:20 +0000 (13:38 +0000)]
[DWARFv5] Tolerate files not all having an MD5 checksum.
In some cases, for example when compiling a preprocessed file, the
front-end is not able to provide an MD5 checksum for all files. When
that happens, omit the MD5 checksums from the final DWARF, because
DWARF doesn't have a way to indicate that some but not all files have
a checksum.
When assembling a .s file, and some but not all .file directives
provide an MD5 checksum, issue a warning and don't emit MD5 into the
DWARF.
Fixes PR37623.
Differential Revision: https://reviews.llvm.org/D48135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334710
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Simon Dardis [Thu, 14 Jun 2018 13:03:53 +0000 (13:03 +0000)]
[mips] Correct predicates for MSA pseudo instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334708
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Max Kazantsev [Thu, 14 Jun 2018 13:02:13 +0000 (13:02 +0000)]
[EarlyCSE] Propagate conditions of AND and OR instructions
This patches teaches EarlyCSE to figure out that if `and i1 %x, %y` is true then both
`%x` and `%y` are true in the taken branch, and if `or i1 %x, %y` is false then both
`%x` and `%y` are false in non-taken branch. Fix for PR37635.
Differential Revision: https://reviews.llvm.org/D47574
Reviewed By: reames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334707
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Florian Hahn [Thu, 14 Jun 2018 11:56:19 +0000 (11:56 +0000)]
[TableGen] Move some shared_ptrs to avoid unnecessary copies (NFC).
Those changes were suggested post-commit for D47463.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334706
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Bjorn Pettersson [Thu, 14 Jun 2018 11:23:42 +0000 (11:23 +0000)]
[DebugInfo] Check size of variable in ConvertDebugDeclareToDebugValue
Summary:
Do not convert a DbgDeclare to DbgValue if the store
instruction only refer to a fragment of the variable
described by the DbgDeclare.
Problem was seen when for example having an alloca for an
array or struct, and there were stores to individual elements.
In the past we inserted a DbgValue intrinsics for each store,
just as if the store wrote the whole variable.
When handling store instructions we insert a DbgValue that
indicates that the variable is "undefined", as we do not know
which part of the variable that is updated by the store.
When ConvertDebugDeclareToDebugValue is used with a load/phi
instruction we assert that the referenced value is large enough
to cover the whole variable. Afaict this should be true for all
scenarios where those methods are used on trunk. If the assert
blows in the future I guess we could simply skip to insert a
dbg.value instruction.
In the future I think we should examine which part of the variable
that is accessed, and add a DbgValue instrinsic with an appropriate
DW_OP_LLVM_fragment expression.
Reviewers: dblaikie, aprantl, rnk
Reviewed By: aprantl
Subscribers: JDevlieghere, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D48024
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334704
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Simon Pilgrim [Thu, 14 Jun 2018 10:25:19 +0000 (10:25 +0000)]
[SLPVectorizer] Remove RawInstructionsData/getMainOpcode and merge into getSameOpcode
This is part of the work to cleanup use of 'alternate' ops so we can use the more general SK_Select shuffle type.
Only getSameOpcode calls getMainOpcode and much of the logic is repeated in both functions. This will require some reworking of D28907 but that patch has hit trouble and is unlikely to be completed anytime soon.
Differential Revision: https://reviews.llvm.org/D48120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334701
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Simon Pilgrim [Thu, 14 Jun 2018 09:48:19 +0000 (09:48 +0000)]
[CostModel] Cleanup isSingleSourceVectorMask to match other shuffle matchers. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334699
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Simon Pilgrim [Thu, 14 Jun 2018 09:35:00 +0000 (09:35 +0000)]
[CostModel] Recognise REVERSE shuffle mask if the elements come from the second src
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334698
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Clement Courbet [Thu, 14 Jun 2018 06:57:52 +0000 (06:57 +0000)]
[llvm-exegesis] Use BenchmarkResult::Instructions instead of OpcodeName
Summary:
Get rid of OpcodeName.
To remove the opcode name from an old file:
```
cat old_file | sed '/opcode_name.*/d'
```
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48121
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334691
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Hiroshi Inoue [Thu, 14 Jun 2018 05:41:49 +0000 (05:41 +0000)]
[NFC] fix trivial typos in comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334687
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Craig Topper [Thu, 14 Jun 2018 03:16:58 +0000 (03:16 +0000)]
[x86] fix mappings of cvttp2si/cvttp2ui x86 intrinsics to x86-specific nodes and isel patterns (PR37551)
Summary:
The tests in:
https://bugs.llvm.org/show_bug.cgi?id=37751
...show miscompiles because we wrongly mapped and folded x86-specific intrinsics into generic DAG nodes.
This patch corrects the mappings in X86IntrinsicsInfo.h and adds isel matching corresponding to the new patterns. The complete tests for the failure cases should be in avx-cvttp2si.ll and sse-cvttp2si.ll and avx512-cvttp2i.ll
Reviewers: RKSimon, gbedwell, spatel
Reviewed By: spatel
Subscribers: mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D47993
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334685
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Matt Davis [Thu, 14 Jun 2018 01:20:18 +0000 (01:20 +0000)]
[llvm-mca] Introduce the ExecuteStage (was originally the Scheduler class).
Summary: This patch transforms the Scheduler class into the ExecuteStage. Most of the logic remains.
Reviewers: andreadb, RKSimon, courbet
Reviewed By: andreadb
Subscribers: mgorny, javed.absar, tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D47246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334679
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Tom Stellard [Wed, 13 Jun 2018 22:30:47 +0000 (22:30 +0000)]
AMDGPU/GlobalISel: Implement select() for 32-bit G_FADD and G_FMUL
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D46171
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334665
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Zachary Turner [Wed, 13 Jun 2018 21:24:19 +0000 (21:24 +0000)]
Revert "Enable ThreadPool to queue tasks that return values."
This is failing to compile when LLVM_ENABLE_THREADS is false,
and the fix is not immediately obvious, so reverting while I look
into it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334658
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Francis Visoiu Mistrih [Wed, 13 Jun 2018 21:03:56 +0000 (21:03 +0000)]
Reland: [Timers] Use the pass argument name for JSON keys in time-passes
When using clang --save-stats -mllvm -time-passes, both timers and stats
end up in the same json file.
We could end up with things like:
{
"asm-printer.EmittedInsts": 1,
"time.pass.Virtual Register Map.wall": 2.
9015541076660156e-04,
"time.pass.Virtual Register Map.user": 2.
0500000000000379e-04,
"time.pass.Virtual Register Map.sys": 8.
5000000000001741e-05,
}
This patch makes use of the pass argument name (if available) in the
JSON key to end up with things like:
{
"asm-printer.EmittedInsts": 1,
"time.pass.virtregmap.wall": 2.
9015541076660156e-04,
"time.pass.virtregmap.user": 2.
0500000000000379e-04,
"time.pass.virtregmap.sys": 8.
5000000000001741e-05,
}
This also helps avoiding to write another JSON printer to handle all the
cases that we could have in our pass names.
Fixed test instead of adding a new one originally from r334649.
Differential Revision: https://reviews.llvm.org/D48109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334657
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Florian Hahn [Wed, 13 Jun 2018 20:59:53 +0000 (20:59 +0000)]
[TableGen] Make getOnlyTree return a const ref (NFC)
This avoids some unnecessary copies of shared_ptrs.
Those changes were suggested post-commit for D47463.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334656
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George Karpenkov [Wed, 13 Jun 2018 20:48:53 +0000 (20:48 +0000)]
Update comments of CheckedArithmetic API based on Philip Reames feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334655
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Reid Kleckner [Wed, 13 Jun 2018 20:47:21 +0000 (20:47 +0000)]
[WinASan] Don't instrument globals in sections containing '$'
Such globals are very likely to be part of a sorted section array, such
the .CRT sections used for dynamic initialization. The uses its own
sorted sections called ATL$__a, ATL$__m, and ATL$__z. Instead of special
casing them, just look for the dollar sign, which is what invokes linker
section sorting for COFF.
Avoids issues with ASan and the ATL uncovered after we started
instrumenting comdat globals on COFF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334653
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Francis Visoiu Mistrih [Wed, 13 Jun 2018 20:44:02 +0000 (20:44 +0000)]
Revert r334649 "[Timers] Use the pass argument name for JSON keys in time-passes"
This reverts commit r334649.
This breaks a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334651
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Francis Visoiu Mistrih [Wed, 13 Jun 2018 20:09:59 +0000 (20:09 +0000)]
[Timers] Use the pass argument name for JSON keys in time-passes
When using clang --save-stats -mllvm -time-passes, both timers and stats
end up in the same json file.
We could end up with things like:
{
"asm-printer.EmittedInsts": 1,
"time.pass.Virtual Register Map.wall": 2.
9015541076660156e-04,
"time.pass.Virtual Register Map.user": 2.
0500000000000379e-04,
"time.pass.Virtual Register Map.sys": 8.
5000000000001741e-05,
}
This patch makes use of the pass argument name (if available) in the
JSON key to end up with things like:
{
"asm-printer.EmittedInsts": 1,
"time.pass.virtregmap.wall": 2.
9015541076660156e-04,
"time.pass.virtregmap.user": 2.
0500000000000379e-04,
"time.pass.virtregmap.sys": 8.
5000000000001741e-05,
}
This also helps avoiding to write another JSON printer to handle all the
cases that we could have in our pass names.
Differential Revision: https://reviews.llvm.org/D48109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334649
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Craig Topper [Wed, 13 Jun 2018 20:03:42 +0000 (20:03 +0000)]
[X86] Move RCPSSr_Int, RSQRTSSr_Int, SQRTSDr_Int, SQRTSSr_Int to the correct load folding table.
They were in the operand 1 folding table, but their foldable operand is operand 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334648
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Zachary Turner [Wed, 13 Jun 2018 19:37:41 +0000 (19:37 +0000)]
Add missing #include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334644
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Zachary Turner [Wed, 13 Jun 2018 19:29:16 +0000 (19:29 +0000)]
Enable ThreadPool to support tasks that return values.
Previously ThreadPool could only queue async "jobs", i.e. work
that was done for its side effects and not for its result. It's
useful occasionally to queue async work that returns a value.
From an API perspective, this is very intuitive. The previous
API just returned a shared_future<void>, so all we need to do is
make it return a shared_future<T>, where T is the type of value
that the operation returns.
Making this work required a little magic, but ultimately it's not
too bad. Instead of keeping a shared queue<packaged_task<void()>>
we just keep a shared queue<unique_ptr<TaskBase>>, where TaskBase
is a class with a pure virtual execute() method, then have a
templated derived class that stores a packaged_task<T()>. Everything
else works out pretty cleanly.
Differential Revision: https://reviews.llvm.org/D48115
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334643
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Stanislav Mekhanoshin [Wed, 13 Jun 2018 18:52:54 +0000 (18:52 +0000)]
[AMDGPU] Corrected computeKnownBits for V_PERM_B32
Differential Revision: https://reviews.llvm.org/D48133
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334640
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George Karpenkov [Wed, 13 Jun 2018 18:32:02 +0000 (18:32 +0000)]
Add checkMulAdd helper function to CheckedArithmetic
Multiplication followed by addition
(https://en.wikipedia.org/wiki/Multiply–accumulate_operation) is a
sufficiently common use-case to warrant a separate helper.
Differential Revision: https://reviews.llvm.org/D48138
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334635
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George Karpenkov [Wed, 13 Jun 2018 18:31:43 +0000 (18:31 +0000)]
Change checked arithmetic functions API to return Optional
Returning optional is much safer.
The previous API had potential to cause use of undefined variables, if
the value passed by pointer was accidentally read afterwards.
Differential Revision: https://reviews.llvm.org/D48137
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334634
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Andrea Di Biagio [Wed, 13 Jun 2018 18:30:14 +0000 (18:30 +0000)]
[llvm-mca] Fixed a bug in the logic that checks if a memory operation is ready to execute.
Fixes PR37790.
In some (very rare) cases, the LSUnit (Load/Store unit) was wrongly marking a
load (or store) as "ready to execute" effectively bypassing older memory barrier
instructions.
To reproduce this bug, the memory barrier must be the first instruction in the
input assembly sequence, and it doesn't have to perform any register writes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334633
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Jordan Rose [Wed, 13 Jun 2018 18:21:47 +0000 (18:21 +0000)]
[CMake] Handle 'libtool' being at a path with spaces in it.
This can happen on macOS if the user's Xcode is at a path with spaces in it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334632
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Peter Collingbourne [Wed, 13 Jun 2018 18:03:14 +0000 (18:03 +0000)]
LTO: Keep file handles open for memory mapped files.
On Windows we've observed that if you open a file, write to it, map it into
memory and close the file handle, the contents of the memory mapping can
sometimes be incorrect. That was what we did when adding an entry to the
ThinLTO cache using the TempFile and MemoryBuffer classes, and it was causing
intermittent build failures on Chromium's ThinLTO bots on Windows. More
details are in the associated Chromium bug (crbug.com/786127).
We can prevent this from happening by keeping a handle to the file open while
the mapping is active. So this patch changes the mapped_file_region class to
duplicate the file handle when mapping the file and close it upon unmapping it.
One gotcha is that the file handle that we keep open must not have been
created with FILE_FLAG_DELETE_ON_CLOSE, as otherwise the operating system
will prevent other processes from opening the file. We can achieve this
by avoiding the use of FILE_FLAG_DELETE_ON_CLOSE altogether. Instead,
we use SetFileInformationByHandle with FileDispositionInfo to manage the
delete-on-close bit. This lets us remove the hack that we used to use to
clear the delete-on-close bit on a file opened with FILE_FLAG_DELETE_ON_CLOSE.
A downside of using SetFileInformationByHandle/FileDispositionInfo as
opposed to FILE_FLAG_DELETE_ON_CLOSE is that it prevents us from using
CreateFile to open the file while the flag is set, even within the same
process. This doesn't seem to matter for almost every client of TempFile,
except for LockFileManager, which calls sys::fs::create_link to create a
hard link from the lock file, and in the process of doing so tries to open
the file. To prevent this change from breaking LockFileManager I changed it
to stop using TempFile by effectively reverting r318550.
Differential Revision: https://reviews.llvm.org/D48051
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334630
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Craig Topper [Wed, 13 Jun 2018 17:55:13 +0000 (17:55 +0000)]
[X86] Add one more intrinsic and test cases to avx512-cvttp2i.ll.
spatel noticed it was missing in D47993.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334629
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Saleem Abdulrasool [Wed, 13 Jun 2018 17:51:27 +0000 (17:51 +0000)]
IR: fix documentation markup
Use `\brief` instead of `\Brief`. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334627
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Yaxun Liu [Wed, 13 Jun 2018 17:31:51 +0000 (17:31 +0000)]
[AMDGPU] Change enqueue kernel handle type
Currently the handle type is a global pointer which holds 8 bytes.
We need a larger type which hold 16 bytes, therefore change it
to [i64 x 2].
Differential Revision: https://reviews.llvm.org/D48094
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334625
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Simon Pilgrim [Wed, 13 Jun 2018 17:12:11 +0000 (17:12 +0000)]
[CostModel][X86] Test showing failure to recognise REVERSE shuffle mask if the elements come from the second src
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334623
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Dmitry Preobrazhensky [Wed, 13 Jun 2018 17:02:03 +0000 (17:02 +0000)]
[AMDGPU][MC] Enabled parsing of relocations on VALU instructions
See bug 37566: https://bugs.llvm.org/show_bug.cgi?id=37566
Reviewers: artem.tamazov, arsenm, nhaehnle
Differential Revision: https://reviews.llvm.org/D47884
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334622
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Simon Pilgrim [Wed, 13 Jun 2018 16:52:02 +0000 (16:52 +0000)]
[CostModel] Recognise BROADCAST shuffle mask if the elements come from the second src
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334620
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Andrea Di Biagio [Wed, 13 Jun 2018 16:33:52 +0000 (16:33 +0000)]
Revert: [llvm-mca] Flush the output stream before we start the analysis of a new code region. NFC
Not sure why, but it breaks buildbot clang-cmake-armv8-full.
It causes a failure in TEST 'Xray-armhf-linux :: TestCases/Posix/profiling-single-threaded.cc'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334617
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Simon Pilgrim [Wed, 13 Jun 2018 16:33:42 +0000 (16:33 +0000)]
[CostModel][X86] Test showing failure to recognise BROADCAST shuffle mask if the elements come from the second src
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334616
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Andrea Di Biagio [Wed, 13 Jun 2018 15:43:56 +0000 (15:43 +0000)]
[llvm-mca] Flush the output stream before we start the analysis of a new code region. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334610
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Dmitry Preobrazhensky [Wed, 13 Jun 2018 15:32:46 +0000 (15:32 +0000)]
[AMDGPU][MC][GFX8][GFX9] Allow LDS direct reads for BUFFER_LOAD_DWORDX2/X3/X4
See bug 37653: https://bugs.llvm.org/show_bug.cgi?id=37653
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D47885
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334609
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Sanjay Patel [Wed, 13 Jun 2018 15:22:48 +0000 (15:22 +0000)]
[DAGCombiner] remove hasOneUse() check from fadd constants transform
We're constant folding here, so we shouldn't check uses. This matches
the IR optimizer behavior.
The x86 test shows the expected win. The AArch64 test shows something
else. This only seems to happen if the "generic" AArch64 CPU model is
used by MachineCombiner, so I'll file a bug report to follow-up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334608
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Tom Stellard [Wed, 13 Jun 2018 15:06:37 +0000 (15:06 +0000)]
AMDGPU: Move isSDNodeSourceOfDivergence() implementation to SITargetLowering
Summary:
The code that handles ISD:Register and ISD::CopyFromReg assumes
the target is amdgcn, so this is broken on r600. We don't
need this analysis on r600 anyway so we can safely move
it to SITargetLowering.
Reviewers: alex-t, arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: msearles, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D46298
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334607
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Sanjay Patel [Wed, 13 Jun 2018 15:01:07 +0000 (15:01 +0000)]
[x86] add test for fadd with more than one use; NFC
The equivalent AArch64 test added at rL334556 isn't showing
the expected output from the DAGCombiner code change that
would fix this example. That's a machine combiner bug from
what I see.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334605
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Cameron McInally [Wed, 13 Jun 2018 14:32:12 +0000 (14:32 +0000)]
[FPEnv] Expand constrained FP operations
Add a helper function to expand constrained FP operations as needed.
Note that the Strict POWI operation is not handled in this patch since
the format is slightly different from the others.
Differential Revision: https://reviews.llvm.org/D47491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334603
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Hans Wennborg [Wed, 13 Jun 2018 14:29:26 +0000 (14:29 +0000)]
Do not enforce absolute path argv0 in windows
Even if we support no-canonical-prefix on
clang-cl(https://reviews.llvm.org/D47480), argv0 becomes absolute path
in clang-cl and that embeds absolute path in /showIncludes.
This patch removes such full path normalization from InitLLVM on
windows, and that removes absolute path from clang-cl output
(obj/stdout/stderr) when debug flag is disabled.
Patch by Takuto Ikuta!
Differential Revision https://reviews.llvm.org/D47578
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334602
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Guillaume Chatelet [Wed, 13 Jun 2018 14:07:36 +0000 (14:07 +0000)]
[llvm-exegesis] Fix buildbot - power was using native target for X86.
Reviewers: courbet
Reviewed By: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48125
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334601
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Guillaume Chatelet [Wed, 13 Jun 2018 13:53:56 +0000 (13:53 +0000)]
[llvm-exegesis] Fix failing assert when creating Snippet for LAHF.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334599
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Krzysztof Parzyszek [Wed, 13 Jun 2018 13:49:06 +0000 (13:49 +0000)]
Revert "Improve handling of COPY instructions with identical value numbers"
This reverts r334594, it breaks buildbots and fails with expensive checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334598
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Guillaume Chatelet [Wed, 13 Jun 2018 13:24:41 +0000 (13:24 +0000)]
[llvm-exegesis] Cleaner design without mutable data.
Summary: Previous design was relying on the 'mutate' keyword and was quite confusing. This version separate mutable from immutable data and makes it clearer what changes and what doesn't.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48020
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334596
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Zoran Jovanovic [Wed, 13 Jun 2018 12:51:37 +0000 (12:51 +0000)]
[mips][microMIPS] Extending size reduction pass with LWP and SWP
Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
It introduces reduction of two instructions into one instruction:
Two SW instructions are transformed into one SWP instrucition.
Two LW instructions are transformed into one LWP instrucition.
Differential Revision: https://reviews.llvm.org/D39115
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334595
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Krzysztof Parzyszek [Wed, 13 Jun 2018 12:47:17 +0000 (12:47 +0000)]
Improve handling of COPY instructions with identical value numbers
Differential Revision: https://reviews.llvm.org/D48102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334594
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Sanjay Patel [Wed, 13 Jun 2018 12:28:32 +0000 (12:28 +0000)]
[x86] eliminate even more sign-bit tests with vector select
This shortcoming was noted in D47330, and the test diffs show we already
had other examples where we failed to fold to a SHRUNKBLEND:
/// Dynamic (non-constant condition) vector blend where only the sign bits
/// of the condition elements are used. This is used to enforce that the
/// condition mask is not valid for generic VSELECT optimizations.
This patch implements an idea from D48043 and would obsolete that patch
because it catches more cases (notable the AVX1 case that was missed there).
All we're doing is allowing the existing transform to fire more often by
removing the post-legalize constraint. All of the relevant feature checks
and other predicates are left as-is.
Differential Revision: https://reviews.llvm.org/D48078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334592
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Alex Bradbury [Wed, 13 Jun 2018 12:04:51 +0000 (12:04 +0000)]
[RISCV] Add codegen support for atomic load/stores with RV32A
Fences are inserted according to table A.6 in the current draft of version 2.3
of the RISC-V Instruction Set Manual, which incorporates the memory model
changes and definitions contributed by the RISC-V Memory Consistency Model
task group.
Instruction selection failures will now occur for 8/16/32-bit atomicrmw and
cmpxchg operations when targeting RV32IA until lowering for these operations
is added in a follow-on patch.
Differential Revision: https://reviews.llvm.org/D47589
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334591
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Alex Bradbury [Wed, 13 Jun 2018 11:58:46 +0000 (11:58 +0000)]
[RISCV] Codegen support for atomic operations on RV32I
This patch adds lowering for atomic fences and relies on AtomicExpandPass to
lower atomic loads/stores, atomic rmw, and cmpxchg to __atomic_* libcalls.
test/CodeGen/RISCV/atomic-* are modelled on the exhaustive
test/CodeGen/PPC/atomics-regression.ll, and will prove more useful once RV32A
codegen support is introduced.
Fence mappings are taken from table A.6 in the current draft of version 2.3 of
the RISC-V Instruction Set Manual, which incorporates the memory model changes
and definitions contributed by the RISC-V Memory Consistency Model task group.
Differential Revision: https://reviews.llvm.org/D47587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334590
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Simon Pilgrim [Wed, 13 Jun 2018 10:49:24 +0000 (10:49 +0000)]
[SLPVectorizer] getSameOpcode - remove useless cast [NFC]
There's no need to cast the base Value to an Instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334588
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Simon Pilgrim [Wed, 13 Jun 2018 10:14:27 +0000 (10:14 +0000)]
[SLPVectorizer] getSameOpcode - remove unusued alternate code [NFC]
We early-out for the case where we don't use alternate opcodes, so no need to check for it later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334587
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Clement Courbet [Wed, 13 Jun 2018 09:41:49 +0000 (09:41 +0000)]
[TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.
Summary:
For targets I'm not familiar with, I've automatically made the "default to 1 for each resource" behaviour explicit in the td files.
For more obvious cases, I've ventured a fix.
Some notes:
- Exynos is especially fishy.
- AArch64SchedThunderX2T99.td had some truncated entries. If I understand correctly, the person who wrote that interpreted the ResourceCycle as a range. I made the decision to use the upper/lower bound for consistency with the 'Latency' value. I'm sure there is a better choice.
- The change to X86ScheduleBtVer2.td is an NFC, it just makes values more explicit.
Also see PR37310.
Reviewers: RKSimon, craig.topper, javed.absar
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D46356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334586
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Hans Wennborg [Wed, 13 Jun 2018 09:11:10 +0000 (09:11 +0000)]
GettingStarted.rst: Fix 'If you you' typo (PR37787)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334584
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Hiroshi Inoue [Wed, 13 Jun 2018 08:54:13 +0000 (08:54 +0000)]
[PowerPC] fix trivial typos in comment, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334583
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Hans Wennborg [Wed, 13 Jun 2018 08:43:03 +0000 (08:43 +0000)]
Fix -DLLVM_ENABLE_THREADS=OFF build after r334537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334582
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Pavel Labath [Wed, 13 Jun 2018 08:29:19 +0000 (08:29 +0000)]
Fix "Optional" is ambiguous error on some bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334580
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Hiroshi Inoue [Wed, 13 Jun 2018 08:25:14 +0000 (08:25 +0000)]
[PowerPC] avoid verification failure due to PowerPC VSX Swap Removal pass
This patch fixes a failure in lnt tests with -verify-machineinstrs option.
When VSX Swap Removal pass swaps two register operands, it did not maintain kill flags associated with operands. This patch swaps flags as well as register number to avoid inconsistent kill flags information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334579
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Pavel Labath [Wed, 13 Jun 2018 08:14:27 +0000 (08:14 +0000)]
[DWARF/AccelTable] Remove getDIESectionOffset for DWARF v5 entries
Summary:
This method was not correct for entries in DWO files as it assumed it
could just add up the CU and DIE offsets to get the absolute DIE offset.
This is not correct for the DWO files, as here the CU offset will
reference the skeleton unit, whereas the DIE offset will be the offset
in the full unit in the DWO file.
Unfortunately, this means that we are not able to determine the absolute
DIE offset using the information in the .debug_names section alone,
which means we have to offload some of this work to the users of this
class.
To demonstrate how this can be done, I've added/fixed the ability to
lookup entries using accelerator tables in DWO files in llvm-dwarfdump.
To make this happen, I've needed to make two extra changes in other
classes:
- made the DWARFContext method to lookup a CU based on the section
offset public. I've needed this functionality to lookup a CU, and this
seems like a useful thing in general.
- made DWARFUnit::getDWOId call extractDIEsIfNeeded. Before this, the
DWOId was filled in only if the root DIE happened to be parsed
before we called the accessor. Since the lazy parsing is supposed to
happen under the hood, calling extractDIEsIfNeeded seems appropriate.
Reviewers: JDevlieghere, aprantl, dblaikie
Subscribers: mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D48009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334578
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Craig Topper [Wed, 13 Jun 2018 07:19:21 +0000 (07:19 +0000)]
[X86] Remove masking from avx512vbmi2 concat and shift by immediate intrinsics. Use select in IR instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334576
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Bill Wendling [Wed, 13 Jun 2018 05:53:59 +0000 (05:53 +0000)]
Set the code model when specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334571
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Tom Stellard [Wed, 13 Jun 2018 05:14:10 +0000 (05:14 +0000)]
utils/release: Add merge-git.sh
Summary:
This script allows you to use git to backport a commit to a stable
branch while generating the exact same commit message (ignoring
whitespace) that you would get from using the merge.sh script with svn.
Reviewers: hansw
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47760
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334568
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Max Kazantsev [Wed, 13 Jun 2018 02:25:32 +0000 (02:25 +0000)]
[SimplifyIndVars] Ignore dead users
IndVarSimplify sometimes makes transforms basing on users that are trivially dead. In particular,
if DCE wasn't run before it, there may be a dead `sext/zext` in loop that will trigger widening
transforms, however it makes no sense to do it.
This patch teaches IndVarsSimplify ignore the mist trivial cases of that.
Differential Revision: https://reviews.llvm.org/D47974
Reviewed By: sanjoy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334567
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Ahmed Bougacha [Wed, 13 Jun 2018 02:16:01 +0000 (02:16 +0000)]
Revert "Fix how LLVMOPTIONALCOMPONENTS is passed to llvm-build"
This reverts commit r334543.
My understanding is, that commit is intended to make the llvm-build
invocation have a correct "--enable-optional-components" value, but:
- it already has a value: it's quoted in the command line a few lines
below, and, if I hack llvm-build to print sys.argv, it does look correct:
-- llvm-build output: ['.../utils/llvm-build/llvm-build',
'--native-target', 'X86', '--enable-targets', 'X86;ARM;AArch64',
'--enable-optional-components', '',
'--write-library-table',
'.../build/tools/llvm-config/LibraryDependencies.inc',
'--write-cmake-fragment', '.../build/LLVMBuild.cmake']
- the " " string seems to evaluate to TRUE in CMake (*sigh*), so this
basically force-enables LLVM_USE_INTEL_JITEVENTS, regardless of the
value of the option.
On Darwin, JITEvents is not supported, so this bypasses that OS check
but is guaranteed to fail later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334566
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Craig Topper [Wed, 13 Jun 2018 00:04:08 +0000 (00:04 +0000)]
[X86] Mark all instructions that have masked store semantics with NotMemoryFoldable. Remove dependency on SchedRW from memory table autogenerator.
Previously we were whitelisting in instructions based on their SchedRW value. With the masked store instructions explicitly removed via NotMemoryFoldable, we don't seem to need this check anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334563
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Craig Topper [Wed, 13 Jun 2018 00:04:04 +0000 (00:04 +0000)]
[X86] Remove VPCOMPRESSB/W from the autogenerated load folding table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334562
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Stanislav Mekhanoshin [Tue, 12 Jun 2018 23:50:37 +0000 (23:50 +0000)]
[AMDGPU] DAG combine to produce V_PERM_B32
Differential Revision: https://reviews.llvm.org/D48099
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334559
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Sanjay Patel [Tue, 12 Jun 2018 22:50:37 +0000 (22:50 +0000)]
[AArch64] add tests for fadd with more than one use; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334556
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Raphael Isemann [Tue, 12 Jun 2018 22:40:20 +0000 (22:40 +0000)]
Added missing include to AMDHSAKernelDescriptor.h
We use size_t in this header, so we also need to include
cstddef to make it compile. Fixes the module builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334555
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Krzysztof Parzyszek [Tue, 12 Jun 2018 21:51:49 +0000 (21:51 +0000)]
[DAGCombiner] Recognize more patterns for ABS
Differential Revision: https://reviews.llvm.org/D47831
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334553
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Craig Topper [Tue, 12 Jun 2018 21:42:42 +0000 (21:42 +0000)]
[X86] add avx512 tests for potentially miscompiling cvttp2si/cvttp2ui (PR37751).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334551
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Reid Kleckner [Tue, 12 Jun 2018 21:15:27 +0000 (21:15 +0000)]
Remove malloc.h include from Intel JIT events code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334547
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Reid Kleckner [Tue, 12 Jun 2018 20:54:11 +0000 (20:54 +0000)]
Add null check to Intel JIT event listener
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334544
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Reid Kleckner [Tue, 12 Jun 2018 20:53:46 +0000 (20:53 +0000)]
Fix how LLVMOPTIONALCOMPONENTS is passed to llvm-build
Patch by Force.Charlie-I
If LLVM_USE_INTEL_JITEVENTS and LLVM_USE_OPROFILE not set,
"${LLVMOPTIONALCOMPONENTS}" is empty, but
**--enable-optional-components** need arg, Cause
**--write-library-table** to be skipped parsed.
Differential Revision: https://reviews.llvm.org/D47982
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334543
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Lang Hames [Tue, 12 Jun 2018 20:43:18 +0000 (20:43 +0000)]
[ORC] Add a fallback definition generator for VSOs.
If a VSO has a fallback definition generator attached it will be called during
lookup (and lookupFlags) for any unresolved symbols. The definition generator
can add new definitions to the VSO for any unresolved symbol. This allows VSOs
to generate new definitions on demand.
The immediate use case for this code is supporting VSOs that can import
definitions found via dlsym on demand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334538
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Lang Hames [Tue, 12 Jun 2018 20:43:17 +0000 (20:43 +0000)]
[ORC] Refactor blocking lookup logic into the blockingLookup function, and
implement existing blocking lookups (the lookup function) and
JITSymbolResolverAdapter on top of that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334537
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Lang Hames [Tue, 12 Jun 2018 20:43:17 +0000 (20:43 +0000)]
[RuntimeDyld] Add an assert to catch misbehaving symbol resolvers.
Resolvers are required to find results for all requested symbols or return an
error, but if a resolver fails to adhere to this contract (by returning results
for only a subset of the requested symbols) then this code will infinite loop.
This assertion catches resolvers that fail to adhere to the contract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334536
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Lang Hames [Tue, 12 Jun 2018 20:43:15 +0000 (20:43 +0000)]
[MCJIT] Call materializeAll on modules before compiling them in MCJIT.
This only affects modules with lazy GVMaterializers attached (usually modules
read off disk using the lazy bitcode reader). For such modules, materializing
before compiling prevents crashes due to missing function bodies /
initializers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334535
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Petr Hosek [Tue, 12 Jun 2018 20:00:50 +0000 (20:00 +0000)]
[AArch64] Support reserving x20 register
Register x20 is a callee-saved register which may be used for other
purposes in certain contexts, for example to hold special variables
within the kernel. This change adds support for reserving this register
both to frontend and backend to make this register usable for these
purposes.
Differential Revision: https://reviews.llvm.org/D46552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334531
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