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Tim Rowley [Fri, 12 Aug 2016 22:59:25 +0000 (16:59 -0600)]
swr: [rasterizer core] clamp scissor rects to current tile rect
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Fri, 12 Aug 2016 19:39:44 +0000 (13:39 -0600)]
swr: [rasterizer core] align stats structures
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Thu, 11 Aug 2016 20:52:18 +0000 (14:52 -0600)]
swr: [rasterizer core] use AVX2 permute to simplify PaTriList
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Thu, 11 Aug 2016 16:49:43 +0000 (10:49 -0600)]
swr: [rasterizer core] move some global variables to SWR_CONTEXT
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Wed, 10 Aug 2016 19:20:30 +0000 (13:20 -0600)]
swr: [rasterizer core] change scale on VP matrix element gathers
Was 1, which led to pulling denorms for non-zero indices.
Changed to sizeof(float).
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Wed, 10 Aug 2016 17:25:31 +0000 (11:25 -0600)]
swr: [rasterizer] implementing native AVX-512 simd16 intrinsics
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Jason Ekstrand [Mon, 8 Aug 2016 23:53:00 +0000 (16:53 -0700)]
i965/blorp: Use nir_alu_type for the texture data type
This lets us remove the brw_reg.h include
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 8 Aug 2016 22:33:43 +0000 (15:33 -0700)]
i965: brw_blorp_blit.cpp -> blorp_blit.c
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 8 Aug 2016 22:30:57 +0000 (15:30 -0700)]
i965: brw_blorp_clear.cpp -> blorp_clear.c
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 8 Aug 2016 22:25:17 +0000 (15:25 -0700)]
i965: Split brw_blorp.c/h into multiple files
This mega-commit pulls most of the i965-specific bits of blorp into the
brw_blorp.c/h files which now contain nothing but i965 wrappers around
"core blorp" calls. The "core blorp" api is moved into blorp.h and the
internal blorp data structures are moved into blorp_priv.h. The new file
blorp.c is created to house "core blorp" internals which are pulled from
the old brw_blorp.c
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 26 Jul 2016 00:48:05 +0000 (17:48 -0700)]
i965/blorp: Factor the guts of blorp_hiz_exec into a helper
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 25 Jul 2016 21:03:49 +0000 (14:03 -0700)]
i965/blorp: Break the guts of do_single_blorp_clear into two helpers
The helpers are completely miptree-unaware and each fairly cleanly do a
single thing. This does come at the downside of not doing proper debug
reporting on whether or not we're doing replicated clears.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 25 Jul 2016 21:03:42 +0000 (14:03 -0700)]
i965/meta_util: Convert get_fast_clear_rect to take an isl_surf
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 25 Jul 2016 21:09:14 +0000 (14:09 -0700)]
i965/blorp/clear: Move isl_surf setup higher in the function
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 25 Jul 2016 21:44:50 +0000 (14:44 -0700)]
i965/blorp: Refactor fast-clear logic a bit
This pulls the mcs allocation into the if statement where we initially
determine that we are doing a fast clear and moves the programming of
wm_inputs and figuring out the fast clear rect into it's own if statement.
The next commit will put code inbetween the two.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 25 Jul 2016 21:05:48 +0000 (14:05 -0700)]
i965/blorp/clear: Stop stomping the destination format
The blorp_surface_info_init call above should set the format for us and
stomping it later does nothing whatsoever.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sun, 24 Jul 2016 08:13:49 +0000 (01:13 -0700)]
i965/meta_util: Only modify the input parameters in get_fast_clear_rect
We had another inline copy of brw_meta_get_buffer_rect embedded in
get_fast_clear_rect for no good reason. This lets us get rid of the
gl_frameuffer parameter to get_fast_clear_rect.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sun, 24 Jul 2016 08:08:14 +0000 (01:08 -0700)]
i965/blorp: Stop calling brw_meta_get_buffer_rect
We already have an inlined version of the function slightly higher up in
do_single_blorp_clear and all calling it does is stomp the values with the
same thing. We might as well just get rid of it.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sat, 23 Jul 2016 19:46:10 +0000 (12:46 -0700)]
i965/blorp: Pull the guts of resolve_color into a miptree-agnostic helper
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sat, 23 Jul 2016 19:13:07 +0000 (12:13 -0700)]
i965/meta_util: Convert get_resolve_rect to use ISL
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 20 Jul 2016 02:19:12 +0000 (19:19 -0700)]
i965/blorp: Make the guts of brw_blorp_blit_miptrees miptree-unaware
Now that we have the brw_blorp_surf struct, we can start to make bits of
blorp completely miptree-unaware. To start things off, we split the guts
of brw_blorp_blit_miptrees into a brw_blorp_blit function which knows
nothing about miptrees.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 20 Jul 2016 02:04:03 +0000 (19:04 -0700)]
i965/blorp: Add a new brw_blorp_surf intermediate struct
At the moment, this seems to make all of the interfaces messier rather than
clener. However, it does provide a representation of a surface that
simultaneously contains everything and is completely unaware of miptrees.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 20 Jul 2016 02:01:38 +0000 (19:01 -0700)]
i965/blorp: Use the isl_surf for more params setup
The isl_surf munging doesn't happen until fairly late in the blorp_blit
function. We can use the isl_surf for the vast majority if not all of our
params setup.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 20 Jul 2016 02:59:16 +0000 (19:59 -0700)]
i965/blorp: Do gen6 stencil offsets up-front
This keeps all of the nastyness of gen6 stencil on the i965 side of the API
line and lets us delete that nasty hand-rolled ISL-based offset path that
we were using for ALL_SLICES_AT_EACH_LOD.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 22 Jul 2016 21:41:43 +0000 (14:41 -0700)]
i965/blorp: Set up HiZ surfaces up-front
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 1 Jul 2016 23:01:56 +0000 (16:01 -0700)]
i964/blorp: Set up most aux surfaces up-front
This commit also adds support for an offset for aux surfaces. In GL, this
only gets used for HiZ on SNB at the moment. However, in Vulkan, all aux
surfaces are at a non-zero offset and that is likely to happen in GL
eventually.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 22 Jul 2016 21:24:06 +0000 (14:24 -0700)]
i965/blorp: Stop using the miptree in state setup for tex/rt surfaces
This commit movies us from a miptree model to a surf+bo+offset model. In
the GL driver, miptrees are almost always at the start of the bo so the
offset is zero but we don't want to always make that assumption. In the
sort term, gen6 stencil and HiZ will be at an offset but, in the long term,
any Vulkan surface is liable to be at a non-zero offset.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 1 Jul 2016 21:05:57 +0000 (14:05 -0700)]
i965/blorp/blit: Move format work-arounds before surface_info_init
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 26 Jul 2016 16:30:15 +0000 (09:30 -0700)]
i965/miptree: Add real support for HiZ
The previous HiZ support was bogus because all of get_aux_isl_surf looked
at mt->mcs_mt directly. For HiZ buffers, you need to look at either
mt->hiz_buf or mt->hiz_buf->mt.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 5 Aug 2016 22:06:36 +0000 (15:06 -0700)]
isl/state: Only set clear color if aux is used
Otherwise, the clear color will get ignored. This prevents assertion
errors if clear color is set to something invalid and aux is not used.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 1 Jul 2016 23:02:29 +0000 (16:02 -0700)]
i965/miptree: Use the isl helpers for creating aux surfaces
In order for the calculations of things such as fast clear rectangles to
work, we need more details of the auxiliary surface to be correct. In
particular, we need to be able to trust the width and height fields.
(These are not necessarily what you want coming out of the miptree.) The
only values state setup really cares about are the row and array pitch and
those we can safely stomp from the miptree.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sun, 24 Jul 2016 07:52:34 +0000 (00:52 -0700)]
isl: Add helpers for creating different types of aux surfaces
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 26 Jul 2016 16:33:23 +0000 (09:33 -0700)]
i965/miptree: Use mcs_mt->qpitch for aux surfaces
At one point, we were doing this correctly. It must have gotten lost in
one of the many rebases.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 19 Jul 2016 23:25:50 +0000 (16:25 -0700)]
i965/miptree: Allow get_aux_isl_surf when there is no aux surface
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 1 Jul 2016 23:02:45 +0000 (16:02 -0700)]
i965/miptree: Support depth in get_isl_clear_color
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 21:38:54 +0000 (14:38 -0700)]
isl/state: Add an assertion for IVB multisample array textures
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 23:14:24 +0000 (16:14 -0700)]
isl: Add a #define for DEV_IS_BAYTRAIL
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 01:34:02 +0000 (18:34 -0700)]
i965/blorp: Remove unused fields from blorp_surface_info
The only reason why we need layer or level is that we need the z-offset for
3-D surfaces. Let's just have the one field for that.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 01:33:05 +0000 (18:33 -0700)]
i965/blorp: Simplify depth buffer state setup a bit
The data comes in via ISL in a format that's almost directly usable by the
hardware so we can avoid some of the conversion headache.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 00:13:39 +0000 (17:13 -0700)]
i965/blorp: Use the generic surface state path for gen8 textures
Now that the generic blorp path uses base level/layer, there's no need to
make gen8 special.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 27 Jun 2016 15:43:27 +0000 (08:43 -0700)]
isl: Add asserts for gen8+ X/YOffset rules
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 27 Jun 2016 18:54:14 +0000 (11:54 -0700)]
i965/blorp: Only do offset hacks for fake W-tiling and IMS
Since the dawn of time, blorp has used offsets directly to get at different
mip levels and array slices of surfaces. This isn't really necessary since
we can just use the base level/layer provided in the surface state. While
it may have simplified blorp's original design, we haven't been using the
blorp path for surface state on gen8 thanks to render compression and
there's really no good need for it most of the time. This commit restricts
such surface munging to the cases of fake W-tiling and fake interleaved
multisampling.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 21:46:07 +0000 (14:46 -0700)]
i965/blorp: Add a z_offset field to blorp_surface_info
The layer field is in terms of physical layers which isn't quite what the
sampler will want for 2-D MS array textures.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 21:10:49 +0000 (14:10 -0700)]
i965/blorp: Pass the Z component into all texture operations
Multisample array surfaces on IVB don't support the minimum array element
surface attribute so it needs to come through the sampler message. We may
as well just pass it through everything.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 02:30:32 +0000 (19:30 -0700)]
i965/blorp: Rework hiz rect alignment calculations
At the moment, the minify operation does nothing because
params.depth.view.base_level is always zero. However, as soon as we start
using actual base miplevels and array slices, we are going to need the
minification. Also, we only need to align the surface dimensions in the
case where we are operating on miplevel 0. Previously, it didn't matter
because it aligned on miplevel 0 and, for all other miplevels, the miptree
code guaranteed that the level was already aligned.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 00:30:35 +0000 (17:30 -0700)]
i965/blorp: Map 1-D render targets with DIM_LAYOUT_GEN4_2D as 2D on gen9
The sampling hardware can handle them ok. It just looks at the tiling to
determine whether it's the new gen9 1-D layout or the old one. The render
hardware isn't so smart.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 27 Jun 2016 22:30:15 +0000 (15:30 -0700)]
i965/miptree: Fill out the isl_surf::usage field
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 1 Jul 2016 21:25:59 +0000 (14:25 -0700)]
isl: Take the slice0_extent shortcut for interleaved MSAA
The shortcut works just fine for MSAA and the comment even says so.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Fri, 1 Jul 2016 21:21:44 +0000 (14:21 -0700)]
isl: Remove duplicate px->sa conversions
In all three cases, we start with width and height taken from
isl_surf::phys_slice0_extent_sa which is already in samples. There is no
need to do the conversion and doing so gives us an incorrect value.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Mon, 27 Jun 2016 16:05:46 +0000 (09:05 -0700)]
i965/blorp: Use the isl_view from the blorp_surface_info
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 17 Aug 2016 08:06:36 +0000 (01:06 -0700)]
i965/blorp: Get rid of brw_blorp_surface_info::width/height
Instead, we manually mutate the surface size as needed.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 03:48:20 +0000 (20:48 -0700)]
i965/blorp: Move surface offset calculations into a helper
The helper does a full transformation on the surface to turn it into a new
2-D single-layer single-level surface representing the original layer and
level in memory.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 03:57:41 +0000 (20:57 -0700)]
i965/blorp: Use ISL to compute image offsets
For the moment, we still call the old miptree function; we just assert that
the two are equal.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 22:00:31 +0000 (15:00 -0700)]
isl: Add functions for computing surface offsets in samples
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 04:50:22 +0000 (21:50 -0700)]
isl: Fix get_image_offset_sa_gen4_2d for multisample surfaces
The function takes a logical array layer but was assuming it was a physical
array layer. While we'er here, we also make it not assert-fail on gen9 3-D
surfaces.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 03:11:46 +0000 (20:11 -0700)]
i965/blorp: Add an isl_view to blorp_surface_info
Eventually, this will be the actual view that gets passed into isl to
create the surface state. For now, we just use it for the format and the
swizzle.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 01:40:08 +0000 (18:40 -0700)]
i965/blorp: Move intratile offset calculations out of surface state setup
Previously we multiplied full x/y offsets, resolved tile aligned buffer
offset and intra tile offset based on that. Now we let ISL to take into
account the msaa setting and we only multiply the resolved intra tile
offsets.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 24 Jun 2016 00:06:37 +0000 (17:06 -0700)]
i965/blorp: Refactor interleaved multisample destination handling
We put all of the code for fake IMS together. This requires moving a bit
of the program key setup code further down so that it gets the right values
out of the final surface.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Thu, 23 Jun 2016 23:27:17 +0000 (16:27 -0700)]
i965/blorp: Get rid of brw_blorp_surface_info::array_layout
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Thu, 23 Jun 2016 22:50:18 +0000 (15:50 -0700)]
i965/blorp: Use isl_msaa_layout instead of intel_msaa_layout
We also remove brw_blorp_surface_info::msaa_layout.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Thu, 23 Jun 2016 22:17:15 +0000 (15:17 -0700)]
i965/blorp: Use the ISL aux_layout for deciding whether to do an MCS fetch
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Thu, 23 Jun 2016 18:00:59 +0000 (11:00 -0700)]
i965/blorp: Get rid of brw_blorp_surface_info::num_samples
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Thu, 23 Jun 2016 18:35:50 +0000 (11:35 -0700)]
i965/blorp: Make sample count asserts a bit more lazy
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 22 Jun 2016 23:46:20 +0000 (16:46 -0700)]
i965/blorp: Get rid of brw_blorp_surface_info::map_stencil_as_y_tiled
Now that we're carrying around the isl_surf, we can just modify it
directly instead of passing an extra bit around.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 22 Jun 2016 23:41:58 +0000 (16:41 -0700)]
i965/blorp: Remove compute_tile_offsets
We have a handy little function is ISL that does exactly the same thing.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 22 Jun 2016 22:33:44 +0000 (15:33 -0700)]
i965/blorp: Create the isl_surf up-front
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Thu, 23 Jun 2016 22:32:57 +0000 (15:32 -0700)]
i965/blorp/clear: Initialize surface info after allocating an MCS
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Tue, 28 Jun 2016 21:20:15 +0000 (14:20 -0700)]
isl/state: Use a valid alignment for 1-D textures
The alignment we use doesn't matter (see the comment) but it should at
least be an alignment we can represent with the enums.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 22 Jun 2016 23:13:42 +0000 (16:13 -0700)]
i965/miptree: Remove the stencil_as_y_tiled parameter from get_tile_masks
It's only used to stomp the tiling to Y and it's only used by blorp so
there's no reason why blorp can't do it itself.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Wed, 22 Jun 2016 23:37:54 +0000 (16:37 -0700)]
isl: Fix the parameter names for get_intratile_offset
It's been in elements for a while but, for whatever reason, the parameter
names in the header file never got updated.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Brian Paul [Wed, 17 Aug 2016 16:41:30 +0000 (10:41 -0600)]
util: try to use SSE instructions with MSVC and 32-bit gcc
The lrint() and lrintf() functions are pretty slow and make some
texture transfers very inefficient. This patch makes a better effort
at using those intrisics for 32-bit gcc and MSVC.
Note, this patch doesn't address the use of SSE4.1 with MSVC.
v2: get rid of the ROUND_WITH_SSE symbol, per Matt.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Brian Paul [Wed, 17 Aug 2016 14:31:20 +0000 (08:31 -0600)]
svga: fix src/dst typo in can_blit_via_copy_region_vgpu10()
The function was always returning false because of this typo.
Retested with piglit. There's some sRGB-related blit failures, but
that seems unrelated.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Brian Paul [Wed, 17 Aug 2016 14:20:33 +0000 (08:20 -0600)]
svga: initialize a variable to silence a gcc warning
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Ian Romanick [Wed, 15 Apr 2015 23:43:20 +0000 (16:43 -0700)]
glsl: Pull enum ir_expression_operation out to its own file
No change except to the copyright symbol. The next patch will generate
this file with Python, and Unicode + Python = pure rage.
v2: Massive rebase... I guess a lot can change in a year.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Thu, 14 Jul 2016 01:02:10 +0000 (18:02 -0700)]
glsl: Make the generated sources build rules more like NIR
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francesco Ansanelli [Tue, 16 Aug 2016 12:38:46 +0000 (14:38 +0200)]
mesa/st: use llabs instead of abs for long args (v2)
v2: long has 32bit on Windows (Marek)
Signed-off-by: Francesco Ansanelli <francians@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Fri, 12 Aug 2016 11:00:58 +0000 (13:00 +0200)]
radeonsi: fix up buffer descriptor upper-bound checking
st/mesa does this too, so we're safe.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 12 Aug 2016 00:33:41 +0000 (02:33 +0200)]
gallium: change pipe_image_view::first_element/last_element -> offset/size
This is required by OpenGL. Our hardware supports this.
Example: Bind RGBA32F with offset = 4 bytes.
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 12 Aug 2016 00:33:41 +0000 (02:33 +0200)]
gallium: change pipe_sampler_view::first_element/last_element -> offset/size
This is required by OpenGL. Our hardware supports this.
Example: Bind RGBA32F with offset = 4 bytes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97305
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Aug 2016 20:11:34 +0000 (22:11 +0200)]
gallium/radeon: assign the highest priority to scratch; make rings second
just FYI, the kernel receives priority/4
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Aug 2016 20:08:51 +0000 (22:08 +0200)]
gallium/winsys: re-number winsys priority flags
free 60..63, move CP_DMA up
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Aug 2016 20:00:49 +0000 (22:00 +0200)]
gallium/radeon: mark shader rings as highest-priority buffers
and rename the enum
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Aug 2016 19:50:55 +0000 (21:50 +0200)]
gallium/radeon: set SHADER_RW_BUFFER priority for streamout buffers
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Aug 2016 15:56:44 +0000 (17:56 +0200)]
radeonsi: use current context for DCC feedback-loop decompress, fixes Elemental
This is just a workaround. The problem is described in the code.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96541
v2: say that it's only between the current context and aux_context
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Marek Olšák [Wed, 10 Aug 2016 10:43:45 +0000 (12:43 +0200)]
radeonsi: simplify CB_TARGET_MASK logic
we can now rely on CB_COLORn_INFO to disable empty slots.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 10 Aug 2016 10:21:53 +0000 (12:21 +0200)]
radeonsi: don't set CB_COLOR1_INFO for dual src blending
Vulkan doesn't do this. The reason may be that CB_COLOR1_INFO.SOURCE_FORMAT
from NI was moved to SPI_SHADER_COL_FORMAT for SI.
I asked CB guys about this 2 days ago and they still haven't replied.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 10 Aug 2016 10:19:49 +0000 (12:19 +0200)]
radeonsi: eliminate PS OUT[1] if dual src blending is off and CB1 is not bound
All VP DX9 ports benefit from this.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 9 Aug 2016 21:37:04 +0000 (23:37 +0200)]
gallium/radeon: use unflushed fences for PIPE_QUERY_GPU_FINISHED
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Tue, 9 Aug 2016 10:26:37 +0000 (12:26 +0200)]
gallium/radeon: use lp_build_alloca_undef
Avoid building all those store 0 / store undef instruction pairs that
end up getting removed anyway.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 9 Aug 2016 10:25:43 +0000 (12:25 +0200)]
gallivm: add lp_build_alloca_undef
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 9 Aug 2016 10:23:41 +0000 (12:23 +0200)]
gallivm: add create_builder_at_entry helper function
Reduces code duplication.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 21:52:54 +0000 (23:52 +0200)]
gallium/radeon: protect against out of bounds temporary array accesses
They can lead to VM faults and worse, which goes against the GL robustness
promises.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 21:52:06 +0000 (23:52 +0200)]
gallium/radeon: add radeon_llvm_bound_index for bounds checking
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 20:31:02 +0000 (22:31 +0200)]
gallium/radeon: reduce alloca of temporaries based on usagemask
v2: take actual writemasks into account
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 10 Aug 2016 16:50:24 +0000 (18:50 +0200)]
gallium/radeon: use tgsi_scan_arrays for temp arrays
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 10 Aug 2016 16:41:21 +0000 (18:41 +0200)]
gallium/radeon: allocate temps array info in radeon_llvm_context_init
Also, prepare for using tgsi_array_info.
This also opens the door for properly handling allocation failures, but I'm
leaving that for a separate change.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 21:20:45 +0000 (23:20 +0200)]
gallium/radeon: always do the full store in store_value_to_array
Doing the write-back of the temporary vector in radeon_llvm_emit_store makes
no sense.
This also allows us to get rid of get_alloca_for_array.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 21:13:44 +0000 (23:13 +0200)]
gallium/radeon: extract common getelementptr logic into get_pointer_into_array
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 20:50:05 +0000 (22:50 +0200)]
gallium/radeon: pass indirect register info into get_alloca_for_array
To have the same signature as get_array_range.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 8 Aug 2016 20:43:09 +0000 (22:43 +0200)]
gallium/radeon: extract common lookup code into get_temp_array function
Reviewed-by: Marek Olšák <marek.olsak@amd.com>