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Florian Hahn [Wed, 1 Nov 2017 09:48:12 +0000 (09:48 +0000)]
[CodeExtractor] Fix iterator invalidation in findOrCreateBlockForHoisting.
Summary:
By replacing branches to CommonExitBlock, we remove the node from
CommonExitBlock's predecessors, invalidating the iterator. The problem
is exposed when the common exit block has multiple predecessors and
needs to sink lifetime info. The modification in the test case trigger
the issue.
Reviewers: davidxl, davide, wmi
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39112
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317084
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Serguei Katkov [Wed, 1 Nov 2017 07:56:55 +0000 (07:56 +0000)]
Fix APFloat mod sign
fmod specification requires the sign of the remainder is
the same as numerator in case remainder is zero.
Reviewers: gottesmm, scanon, arsenm, davide, craig.topper
Reviewed By: scanon
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D39225
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317081
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Craig Topper [Wed, 1 Nov 2017 07:11:32 +0000 (07:11 +0000)]
[X86] Add more type qualifiers to INSERT_SUBREG operations in rotate patterns so they don't get created with a v64i8 type.
Not sure why tablegen didn't error on this.
Fixes PR35158.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317079
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NAKAMURA Takumi [Wed, 1 Nov 2017 05:14:35 +0000 (05:14 +0000)]
Reformat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317078
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NAKAMURA Takumi [Wed, 1 Nov 2017 05:14:31 +0000 (05:14 +0000)]
Revert rL317019, "[ADT] Split optional to only include copy mechanics and dtor for non-trivial types."
Seems g++-4.8 (eg. Ubuntu 14.04) doesn't like this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317077
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Craig Topper [Wed, 1 Nov 2017 03:30:52 +0000 (03:30 +0000)]
[DAGCombiner] Fix typos in comments. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317072
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Mitch Phillips [Wed, 1 Nov 2017 00:49:45 +0000 (00:49 +0000)]
Add test dependency on llvm-cfi-verify to fix up the build breakages on sanitizers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317060
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Craig Topper [Wed, 1 Nov 2017 00:47:45 +0000 (00:47 +0000)]
[X86] Add AVX512 support to X86FastISel::fastMaterializeFloatZero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317059
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Daniel Sanders [Wed, 1 Nov 2017 00:29:47 +0000 (00:29 +0000)]
[globalisel][tablegen] Stop hard-coding the emitted instruction ID to 0. NFC
The next commit will add support for multi-instruction emission so we need to
start allocating instruction ID's instead of hard-coding them to 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317057
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Jake Ehrlich [Wed, 1 Nov 2017 00:18:51 +0000 (00:18 +0000)]
Add system-linux to allow tests run with llvm-lit to restrict themselves to linux
I need a test that only runs in a reasonable amount of time on systems
that have sparse files. The broadest class of systems that support
sparse files are linux systems. So restricting my test to linux systems
should suffice. This change adds the system-linux feature to llvm-lit so
that it can be required.
Differential Revision: https://reviews.llvm.org/D39482
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317055
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Benjamin Kramer [Tue, 31 Oct 2017 23:21:30 +0000 (23:21 +0000)]
[AMDGPU] Clean up symbols in the global namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317051
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Mitch Phillips [Tue, 31 Oct 2017 23:20:05 +0000 (23:20 +0000)]
Parse DWARF information to reduce false positives.
Summary: Help differentiate code and data by parsing DWARF information. This will reduce false positive rates where data is placed in executable sections and is mistakenly parsed as code, resulting in an inflation in the number of indirect CF instructions (and hence an inflation of the number of unprotected).
Also prints the DWARF line data around the region of each indirect CF instruction.
Reviewers: pcc
Subscribers: probinson, llvm-commits, vlad.tsyrklevich, mgorny, aprantl, kcc
Differential Revision: https://reviews.llvm.org/D38654
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317050
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Daniel Sanders [Tue, 31 Oct 2017 23:03:18 +0000 (23:03 +0000)]
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
Multi-instruction emission needs to ensure the the instructions are generated
a depth-first fashion. For example:
(ADDWrr (SUBWrr a, b), c)
needs to emit the SUBWrr before the ADDWrr. However, our walk over
TreePatternNode's is highly context sensitive which makes it difficult to append
BuildMIActions in the order we want. To fix this, we now keep track of the
insertion point as we add actions. This will allow multi-insn emission to insert
BuildMI's in the correct place.
The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the
const_iterator forms of insert() and emplace() that were added in C++11. As a
result I've switched the const_iterators to iterators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317049
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Philip Reames [Tue, 31 Oct 2017 22:56:16 +0000 (22:56 +0000)]
[SimplifyIndVar] Inline makIVComparisonInvariant to eleminate code duplication [NFC]
This formulation might be slightly slower since I eagerly compute the cheap replacements. If anyone sees this having a compile time impact, let me know and I'll use lazy population instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317048
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Peter Collingbourne [Tue, 31 Oct 2017 22:49:23 +0000 (22:49 +0000)]
Object: Move some code from ELF.h into ELF.cpp.
Differential Revision: https://reviews.llvm.org/D39271
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317046
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Peter Collingbourne [Tue, 31 Oct 2017 22:49:09 +0000 (22:49 +0000)]
Inline compareAddr function into its only caller. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317045
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Daniel Sanders [Tue, 31 Oct 2017 21:54:52 +0000 (21:54 +0000)]
Revert r317040: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
The same bots fail but I believe I know what the issue is now. These bots are
missing the const_iterator versions of insert/emplace/etc. that were introduced
in C++11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317042
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Reid Kleckner [Tue, 31 Oct 2017 21:52:15 +0000 (21:52 +0000)]
[codeview] Merge file checksum entries for DIFiles with the same absolute path
Change the map key from DIFile* to the absolute path string. Computing
the absolute path isn't expensive because we already have a map that
caches the full path keyed on DIFile*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317041
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Daniel Sanders [Tue, 31 Oct 2017 21:34:53 +0000 (21:34 +0000)]
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
Multi-instruction emission needs to ensure the the instructions are generated
a depth-first fashion. For example:
(ADDWrr (SUBWrr a, b), c)
needs to emit the SUBWrr before the ADDWrr. However, our walk over
TreePatternNode's is highly context sensitive which makes it difficult to append
BuildMIActions in the order we want. To fix this, we now keep track of the
insertion point as we add actions. This will allow multi-insn emission to insert
BuildMI's in the correct place.
The previous commit failed on the Ubuntu bots using GCC 4.8. These bots didn't
like a call to emplace(). I've replaced it with insert() to see if it's a quirk
of the C++11 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317040
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Marek Olsak [Tue, 31 Oct 2017 21:06:42 +0000 (21:06 +0000)]
AMDGPU: Select s_buffer_load_dword with a non-constant SGPR offset
Summary:
Apps that benefit:
- alien isolation
- bioshock infinite
- civilization: beyond earth
- company of heroes 2
- dirt showdown
- dota 2
- F1 2015
- grid autosport
- hitman
- legend of grimrock
- serious sam 3: bfe
- shadow warrior
- talos principle
- total war: warhammer
- UE4 demos: effects cave, elemental, sun temple
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D38914
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317038
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Adrian Prantl [Tue, 31 Oct 2017 21:03:22 +0000 (21:03 +0000)]
loop-rotate: simplify code by using llvm::findDbgValues(). (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317037
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Daniel Sanders [Tue, 31 Oct 2017 20:29:28 +0000 (20:29 +0000)]
Revert r317029: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
The Linux bots don't seem to like this usage of emplace(). Reverting while I look into it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317033
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Benjamin Kramer [Tue, 31 Oct 2017 19:55:08 +0000 (19:55 +0000)]
Revert "[DWARF] Now that Optional is standard layout, put it into an union instead of splatting it."
GCC doesn't like it. This reverts commit r317028.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317030
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Daniel Sanders [Tue, 31 Oct 2017 19:54:05 +0000 (19:54 +0000)]
[globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
Multi-instruction emission needs to ensure the the instructions are generated
a depth-first fashion. For example:
(ADDWrr (SUBWrr a, b), c)
needs to emit the SUBWrr before the ADDWrr. However, our walk over
TreePatternNode's is highly context sensitive which makes it difficult to append
BuildMIActions in the order we want. To fix this, we now keep track of the
insertion point as we add actions. This will allow multi-insn emission to insert
BuildMI's in the correct place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317029
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Benjamin Kramer [Tue, 31 Oct 2017 19:40:03 +0000 (19:40 +0000)]
[DWARF] Now that Optional is standard layout, put it into an union instead of splatting it.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317028
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Benjamin Kramer [Tue, 31 Oct 2017 19:22:55 +0000 (19:22 +0000)]
[coro] Make Spill a proper struct instead of deriving from pair.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317027
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Daniel Sanders [Tue, 31 Oct 2017 19:09:29 +0000 (19:09 +0000)]
[globalisel][tablegen] Factor out implicit def/use renderers from createAndImportInstructionRenderer(). NFC
Multi-instruction emission will require that we have separate handling for
the defs between the implicitly created temporaries and the rule outputs.
The former require new temporary vregs while the latter should copy existing
operands. Factor out the implicit def/use renderers to minimize the code
duplication when we implement that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317025
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Craig Topper [Tue, 31 Oct 2017 19:03:51 +0000 (19:03 +0000)]
[SimplifyCFG] Use a more generic name for the selects created by SpeculativelyExecuteBB to prevent long names from being created
Currently the selects are created with the names of their inputs concatenated together. It's possible to get cases that chain these selects together resulting in long names due to multiple levels of concatenation. Our internal branch of llvm managed to generate names over 100000 characters in length on a particular test due to an extreme compounding of the names.
This patch changes the name to a generic name that is not dependent on its inputs.
Differential Revision: https://reviews.llvm.org/D39440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317024
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Craig Topper [Tue, 31 Oct 2017 19:03:49 +0000 (19:03 +0000)]
[SimplifyCFG] Regenerate some test cases using update_test_checks.py to prepare for an upcoming commit. NFC
A future commit will change how some of the value names in the IR are generated which causes these tests to break in their current form. The script generates checks with regular expressions so it should be immune.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317023
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Daniel Sanders [Tue, 31 Oct 2017 18:50:24 +0000 (18:50 +0000)]
[globalisel][tablegen] Add infrastructure to potentially allow BuildMIAction to choose a mutatable instruction. NFC
Prepare for multiple instruction emission by allowing BuildMIAction to
search for a suitable matcher that will support mutation.
This patch deliberately neglects to add matchers aside from the root to
preserve NFC. That said, it should be noted that until we support mutations
other than just the opcode the chances of finding a non-root instruction
for which canMutate() is true, is essentially zero. Furthermore in the
presence of multi-instruction emission the chances of finding any
instruction for which canMutate() is true is also zero. Nevertheless, we
can't continue to require that all BuildMIAction's consider the root of the match
to be recyclable due to the risk of recycling it twice in the same rule.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317022
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Simon Pilgrim [Tue, 31 Oct 2017 18:43:24 +0000 (18:43 +0000)]
[X86][AVX512] Regenerate tests to remove retl/retq regex
These are only testing 64-bit targets so we don't need the regex
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317021
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Simon Pilgrim [Tue, 31 Oct 2017 18:41:48 +0000 (18:41 +0000)]
[X86][AVX512] Split AVX512F and AVX512BW bool-vector bitcast tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317020
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Benjamin Kramer [Tue, 31 Oct 2017 18:35:54 +0000 (18:35 +0000)]
[ADT] Split optional to only include copy mechanics and dtor for non-trivial types.
This makes uses of Optional more transparent to the compiler (and
clang-tidy) and generates slightly smaller code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317019
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Wolfgang Pieb [Tue, 31 Oct 2017 18:25:28 +0000 (18:25 +0000)]
[Metadata][NFC] Make MDNode::resolve() public in preparation for the fix to PR33930.
Reviewers: aprantl
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317018
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Daniel Sanders [Tue, 31 Oct 2017 18:07:03 +0000 (18:07 +0000)]
[globalisel][tablegen] Allow any comment in DebugCommentAction. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317017
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Philip Reames [Tue, 31 Oct 2017 18:04:57 +0000 (18:04 +0000)]
[IndVarSimplify] Extract wrapper around SE-.isLoopInvariantPredicate [NFC]
This an intermediate state, the next patch will re-inline the markLoopInvariantPredicate function to reduce code duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317016
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Rui Ueyama [Tue, 31 Oct 2017 17:37:20 +0000 (17:37 +0000)]
[Support] Make the default chunk size of raw_fd_ostream to 1 GiB.
Previously, we call write(2) for each 32767 byte chunk. That is not
efficient because Linux can handle much larger write requests.
This patch changes the chunk size on Linux to 1 GiB.
This patch also changes the default chunks size to SSIZE_MAX. I think
that doesn't in practice change this function's behavior on any operating
system because SSIZE_MAX on 64-bit machine is unrealistically large,
and writing 2 GiB (SSIZE_MAX on 32-bit) on a 32-bit machine by a single
call of write(2) is also unrealistic, as the userspace is usually
limited to 2 GiB. That said, it is in general a good thing to do because
a write larger than SSIZE_MAX is implementation-defined in POSIX.
Differential Revision: https://reviews.llvm.org/D39444
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317015
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Philip Reames [Tue, 31 Oct 2017 17:06:32 +0000 (17:06 +0000)]
[IndVarSimplify] Simplify code using a dictionary
Possibly very slightly slower, but this code is not performance critical and the readability benefit alone is huge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317012
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Reid Kleckner [Tue, 31 Oct 2017 16:47:38 +0000 (16:47 +0000)]
[X86][AsmParser] Treat '%' as the modulo operator under Intel syntax
It can't be a register prefix, anyway. This is consistent with the masm
docs on MSDN: https://msdn.microsoft.com/en-us/library/t4ax90d2.aspx
This is a straight-forward extension of our support for "MOD"
implemented in https://reviews.llvm.org/D33876 / r306425
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317011
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Nico Weber [Tue, 31 Oct 2017 16:39:47 +0000 (16:39 +0000)]
LTOModule::isBitcodeFile() shouldn't assert when returning false.
Fixes a bunch of assert-on-invalid-bitcode regressions after 315483.
Expected<> calls assertIsChecked() in its dtor, and operator bool() only calls
setChecked() if there's no error. So for functions that don't return an error
itself, the Expected<> version needs explicit code to disarm the error that the
ErrorOr<> code didn't need.
https://reviews.llvm.org/D39437
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317010
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Reid Kleckner [Tue, 31 Oct 2017 16:16:08 +0000 (16:16 +0000)]
[asan] Upgrade private linkage globals to internal linkage on COFF
COFF comdats require symbol table entries, which means the comdat leader
cannot have private linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317009
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Simon Pilgrim [Tue, 31 Oct 2017 16:06:21 +0000 (16:06 +0000)]
[X86][SSE] Add VSRLI/VSRAI/VSLLI demanded elts support to computeKnownBits/ComputeNumSignBits
Mainly a perf improvements as most combines will have occurred before we lower to these instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317005
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Benjamin Kramer [Tue, 31 Oct 2017 14:58:22 +0000 (14:58 +0000)]
[LoopVectorize] Replace manual VPlan memory management with unique_ptr.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317003
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Jonas Devlieghere [Tue, 31 Oct 2017 14:19:02 +0000 (14:19 +0000)]
[test] Fix dsymutil/cmdline.test
This fixes dsymutil/cmdline.test on platforms where the dsymutil binary
has an extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317001
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Florian Hahn [Tue, 31 Oct 2017 14:06:31 +0000 (14:06 +0000)]
[Reassociate] Remove FIXME from looptest.ll (NFC)
Summary: The loop invariant add (i+j) is reassoicated, I think the FIXME can be removed, because this is what the test case tries to check (AFAIK). I also changed the test to use FileCheck.
Reviewers: mcrosier, davide
Reviewed By: mcrosier, davide
Subscribers: davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D39424
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317000
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Jonas Devlieghere [Tue, 31 Oct 2017 13:54:15 +0000 (13:54 +0000)]
[dsymutil] Implement the --threads option
This patch adds the --threads option to dsymutil to process
architectures in parallel. The feature is already present in the version
distributed with Xcode, but was not yet upstreamed.
This is NFC as far as the linking behavior is concerned. As threads are
used automatically, the current tests cover the change in
implementation.
Differential revision: https://reviews.llvm.org/D39355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316999
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Teresa Johnson [Tue, 31 Oct 2017 12:56:09 +0000 (12:56 +0000)]
[ThinLTO] Double bits of module hash used for renaming
Summary:
Use 64 instead of 32 bits of the module hash as the suffix when renaming
after promotion to reduce the likelihood of a collision (which we
observed in a binary when using 32 bits).
Reviewers: pcc
Subscribers: llvm-commits, inglorion
Differential Revision: https://reviews.llvm.org/D39443
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316996
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Matthew Simpson [Tue, 31 Oct 2017 12:34:02 +0000 (12:34 +0000)]
[InstCombine] Simplify selects that test cmpxchg instructions
If a select instruction tests the returned flag of a cmpxchg instruction and
selects between the returned value of the cmpxchg instruction and its compare
operand, the result of the select will always be equal to its false value.
Differential Revision: https://reviews.llvm.org/D39383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316994
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Ayman Musa [Tue, 31 Oct 2017 11:39:31 +0000 (11:39 +0000)]
Adding a shufflevector and select LLVM IR instructions fuzz tool
Based on similar python tool - utils/shuffle-fuzz.py - this tool extends the ability of it's previous by optionally attaching select instruction to the generated shufflevector instructions.
This was mainly developed to perform exhaustive testing of the X86 AVX512 masked shuffle instructions. But yet it can be used for various other targets.
The general design of the implementation is much modular than the original shuffle_fuzz.py tool, which makes it easier for anyone to extend it further.
Differential Revision: https://reviews.llvm.org/D38031
Change-Id: I0efc2aaa091b61a8a9552311c21cc77916a97111
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316989
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David Green [Tue, 31 Oct 2017 10:47:46 +0000 (10:47 +0000)]
[LoopUnroll] Clean up remarks for unroll remainder
The optimisation remarks for loop unrolling with an unrolled remainder looks something like:
test.c:7:18: remark: completely unrolled loop with 3 iterations [-Rpass=loop-unroll]
C[i] += A[i*N+j];
^
test.c:6:9: remark: unrolled loop by a factor of 4 with run-time trip count [-Rpass=loop-unroll]
for(int j = 0; j < N; j++)
^
This removes the first of the two messages.
Differential revision: https://reviews.llvm.org/D38725
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316986
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Michael Zuckerman [Tue, 31 Oct 2017 10:00:19 +0000 (10:00 +0000)]
[AVX512] Adding new patterns for extract_subvector of vXi1
extract subvector of vXi1 from vYi1 is poorly supported by LLVM and most of the time end with an assertion.
This patch fixes this issue by adding new patterns to the TD file.
Reviewers:
1. guyblank
2. igorb
3. zvi
4. ayman
5. craig.topper
Differential Revision: https://reviews.llvm.org/D39292
Change-Id: Ideb4d7e946c8d40cfce2920891f2d89fe64c58f8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316981
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Serguei Katkov [Tue, 31 Oct 2017 07:01:35 +0000 (07:01 +0000)]
[CGP] Fix the detection of trivial case for addressing mode
The address can be presented as a bitcast of baseReg.
In this case it is still trivial but OriginalValue != baseReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316980
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Max Kazantsev [Tue, 31 Oct 2017 06:19:05 +0000 (06:19 +0000)]
[IRCE][NFC] Rename fields of InductiveRangeCheck
Rename `Offset`, `Scale`, `Length` into `Begin`, `Step`, `End` respectively
to make naming of similar entities for Ranges and Range Checks more
consistent.
Differential Revision: https://reviews.llvm.org/D39414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316979
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Craig Topper [Tue, 31 Oct 2017 06:01:04 +0000 (06:01 +0000)]
[X86] Make AVX512_512_SET0 XMM16-31 lower to 128-bit XOR when AVX512VL is enabled. Use 128-bit VLX instruction when VLX is enabled.
Unfortunately, this weakens our ability to do domain fixing when AVX512DQ is not enabled, but it is consistent with our 256-bit behavior.
Maybe we should add custom handling to domain fixing to allow EVEX integer XOR/AND/OR/ANDN to switch to VEX encoded fp instructions if the high registers aren't being used?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316978
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Max Kazantsev [Tue, 31 Oct 2017 05:33:58 +0000 (05:33 +0000)]
[NFC] Get rid of variables used in assert only
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316977
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Philip Reames [Tue, 31 Oct 2017 05:16:46 +0000 (05:16 +0000)]
[IndVarSimplify] Simplify code using preheader assumption
As noted in the nice block comment, the previous code didn't actually handle multi-entry loops correctly, it just assumed SCEV didn't analyze such loops. Given SCEV has comments to the contrary, that seems a bit suspect. More importantly, the pass actually requires loopsimplify form which ensures a loop-preheader is available. Remove the excessive generaility and shorten the code greatly.
Note that we do successfully analyze many multi-entry loops, but we do so by converting them to single entry loops. See the added test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316976
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Max Kazantsev [Tue, 31 Oct 2017 05:07:56 +0000 (05:07 +0000)]
Reapply "[GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors"
This patch fixes the miscompile that happens when PRE hoists loads across guards and
other instructions that don't always pass control flow to their successors. PRE is now prohibited
to hoist across such instructions because there is no guarantee that the load standing after such
instruction is still valid before such instruction. For example, a load from under a guard may be
invalid before the guard in the following case:
int array[LEN];
...
guard(0 <= index && index < LEN);
use(array[index]);
Differential Revision: https://reviews.llvm.org/D37460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316975
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Philip Reames [Tue, 31 Oct 2017 04:19:06 +0000 (04:19 +0000)]
[SimplifyIndVar] Extract out invariant expression handling
Previously, the code returned early from the *function* when it couldn't find a free expansion, it should be returning from the *transform*. I don't have a test case, noticed this via inspection.
As a follow up, I'm going to revisit the logic in the extract function. I think that essentially the whole helper routine can be replaced with SCEVExpander, but I wanted to do that in a series of separate commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316974
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Craig Topper [Tue, 31 Oct 2017 02:34:29 +0000 (02:34 +0000)]
[X86] Clang-format some code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316973
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Shoaib Meenai [Tue, 31 Oct 2017 01:30:46 +0000 (01:30 +0000)]
[cmake] Make check_linker_flags operate via linker flags
`check_linker_flags` currently sets the *compiler* flags (via
`CMAKE_REQUIRED_FLAGS`), and thus implicitly relies on cmake's default
behavior of passing the compiler flags to the linker. This breaks when
cmake's build rules have been altered to not pollute the link line with
compiler flags (which can be desirable for build cleanliness). Instead,
set `CMAKE_EXE_LINKER_FLAGS` explicitly and use `CMP0056` to ensure the
linker flags are passed along. Additionally, since we're inside a
function, we can just alter the variable directly (as the alteration
will be limited to the scope of the function) rather than saving and
restoring the old value.
Differential Revision: https://reviews.llvm.org/D39431
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316972
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Philip Reames [Tue, 31 Oct 2017 00:04:09 +0000 (00:04 +0000)]
Undo accidental commit
These files shouldn't have been submitted in 316967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316968
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Philip Reames [Mon, 30 Oct 2017 23:59:51 +0000 (23:59 +0000)]
[CGP] Fix crash on i96 bit multiply
Issue found by llvm-isel-fuzzer on OSS fuzz, https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3725
If anyone actually cares about > 64 bit arithmetic, there's a lot more to do in this area. There's a bunch of obviously wrong code in the same function. I don't have the time to fix all of them and am just using this to understand what the workflow for fixing fuzzer cases might look like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316967
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Simon Pilgrim [Mon, 30 Oct 2017 22:38:07 +0000 (22:38 +0000)]
Fix unused variable warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316964
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Simon Pilgrim [Mon, 30 Oct 2017 22:23:57 +0000 (22:23 +0000)]
[SelectionDAG] Tidyup computeKnownBits extension/truncation cases. NFCI.
We don't need to extend/truncate the Known structure before calling computeKnownBits - it will reset at the start of the function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316962
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Javed Absar [Mon, 30 Oct 2017 22:00:06 +0000 (22:00 +0000)]
[AArch64]: range loopify frame-lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316960
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Rui Ueyama [Mon, 30 Oct 2017 21:19:54 +0000 (21:19 +0000)]
Fix -fuse-ld feature detection error.
check_cxx_compiler_flag doesn't seem to try to link a program, so
the existing code doesn't correctly detect the availability of a given
linker. This patch uses check_cxx_source_compiles instead.
I confirmed that cmake now reports this error
Host compiler does not support '-fuse-ld=foo'
for -DLLVM_USE_LINKER=foo.
Differential Revision: https://reviews.llvm.org/D39274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316958
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Yaxun Liu [Mon, 30 Oct 2017 21:19:41 +0000 (21:19 +0000)]
InferAddressSpaces: Fix bug about replacing addrspacecast
InferAddressSpaces assumes the pointee type of addrspacecast
is the same as the operand, which is not always true and causes
invalid IR.
This bug cause build failure in HCC.
This patch fixes that.
Differential Revision: https://reviews.llvm.org/D39432
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316957
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Tim Shen [Mon, 30 Oct 2017 21:12:14 +0000 (21:12 +0000)]
[CMake] Fix linker detection in AddLLVM.cmake
Fix linker not being correctly detected when a custom one is specified
through LLVM_USE_LINKER CMake variable.
In particular,
cmake -DCMAKE_BUILD_TYPE=Release -DLLVM_USE_LINKER=gold ../llvm
resulted into
Linker detection: GNU ld
instead of
Linker detection: GNU Gold
due to the construction not accounting for such variable. It led to the general
confusion and prevented setting linker-specific flags inside functions defined
in AddLLVM.cmake.
Thanks Oleksii Vilchanskyi for the patch!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316956
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Craig Topper [Mon, 30 Oct 2017 21:09:19 +0000 (21:09 +0000)]
[X86] Add AVX512 support to fast isel's X86ChooseCmpOpcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316955
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Davide Italiano [Mon, 30 Oct 2017 20:20:16 +0000 (20:20 +0000)]
[NewGVN] Stop assuming PHI args ordering when looking at phi-of-ops.
It's not guaranteed. There's a bug open to sort them in predecessor
order, but it won't happen anytime soon. In the meanwhile, passes
will have to do an O(#preds) scan. Such is life.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316953
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Stefan Pintilie [Mon, 30 Oct 2017 19:55:38 +0000 (19:55 +0000)]
Revert "[PowerPC] Try to simplify a Swap if it feeds a Splat"
Revert r316478.
A test case has failed.
Will recommit this change once we find and fix the failure.
This reverts commit
7c330fabaedaba3d02c58bc3cc1198896c895f34.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316952
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Daniel Neilson [Mon, 30 Oct 2017 19:51:48 +0000 (19:51 +0000)]
Create instruction classes for identifying any atomicity of memory intrinsic. (NFC)
Summary:
For reference, see: http://lists.llvm.org/pipermail/llvm-dev/2017-August/116589.html
This patch fleshes out the instruction class hierarchy with respect to atomic and
non-atomic memory intrinsics. With this change, the relevant part of the class
hierarchy becomes:
IntrinsicInst
-> MemIntrinsicBase (methods-only class)
-> MemIntrinsic (non-atomic intrinsics)
-> MemSetInst
-> MemTransferInst
-> MemCpyInst
-> MemMoveInst
-> AtomicMemIntrinsic (atomic intrinsics)
-> AtomicMemSetInst
-> AtomicMemTransferInst
-> AtomicMemCpyInst
-> AtomicMemMoveInst
-> AnyMemIntrinsic (both atomicities)
-> AnyMemSetInst
-> AnyMemTransferInst
-> AnyMemCpyInst
-> AnyMemMoveInst
This involves some class renaming:
ElementUnorderedAtomicMemCpyInst -> AtomicMemCpyInst
ElementUnorderedAtomicMemMoveInst -> AtomicMemMoveInst
ElementUnorderedAtomicMemSetInst -> AtomicMemSetInst
A script for doing this renaming in downstream trees is included below.
An example of where the Any* classes should be used in LLVM is when reasoning
about the effects of an instruction (ex: aliasing).
---
Script for renaming AtomicMem* classes:
PREFIXES="[<,([:space:]]"
CLASSES="MemIntrinsic|MemTransferInst|MemSetInst|MemMoveInst|MemCpyInst"
SUFFIXES="[;)>,[:space:]]"
REGEX="(${PREFIXES})ElementUnorderedAtomic(${CLASSES})(${SUFFIXES})"
REGEX2="visitElementUnorderedAtomic(${CLASSES})"
FILES=$( grep -E "(${REGEX}|${REGEX2})" -r . | tr ':' ' ' | awk '{print $1}' | sort | uniq )
SED_SCRIPT="s~${REGEX}~\1Atomic\2\3~g"
SED_SCRIPT2="s~${REGEX2}~visitAtomic\1~g"
for f in $FILES; do
echo "Processing: $f"
sed -i ".bak" -E "${SED_SCRIPT};${SED_SCRIPT2};${EA_SED_SCRIPT};${EA_SED_SCRIPT2}" $f
done
Reviewers: sanjoy, deadalnix, apilipenko, anna, skatkov, mkazantsev
Reviewed By: sanjoy
Subscribers: hfinkel, jholewinski, arsenm, sdardis, nhaehnle, JDevlieghere, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D38419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316950
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Mandeep Singh Grang [Mon, 30 Oct 2017 19:42:41 +0000 (19:42 +0000)]
[GVNHoist] Fix non-deterministic sort order of PHIs for identical instructions
Summary: This fixes failure in Transforms/GVNHoist/hoist.ll uncovered by D39245.
Reviewers: hiraditya, spop, dberlin
Reviewed By: dberlin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39410
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316949
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Simon Pilgrim [Mon, 30 Oct 2017 19:31:08 +0000 (19:31 +0000)]
[SelectionDAG] Add VSELECT demanded elts support to computeKnownBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316947
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Zvi Rackover [Mon, 30 Oct 2017 19:29:15 +0000 (19:29 +0000)]
X86 Tests: Update the variable-index permute tests with FP types. NFC.
These cases will be addressed in a future update to D39126.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316946
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Simon Pilgrim [Mon, 30 Oct 2017 19:19:58 +0000 (19:19 +0000)]
[X86][SSE] Add another computeKnownBits test showing missing VSELECT demandedelts support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316945
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Simon Pilgrim [Mon, 30 Oct 2017 19:08:21 +0000 (19:08 +0000)]
[SelectionDAG] Add VSELECT support to computeKnownBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316944
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Simon Pilgrim [Mon, 30 Oct 2017 18:48:31 +0000 (18:48 +0000)]
[X86][SSE] computeKnownBits tests showing missing VSELECT demandedelts support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316940
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Simon Pilgrim [Mon, 30 Oct 2017 18:37:27 +0000 (18:37 +0000)]
[X86][AVX512] Cleanup scheduler tests - split GENERIC and SKX targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316938
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Simon Pilgrim [Mon, 30 Oct 2017 17:53:51 +0000 (17:53 +0000)]
[SelectionDAG] Add SELECT demanded elts support to ComputeNumSignBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316933
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Simon Pilgrim [Mon, 30 Oct 2017 17:46:50 +0000 (17:46 +0000)]
[X86][SSE] ComputeNumSignBits tests showing missing VSELECT demandedelts support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316932
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Simon Pilgrim [Mon, 30 Oct 2017 17:24:40 +0000 (17:24 +0000)]
[MC] Split out register def/use idx calls to make debugging simpler. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316927
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Simon Pilgrim [Mon, 30 Oct 2017 17:23:17 +0000 (17:23 +0000)]
[X86][AVX] Add missing vcvtpd2dq/vcvtps2dq scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316926
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Simon Pilgrim [Mon, 30 Oct 2017 17:20:50 +0000 (17:20 +0000)]
[X86][SSE] Add clflush scheduling test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316925
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Jina Nahias [Mon, 30 Oct 2017 16:37:28 +0000 (16:37 +0000)]
[X86][AVX512] Adding a pattern for broadcastm intrinsic.
Differential Revision: https://reviews.llvm.org/D38312
Change-Id: I71c8605a8e4c98013ef25289694afc5cfd46bb0b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316921
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Rafael Espindola [Mon, 30 Oct 2017 16:32:31 +0000 (16:32 +0000)]
Move isDSOLocal check and add a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316920
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Fangrui Song [Mon, 30 Oct 2017 16:03:44 +0000 (16:03 +0000)]
[PPC CodeGen] Fix the bitreverse.i64 intrinsic.
Summary: The two 32-bit words were swapped. Update a test omitted in reverted r316270.
Reviewers: jtony, aaron.ballman
Subscribers: nemanjai, kbarton
Differential Revision: https://reviews.llvm.org/D39163
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316916
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Craig Topper [Mon, 30 Oct 2017 14:51:37 +0000 (14:51 +0000)]
[X86] Make sure we don't create locked inc/dec instructions when the carry flag is being used.
Summary:
INC/DEC don't update the carry flag so we need to make sure we don't try to use it.
This patch introduces new X86ISD opcodes for locked INC/DEC. Teaches lowerAtomicArithWithLOCK to emit these nodes if INC/DEC is not slow or the function is being optimized for size. An additional flag is added that allows the INC/DEC to be disabled if the caller determines that the carry flag is being requested.
The test_sub_1_cmp_1_setcc_ugt test is currently showing this bug. The other test case changes are recovering cases that were regressed in r316860.
This should fully fix PR35068 finishing the fix started in r316860.
Reviewers: RKSimon, zvi, spatel
Reviewed By: zvi
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316913
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Craig Topper [Mon, 30 Oct 2017 14:50:11 +0000 (14:50 +0000)]
[X86] Remove AVX512 early out from X86FastISel::X86SelectCmp.
This shouldn't be needed anymore since i1 isn't a legal type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316912
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Craig Topper [Mon, 30 Oct 2017 14:50:10 +0000 (14:50 +0000)]
[X86] Regenerate test using update_llc_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316911
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Sanjay Patel [Mon, 30 Oct 2017 14:34:30 +0000 (14:34 +0000)]
[PassManager, SimplifyCFG] add test for PR34603 / D38566; NFC
Sinking common insts and converting to select early can inhibit better folds in other passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316908
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Yaxun Liu [Mon, 30 Oct 2017 14:30:28 +0000 (14:30 +0000)]
[AMDGPU] Emit metadata for hidden arguments for kernel enqueue
Identifies kernels which performs device side kernel enqueues and emit
metadata for the associated hidden kernel arguments. Such kernels are
marked with calls-enqueue-kernel function attribute by
AMDGPUOpenCLEnqueueKernelLowering pass and later on
hidden kernel arguments metadata HiddenDefaultQueue and
HiddenCompletionAction are emitted for them.
Differential Revision: https://reviews.llvm.org/D39255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316907
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Clement Courbet [Mon, 30 Oct 2017 14:19:33 +0000 (14:19 +0000)]
[CodeGen][ExpandMemcmp] Allow memcmp to expand to vector loads (2).
- Targets that want to support memcmp expansions now return the list of
supported load sizes.
- Expansion codegen does not assume that all power-of-two load sizes
smaller than the max load size are valid. For examples, this is not the
case for x86(32bit)+sse2.
Fixes PR34887.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316905
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Krzysztof Parzyszek [Mon, 30 Oct 2017 14:11:52 +0000 (14:11 +0000)]
[Hexagon] Allow the RDF optimizations to be run in .mir testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316904
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Javed Absar [Mon, 30 Oct 2017 13:51:56 +0000 (13:51 +0000)]
[GlobalISel|ARM] : Allow legalizing G_FSUB
Adding support for VSUB.
Reviewed by: @rovka
Differential Revision: https://reviews.llvm.org/D39261
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316902
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Andrew V. Tischenko [Mon, 30 Oct 2017 12:02:06 +0000 (12:02 +0000)]
Invalid used of 'w' suffix on push and pop using 64-bit register.
Differential Revision: https://reviews.llvm.org/D38626
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316898
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Diana Picus [Mon, 30 Oct 2017 11:58:09 +0000 (11:58 +0000)]
[ARM GlobalISel] Fixup r316572. NFC
Just missed a few spots...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316897
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Jina Nahias [Mon, 30 Oct 2017 10:35:53 +0000 (10:35 +0000)]
Revert "[X86][AVX512] Adding a pattern for broadcastm intrinsic."
This reverts commit r316890.
Change-Id: I683cceee9848ef309b452293086b1f26a941950d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316894
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Florian Hahn [Mon, 30 Oct 2017 10:07:42 +0000 (10:07 +0000)]
Recommit r315288: [SCCP] Propagate integer range info for parameters in IPSCCP.
This version of the patch includes a fix addressing a stage2 LTO buildbot
failure and addressed some additional nits.
Original commit message:
This updates the SCCP solver to use of the ValueElement lattice for
parameters, which provides integer range information. The range
information is used to remove unneeded icmp instructions.
For the following function, f() can be optimized to ret i32 2 with
this change
source_filename = "sccp.c"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: norecurse nounwind readnone uwtable
define i32 @main() local_unnamed_addr #0 {
entry:
%call = tail call fastcc i32 @f(i32 1)
%call1 = tail call fastcc i32 @f(i32 47)
%add3 = add nsw i32 %call, %call1
ret i32 %add3
}
; Function Attrs: noinline norecurse nounwind readnone uwtable
define internal fastcc i32 @f(i32 %x) unnamed_addr #1 {
entry:
%c1 = icmp sle i32 %x, 100
%cmp = icmp sgt i32 %x, 300
%. = select i1 %cmp, i32 1, i32 2
ret i32 %.
}
attributes #1 = { noinline }
Reviewers: davide, sanjoy, efriedma, dberlin
Reviewed By: davide, dberlin
Subscribers: mcrosier, gberry, mssimpso, dberlin, llvm-commits
Differential Revision: https://reviews.llvm.org/D36656
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316891
91177308-0d34-0410-b5e6-
96231b3b80d8
Jina Nahias [Mon, 30 Oct 2017 09:59:52 +0000 (09:59 +0000)]
[X86][AVX512] Adding a pattern for broadcastm intrinsic.
Differential Revision: https://reviews.llvm.org/D38312
Change-Id: I6551fb13879e098aed74de410e29815cf37d9ab5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316890
91177308-0d34-0410-b5e6-
96231b3b80d8