OSDN Git Service
Philip Reames [Thu, 14 Mar 2019 18:02:19 +0000 (18:02 +0000)]
[Tests] Revert an accident change to a test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356183
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Jessica Paquette [Thu, 14 Mar 2019 18:01:30 +0000 (18:01 +0000)]
[GlobalISel][AArch64] Add partial selection support for G_INSERT_VECTOR_ELT
This adds support for inserting elements into packed vectors. It also adds
two tests: one for selection, and one for regbank select.
Unpacked vectors will come in a follow-up.
Differential Revision: https://reviews.llvm.org/D59325
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356182
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Philip Reames [Thu, 14 Mar 2019 17:59:59 +0000 (17:59 +0000)]
Auto-generate an existing test to make it easier to update
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356181
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Pete Couperus [Thu, 14 Mar 2019 17:50:46 +0000 (17:50 +0000)]
[ARC] Better classify add/sub immediate instructions in frame lowering.
Summary:
Some operations have multiple ARC instructions that are applicable.
For instance, "add r0, r0, 123" can be encoded as a "LImm" instruction
with a 32-bit immediate (8-bytes), or as a signed 12-bit immediate instruction
for the case where the source and destination register are the same (4-bytes).
The ARC assembler will choose the shortest encoding, but we should track
the correct instruction in the compiler.
This patch fixes the instruction used in some cases from ARCFrameLowering.
Subscribers: hiraditya, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59326
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356179
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Max Moroz [Thu, 14 Mar 2019 17:49:27 +0000 (17:49 +0000)]
Speeding up llvm-cov export with multithreaded renderFiles implementation.
Summary:
CoverageExporterJson::renderFiles accounts for most of the execution time given a large profdata file with multiple binaries.
Proposed solution is to generate JSON for each file in parallel and sort at the end to preserve deterministic output. Also added flags to skip generating parts of the output to trim the output size.
Patch by Sajjad Mirza (@sajjadm).
Reviewers: Dor1s, vsk
Reviewed By: Dor1s, vsk
Subscribers: liaoyuke, mgrang, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59277
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356178
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Sanjay Patel [Thu, 14 Mar 2019 17:39:40 +0000 (17:39 +0000)]
[InstCombine] add tests for funnel shift constant shift amount mod bitwidth; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356175
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Philip Reames [Thu, 14 Mar 2019 17:36:58 +0000 (17:36 +0000)]
[Tests] Add tests for reordering of unordered atomics on invariant locations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356172
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Philip Reames [Thu, 14 Mar 2019 17:20:59 +0000 (17:20 +0000)]
Allow code motion (and thus folding) for atomic (but unordered) memory operands
Building on the work done in D57601, now that we can distinguish between atomic and volatile memory accesses, go ahead and allow code motion of unordered atomics. As seen in the diffs, this allows much better folding of memory operations into using instructions. (Mostly done by the PeepholeOpt pass.)
Note: I have not reviewed all callers of hasOrderedMemoryRef since one of them - isSafeToMove - is very widely used. I'm relying on the documented semantics of each method to judge correctness.
Differential Revision: https://reviews.llvm.org/D59345
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356170
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Philip Reames [Thu, 14 Mar 2019 17:05:18 +0000 (17:05 +0000)]
[Tests] Add negative folding tests w/fences as requested in D59345
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356165
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Craig Topper [Thu, 14 Mar 2019 16:53:24 +0000 (16:53 +0000)]
[X86] Fix the pattern changes from r356121 so that the ROR*r1/ROR*m1 pattern use the rotr opcode.
These instructions used to use rotl with a bitwidth-1 immediate. I changed the immediate to 1,
but failed to change the opcode.
Thankfully this seems to have not caused a functional issue because we now had two rotl by 1 patterns,
but the correct ones were earlier and took priority. So we just missed some optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356164
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Adrian Prantl [Thu, 14 Mar 2019 16:29:54 +0000 (16:29 +0000)]
Add IR debug info support for Elemental, Pure, and Recursive Procedures.
Patch by Eric Schweitz!
Differential Revision: https://reviews.llvm.org/D54043
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356163
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Sam Parker [Thu, 14 Mar 2019 15:36:54 +0000 (15:36 +0000)]
[NFC][ARM] Update test
Change some regex to handle commutable instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356159
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Sanjay Patel [Thu, 14 Mar 2019 15:32:34 +0000 (15:32 +0000)]
[x86] prevent infinite looping from vselect commutation (PR41066)
This is an immediate fix for:
https://bugs.llvm.org/show_bug.cgi?id=41066
...but as noted there and the code comments, we should do better
by stubbing this out sooner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356158
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Pavel Labath [Thu, 14 Mar 2019 15:23:40 +0000 (15:23 +0000)]
YAMLIO: Improve template arg deduction for mapOptional
Summary:
The way c++ template argument deduction works, both arguments are used
to deduce the template type in the three-argument overload of
mapOptional. This is a problem if the types are slightly different, even
if they are implicitly convertible. This is fairly easy to trigger with
integral types, as the default type of most integral constants is int,
which then requires casting the constant to the type of the other
argument.
This patch fixes that by using a separate template type for the default
value, which is then cast to the type of the first argument. To avoid
this conversion triggerring conversions marged as explicit, we use
static_assert to check that the types are implicitly convertible.
Reviewers: zturner, sammccall
Subscribers: kristina, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59142
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356157
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Matt Arsenault [Thu, 14 Mar 2019 14:19:01 +0000 (14:19 +0000)]
AMDGPU: Scavenge register instead of findUnusedReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356149
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Matt Arsenault [Thu, 14 Mar 2019 14:18:56 +0000 (14:18 +0000)]
GlobalISel: Use multiple returns for intrinsic structs
This is consistent with what SelectionDAG does and is much easier to
work with than the extract sequence with an artificial wide register.
For the AMDGPU control flow intrinsics, this was producing an s128 for
the i64, i1 tuple return. Any legalization that should apply to a real
s128 value would badly obscure the direct values that need to be seen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356147
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Than McIntosh [Thu, 14 Mar 2019 13:56:49 +0000 (13:56 +0000)]
[SampleFDO] add suffix elision control for fcn names
Summary:
Add hooks for determining the policy used to decide whether/how
to chop off symbol 'suffixes' when locating a given function
in a sample profile.
Prior to this change, any function symbols of the form "X.Y" were
elided/truncated into just "X" when looking up things in a sample
profile data file.
With this change, the policy on suffixes can be changed by adding a
new attribute "sample-profile-suffix-elision-policy" to the function:
this attribute can have the value "all" (the default), "selected", or
"none". A value of "all" preserves the previous behavior (chop off
everything after the first "." character, then treat that as the
symbol name). A value of "selected" chops off only the rightmost
".llvm.XXXX" suffix (where "XXX" is any string not containing a "."
char). A value of "none" indicates that names should be left as is.
Subscribers: jdoerfert, wmi, mtrofin, danielcdh, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58832
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356146
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Matt Arsenault [Thu, 14 Mar 2019 13:46:17 +0000 (13:46 +0000)]
Note ImmArg in documentation for adding intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356145
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Matt Arsenault [Thu, 14 Mar 2019 13:46:14 +0000 (13:46 +0000)]
ARM: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356144
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Matt Arsenault [Thu, 14 Mar 2019 13:46:09 +0000 (13:46 +0000)]
AMDGPU: Don't add unnecessary convergent attributes
These are redundant with the intrinsic declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356143
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Hans Wennborg [Thu, 14 Mar 2019 12:22:50 +0000 (12:22 +0000)]
gn build: Merge r356080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356139
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Simon Pilgrim [Thu, 14 Mar 2019 11:56:41 +0000 (11:56 +0000)]
[SystemZ] Remove icmp undef
Prep-work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356138
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Simon Pilgrim [Thu, 14 Mar 2019 11:54:46 +0000 (11:54 +0000)]
[SystemZ] Regenerate tests to make complete codegen more obvious
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356137
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James Henderson [Thu, 14 Mar 2019 11:47:41 +0000 (11:47 +0000)]
[llvm-objcopy]Don't implicitly strip sections in segments
This patch changes llvm-objcopy's behaviour to not strip sections that
are in segments, if they otherwise would be due to a stripping operation
(--strip-all, --strip-sections, --strip-non-alloc). This preserves the
segment contents. It does not change the behaviour of --strip-all-gnu
(although we could choose to do so), because GNU objcopy's behaviour in
this case seems to be to strip the section, nor does it prevent removing
of sections in segments with --remove-section (if a user REALLY wants to
remove a section, we should probably let them, although I could be
persuaded that warning might be appropriate). Tests have been added to
show this latter behaviour.
This fixes https://bugs.llvm.org/show_bug.cgi?id=41006.
Reviewed by: grimar, rupprecht, jakehehrlich
Differential Revision: https://reviews.llvm.org/D59293
This is a reland of r356129, attempting to fix greendragon failures
due to a suspected compatibility issue with od on the greendragon bots
versus other versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356136
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Sam Parker [Thu, 14 Mar 2019 11:38:55 +0000 (11:38 +0000)]
Fix for buildbots
Remove unused private field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356135
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James Henderson [Thu, 14 Mar 2019 11:23:04 +0000 (11:23 +0000)]
Revert r356129 due to greendragon bot failures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356133
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Sam Parker [Thu, 14 Mar 2019 11:14:13 +0000 (11:14 +0000)]
[ARM][ParallelDSP] Enable multiple uses of loads
When choosing whether a pair of loads can be combined into a single
wide load, we check that the load only has a sext user and that sext
also only has one user. But this can prevent the transformation in
the cases when parallel macs use the same loaded data multiple times.
To enable this, we need to fix up any other uses after creating the
wide load: generating a trunc and a shift + trunc pair to recreate
the narrow values. We also need to keep a record of which loads have
already been widened.
Differential Revision: https://reviews.llvm.org/D59215
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356132
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Sam Parker [Thu, 14 Mar 2019 11:05:07 +0000 (11:05 +0000)]
[NFC][LSR] Cleanup Cost API
Create members for Loop, ScalarEvolution, DominatorTree,
TargetTransformInfo and Formula.
Differential Revision: https://reviews.llvm.org/D58389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356131
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Sam Parker [Thu, 14 Mar 2019 10:57:40 +0000 (10:57 +0000)]
[ARM] Run ARMParallelDSP in the IRPasses phase
Run EarlyCSE before ParallelDSP and do this in the backend IR opt
phase.
Differential Revision: https://reviews.llvm.org/D59257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356130
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James Henderson [Thu, 14 Mar 2019 10:20:27 +0000 (10:20 +0000)]
[llvm-objcopy]Don't implicitly strip sections in segments
This patch changes llvm-objcopy's behaviour to not strip sections that
are in segments, if they otherwise would be due to a stripping operation
(--strip-all, --strip-sections, --strip-non-alloc). This preserves the
segment contents. It does not change the behaviour of --strip-all-gnu
(although we could choose to do so), because GNU objcopy's behaviour in
this case seems to be to strip the section, nor does it prevent removing
of sections in segments with --remove-section (if a user REALLY wants to
remove a section, we should probably let them, although I could be
persuaded that warning might be appropriate). Tests have been added to
show this latter behaviour.
This fixes https://bugs.llvm.org/show_bug.cgi?id=41006.
Reviewed by: grimar, rupprecht, jakehehrlich
Differential Revision: https://reviews.llvm.org/D59293
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356129
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Hans Wennborg [Thu, 14 Mar 2019 10:10:25 +0000 (10:10 +0000)]
gn build: Merge r356082
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356128
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Alex Bradbury [Thu, 14 Mar 2019 08:31:35 +0000 (08:31 +0000)]
[RISCV] Fix rL356123
The wrong version of the patch was committed. This fixes typos that broke the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356124
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Alex Bradbury [Thu, 14 Mar 2019 08:28:48 +0000 (08:28 +0000)]
[RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor RISCVRegisterInfo refactoring
The CSR renaming further prepares the way for an upcoming patch adding support for more
RISC-V ABIs.
Modify RISCVRegisterInfo::getCalleeSavedRegs and
RISCVRegisterInfo::getReservedRegs to do MF->getSubtarget<RISCVSubtarget>()
once rather than multiple times.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356123
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Alex Bradbury [Thu, 14 Mar 2019 08:17:44 +0000 (08:17 +0000)]
[RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs
Add a caller which exhausts regs then calls another function. This allows
getCalleePreservedRegs to be tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356122
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Craig Topper [Thu, 14 Mar 2019 07:07:26 +0000 (07:07 +0000)]
[X86] Add patterns for rotr by immediate to fix PR41057.
Prior to the introduction of funnel shift intrinsics we could count on rotate
by immediates prefering to use rotl since that's what MatchRotate would check
first. The or+shift pattern doesn't have a direction so one must be chosen
arbitrarily.
With funnel shift, there is a direction and fshr will try to use rotr first.
While fshl will try to use rotl first.
This patch adds the isel patterns for rotr to complement the rotl patterns. I've
put the rotr by 1 patterns in the instruction patterns. And moved the rotl by
bitwidth-1 patterns to separate Pat patterns.
Fixes PR41057.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356121
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Craig Topper [Thu, 14 Mar 2019 07:07:24 +0000 (07:07 +0000)]
[X86] Add various test cases for PR41057. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356120
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Quentin Colombet [Thu, 14 Mar 2019 01:37:13 +0000 (01:37 +0000)]
[GlobalISel][Utils] Add a getConstantVRegVal variant that looks through instrs
getConstantVRegVal used to only look for G_CONSTANT when looking at
unboxing the value of a vreg. However, constants are sometimes not
directly used and are hidden behind trunc, s|zext or copy chain of
computation.
In particular this may be introduced by the legalization process that
doesn't want to simplify these patterns because it can lead to infine
loop when legalizing a constant.
To circumvent that problem, add a new variant of getConstantVRegVal,
named getConstantVRegValWithLookThrough, that allow to look through
extensions.
Differential Revision: https://reviews.llvm.org/D59227
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356116
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Douglas Yung [Thu, 14 Mar 2019 01:24:35 +0000 (01:24 +0000)]
Fixup tests to check for any MCInst number instead of a specific one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356115
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Craig Topper [Thu, 14 Mar 2019 01:13:15 +0000 (01:13 +0000)]
[ResetMachineFunctionPass] Add visited functions statistics info
Adding a "NumFunctionsVisited" for collecting the visited function number.
It can be used to collect function pass rate in some tests,
the pass rate = (NumberVisited - NumberReset)/NumberVisited.
e.g. it can be used for caculating GlobalISel pass rate in Test-Suite.
Patch by Tianyang Zhu (zhutianyang)
Differential Revision: https://reviews.llvm.org/D59285
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356114
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Craig Topper [Thu, 14 Mar 2019 00:23:31 +0000 (00:23 +0000)]
[X86] Add 64-bit mode command lines to rot32.ll so that it will demonstrate PR41055 for 32 bit. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356112
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Jordan Rupprecht [Wed, 13 Mar 2019 23:40:16 +0000 (23:40 +0000)]
[llvm-objcopy][NFC] Remove unnecessary llvm-objcopy.h #includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356109
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Jessica Paquette [Wed, 13 Mar 2019 23:29:54 +0000 (23:29 +0000)]
[AArch64][GlobalISel] Gardening: Simplify subregister copy in selectBuildVector
NFC. Some more preliminary factoring for G_INSERT_VECTOR_ELT.
Also better code-reuse, etc., etc.
Differential Revision: https://reviews.llvm.org/D59323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356107
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Jessica Paquette [Wed, 13 Mar 2019 23:22:23 +0000 (23:22 +0000)]
[GlobalISel][AArch64] Gardening: Factor out vector inserts
Factor out the vector insert code in `selectBuildVector`. Replace part of it
with `emitScalarToVector`, since it was pretty much equivalent.
This will make implementing G_INSERT_VECTOR_ELT easier.
Differential Revision: https://reviews.llvm.org/D59322
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356106
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Jordan Rupprecht [Wed, 13 Mar 2019 22:26:01 +0000 (22:26 +0000)]
[llvm-objcopy] Cleanup errors from CopyConfig and remove llvm-objcopy.h dependency
error() was previously cleaned up from CopyConfig, but new uses were introduced.
This also tweaks the error message for --add-symbol to report all invalid flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356105
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Jason Liu [Wed, 13 Mar 2019 21:50:25 +0000 (21:50 +0000)]
[AIX][CMake] Changes for building on AIX with XL and GCC
Summary:
In support of IBM's efforts to produce a viable C and C++ LLVM compiler for AIX
(ref: RFC at http://lists.llvm.org/pipermail/llvm-dev/2019-February/130175.html),
this patch adds customizations to the CMake files in order to properly
invoke the host toolchain for the build on AIX.
Additional changes to enable a successful build will follow.
Patch by Xing Xue
Reviewers: hubert.reinterpretcast, jasonliu, sfertile
Reviewed by: hubert.reinterpretcast
Differential Revision: https://reviews.llvm.org/D58250
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356104
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Sam Clegg [Wed, 13 Mar 2019 21:29:20 +0000 (21:29 +0000)]
[WebAssembly] Improve support for "needed" list in dylink section
This change adds basic support for shared library dependencies
via the dylink section.
See https://github.com/WebAssembly/tool-conventions/pull/77
Differential Revision: https://reviews.llvm.org/D59237
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356102
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Jessica Paquette [Wed, 13 Mar 2019 21:19:29 +0000 (21:19 +0000)]
[GlobalISel][AArch64] Gardening: Factor out code to find lane indices
Some more refactoring for G_INSERT_VECTOR_ELT.
Factor out the code used to find a lane index from `selectExtractElt`. Put it
into a more general-purpose `getConstantValueForReg` function.
This will be shared with the code for G_INSERT_VECTOR_ELT.
Differential Revision: https://reviews.llvm.org/D59324
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356101
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Stanislav Mekhanoshin [Wed, 13 Mar 2019 21:15:52 +0000 (21:15 +0000)]
[AMDGPU] Silence gcc 7 warnings
Differential Revision: https://reviews.llvm.org/D59330
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356100
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Matt Arsenault [Wed, 13 Mar 2019 19:46:34 +0000 (19:46 +0000)]
Verifier: Make sure masked load/store alignment is a power of 2
The same should also be done for scatter/gather, but the verifier
doesn't check those at all now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356094
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Matt Arsenault [Wed, 13 Mar 2019 19:46:34 +0000 (19:46 +0000)]
PowerPC: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356093
91177308-0d34-0410-b5e6-
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Matt Arsenault [Wed, 13 Mar 2019 19:46:33 +0000 (19:46 +0000)]
Hexagon: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356092
91177308-0d34-0410-b5e6-
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Matt Arsenault [Wed, 13 Mar 2019 19:46:32 +0000 (19:46 +0000)]
SystemZ: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356091
91177308-0d34-0410-b5e6-
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Matt Arsenault [Wed, 13 Mar 2019 19:07:59 +0000 (19:07 +0000)]
Mips: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.
I'm not sure what's going on with the immediates.ll test. It seems to
be intended to test invalid cases like this, but then tries to handle
some of them anyway. I've moved the cases that were inconsistent with
the GCCBuiltin definition so they don't test the codegen anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356085
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 13 Mar 2019 19:07:54 +0000 (19:07 +0000)]
[X86] Remove icmp undef in more reduced tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356084
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 13 Mar 2019 19:04:45 +0000 (19:04 +0000)]
[X86] Regenerate tail call tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356083
91177308-0d34-0410-b5e6-
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Tim Renouf [Wed, 13 Mar 2019 18:56:33 +0000 (18:56 +0000)]
[MsgPack] Removed MsgPackTypes
Summary:
MsgPackTypes has been replaced by the lighter-weight MsgPackDocument.
Differential Revision: https://reviews.llvm.org/D57025
Change-Id: Ia7069880ef29f55490abbe5d8ae15f25cc1490a4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356082
91177308-0d34-0410-b5e6-
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Tim Renouf [Wed, 13 Mar 2019 18:55:50 +0000 (18:55 +0000)]
[AMDGPU] Switched HSA metadata to use MsgPackDocument
Summary:
MsgPackDocument is the lighter-weight replacement for MsgPackTypes. This
commit switches AMDGPU HSA metadata processing to use MsgPackDocument
instead of MsgPackTypes.
Differential Revision: https://reviews.llvm.org/D57024
Change-Id: I0751668013abe8c87db01db1170831a76079b3a6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356081
91177308-0d34-0410-b5e6-
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Tim Renouf [Wed, 13 Mar 2019 18:54:47 +0000 (18:54 +0000)]
[MsgPack] New MsgPackDocument class
Summary:
A class that exposes a simple in-memory representation of a document of
MsgPack objects, that can be read from and written to MsgPack, read from
and written to YAML, and inspected and modified in memory. This is
intended to be a lighter-weight (in terms of memory allocations)
replacement for MsgPackTypes.
Two subsequent changes will:
1. switch AMDGPU HSA metadata to using MsgPackDocument instead of
MsgPackTypes;
2. add MsgPack AMDGPU PAL metadata via MsgPackDocument.
Differential Revision: https://reviews.llvm.org/D57023
Change-Id: Ie15a054831d5a6467c5867c064c8f8f6b80270e1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356080
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 13 Mar 2019 18:48:50 +0000 (18:48 +0000)]
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b()
The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well.
We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass.
I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue.
Differential Revision: https://reviews.llvm.org/D59308
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356078
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 13 Mar 2019 18:36:59 +0000 (18:36 +0000)]
[X86] Avoid icmp undef in reduced tests
Because we don't currently simplify icmp with undef in DAG, bugpoint loves to introduce them during reduction.
This is a small step towards re-adding non-undef values into some of the simpler tests so that they should still test correctly and emit similar/same codegen.
Prep work for PR40800 ([SelectionDAG] Add UNDEF handling to SelectionDAG::FoldSetCC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356076
91177308-0d34-0410-b5e6-
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Alex Bradbury [Wed, 13 Mar 2019 18:25:23 +0000 (18:25 +0000)]
[RISCV] Regenerate test/CodeGen/RISCV/legalize-fneg.ll after rL356068
rL356068 caused some minor re-orderings. Regenerate legalize-fneg.ll to
reflect this, and remove the NOLIB check lines (they're redundant given that
the RV32I and RV64I check lines generated by update_llc_test_checks.py already
demonstrate there is no libcall).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356074
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Simon Pilgrim [Wed, 13 Mar 2019 18:18:24 +0000 (18:18 +0000)]
Regenerate test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356071
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Nirav Dave [Wed, 13 Mar 2019 17:44:40 +0000 (17:44 +0000)]
[DAGCombiner] Fix Comment. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356069
91177308-0d34-0410-b5e6-
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Nirav Dave [Wed, 13 Mar 2019 17:07:09 +0000 (17:07 +0000)]
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
Summary:
A number of optimizations are inhibited by single-use TokenFactors not
being merged into the TokenFactor using it. This makes we consider if
we can do the merge immediately.
Most tests changes here are due to the change in visitation causing
minor reorderings and associated reassociation of paired memory
operations.
CodeGen tests with non-reordering changes:
X86/aligned-variadic.ll -- memory-based add folded into stored leaq
value.
X86/constant-combiners.ll -- Optimizes out overlap between stores.
X86/pr40631_deadstore_elision -- folds constant byte store into
preceding quad word constant store.
Reviewers: RKSimon, craig.topper, spatel, efriedma, courbet
Reviewed By: courbet
Subscribers: dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, eraman, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59260
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356068
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Simon Pilgrim [Wed, 13 Mar 2019 17:00:18 +0000 (17:00 +0000)]
[X86][AVX] Add X86ISD::VTRUNC handling to SimplifyDemandedVectorEltsForTargetNode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356067
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 13 Mar 2019 16:37:30 +0000 (16:37 +0000)]
[X86][AVX] Add combineConcatVectors support to improve subvector handling
Attempt to combine CONCAT_VECTORS nodes, which we only really have pre-legalization.
This encourages a lot of X86ISD::SUBV_BROADCAST generation, so I've added SimplifyDemandedVectorEltsForTargetNode handling for this at the same time.
The X86ISD::VTRUNC regression in shuffle-vs-trunc-256-widen.ll will be handled in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356064
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Alex Bradbury [Wed, 13 Mar 2019 16:33:45 +0000 (16:33 +0000)]
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
This follows similar logic in the ARM and Mips backends, and allows the free
use of s0 in functions without a dedicated frame pointer. The changes in
callee-saved-gprs.ll most clearly show the effect of this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356063
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Alex Bradbury [Wed, 13 Mar 2019 16:14:16 +0000 (16:14 +0000)]
[RISCV] Add tests for callee-saved GPRs, FPR32s, and FPR64s
Note that s0 need not be marked reserved if the frame pointer isn't used. For
the ILP32 and LP64 soft float ABIS that are currently support, all FPRs are
always considered temporaries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356061
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Simon Atanasyan [Wed, 13 Mar 2019 16:00:42 +0000 (16:00 +0000)]
[mips] Join some adjacent `let DecoderNamespace` blocks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356059
91177308-0d34-0410-b5e6-
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Louis Dionne [Wed, 13 Mar 2019 15:35:21 +0000 (15:35 +0000)]
[NFC][CMake] Improve Status message in the iOS toolchain file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356056
91177308-0d34-0410-b5e6-
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Sander de Smalen [Wed, 13 Mar 2019 15:18:27 +0000 (15:18 +0000)]
[AArch64] Add test/CodeGen/AArch64/vecreduce-fadd.ll
This test is added to see difference created by:
https://reviews.llvm.org/D59259
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356054
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Sanjay Patel [Wed, 13 Mar 2019 14:49:52 +0000 (14:49 +0000)]
[x86] limit extractelement of setcc to pre-legalization
A fuzzer found the crasher:
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=13700
The bug was introduced recently here:
rL355741
This is the quick fix. If we need to do this transform
later, then we'd have to extend/truncate the vector setcc
element type to the scalar setcc type (i8).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356053
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Simon Atanasyan [Wed, 13 Mar 2019 14:23:12 +0000 (14:23 +0000)]
[mips] Fix encoding of the `mov.d` command for microMIPS R6
Before this change LLVM emits non-microMIPS variant of the `mov.d`
command for microMIPS code.
Differential Revision: http://reviews.llvm.org/D59045
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356052
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Simon Atanasyan [Wed, 13 Mar 2019 14:22:58 +0000 (14:22 +0000)]
[mips] Define `mov.d` instructions using `ABSS_M` multiclass. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356051
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Clement Courbet [Wed, 13 Mar 2019 13:56:23 +0000 (13:56 +0000)]
Re-land r354244 "[DAGCombiner] Eliminate dead stores to stack."
Always check candidates for hasOtherUses(), not only stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356050
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Simon Pilgrim [Wed, 13 Mar 2019 13:14:14 +0000 (13:14 +0000)]
Fix signed/unsigned mismatch warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356046
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Simon Atanasyan [Wed, 13 Mar 2019 13:09:30 +0000 (13:09 +0000)]
[mips] Map SW instruction to its microMIPS R6 variant
To provide mapping between standard and microMIPS R6 variants of the
`sw` command we have to rename SWSP_xxx commands from "sw" to "swsp".
Otherwise `tablegen` starts to show the error `Multiple matches found
for `SW'`. After that to restore printing SWSP command as `sw`, I add
an appropriate `MipsInstAlias` instance.
We also need to implement "size reduction" for microMIPS R6. But this
task is for separate patch. After that the `micromips-lwsp-swsp.ll` test
case will be extended.
Differential Revision: http://reviews.llvm.org/D59046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356045
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Alex Bradbury [Wed, 13 Mar 2019 12:33:44 +0000 (12:33 +0000)]
[RISCV] Regenerate umulo-128-legalisation-lowering.ll
Upstream changes have improved codegen, reducing stack usage. Regenerate the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356044
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 13 Mar 2019 12:20:39 +0000 (12:20 +0000)]
[X86][AVX] lowerShuffleAsBroadcast - improve load folding by avoiding bitcasts
AVX1 broadcasts were failing as we were adding bitcasts that caused MayFoldLoad's hasOneUse to return false.
This patch stops introducing bitcasts so early and also replaces the broadcast index scaling through bitcasts (which can't succeed in some cases) to instead just keep track of the bitoffset which can be converted back to the broadcast index later on.
Differential Revision: https://reviews.llvm.org/D58888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356043
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 13 Mar 2019 11:51:13 +0000 (11:51 +0000)]
Appease MSVC builds by #ifdef wrapping runAndGetCommandOutput tests. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356042
91177308-0d34-0410-b5e6-
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Jeremy Morse [Wed, 13 Mar 2019 11:43:13 +0000 (11:43 +0000)]
[DebugInfo][Docs] Document how dbg.value intrinsics are interpreted in optimized code
This patch adds a section, ``Object lifetime in optimized code'', that
documents how such intrinsics are supposed to be handled. It sets out some of
the principles of how they specify variable locations, and how long those
locations are valid for.
This patch also documents one of the objectives behind the variable-location
design, that we should never allow the debugger to observe a state of the
program that would not have appeared without optimization.
Differential Revision: https://reviews.llvm.org/D58726
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356041
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 13 Mar 2019 11:08:57 +0000 (11:08 +0000)]
[DAG] Move integer setcc %x, %x folding into FoldSetCC
First step towards PR40800 - I intend to move the float case in a separate future patch.
I had to tweak the (overly reduced) thumb2 test and the x86 widening test change is annoying (no longer rematerializable) but we should address this separately.
Differential Revision: https://reviews.llvm.org/D59244
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356040
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Simon Atanasyan [Wed, 13 Mar 2019 11:04:38 +0000 (11:04 +0000)]
[MIPS][microMIPS] Fix PseudoMTLOHI_MM matching and expansion
On micromips MipsMTLOHI is always matched to PseudoMTLOHI_DSP regardless
of +dsp argument. This patch checks is HasDSP predicate is present for
PseudoMTLOHI_DSP so PseudoMTLOHI_MM can be matched when appropriate.
Add expansion of PseudoMTLOHI_MM instruction into a mtlo/mthi pair.
Patch by Mirko Brkusanin.
Differential Revision: http://reviews.llvm.org/D59203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356039
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Simon Atanasyan [Wed, 13 Mar 2019 11:04:28 +0000 (11:04 +0000)]
[mips] Fix CPU used in the test case to suppress warning. NFC
The MSA ASE used in in the test case requires MIPS32 revision 5 or
greater while the test uses MIPS32 revision 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356038
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Jonas Hahnfeld [Wed, 13 Mar 2019 10:38:17 +0000 (10:38 +0000)]
[ELF] Fix GCC8 warnings about "fall through", NFCI
Add break statements in Object/ELF.cpp since the code should consider the
generic tags for Hexagon, MIPS, and PPC. Add a test (copied from llvm-readobj)
to show that this works correctly (earlier versions of this patch would have
asserted).
The warnings in X86ELFObjectWriter.cpp are actually false-positives since
the nested switch() handles all possible values and returns in all cases.
Make this explicit by adding llvm_unreachable's.
Differential Revision: https://reviews.llvm.org/D58837
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356037
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Jonas Hahnfeld [Wed, 13 Mar 2019 10:37:56 +0000 (10:37 +0000)]
[Support] Treat truncation of fullpath as error
If the concatenation of arguments dir and bin has at least PATH_MAX
characters the call to snprintf will truncate. The result will usually
not exist, but if it does it's actually incorrect to return that the
path exists.
(Motivated by GCC compiler warning about format truncation.)
Differential Revision: https://reviews.llvm.org/D58835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356036
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Alex Bradbury [Wed, 13 Mar 2019 09:22:57 +0000 (09:22 +0000)]
[RISCV] Replace incorrect use of sizeof with array_lengthof
RISCVDisassembler was incorrectly using sizeof(Arr) when it should have used
sizeof(Arr)/sizeof(Arr[0]). Update to use array_lengthof instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356035
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Paul Hoad [Wed, 13 Mar 2019 08:15:03 +0000 (08:15 +0000)]
Revert "[clang-format] [PR25010] AllowShortIfStatementsOnASingleLine not working if an "else" statement is present"
This reverts commit
b358cbb9b78389e20f7be36e1a98e26515c3ecce.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356030
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Paul Hoad [Wed, 13 Mar 2019 08:07:46 +0000 (08:07 +0000)]
[clang-format] [PR25010] AllowShortIfStatementsOnASingleLine not working if an "else" statement is present
Summary:
Addressing: PR25010 - https://bugs.llvm.org/show_bug.cgi?id=25010
Code like:
```
if(true) var++;
else {
var--;
}
```
is reformatted to be
```
if (true)
var++;
else {
var--;
}
```
Even when `AllowShortIfStatementsOnASingleLine` is true
The following revision comes from a +1'd suggestion in the PR to support AllowShortIfElseStatementsOnASingleLine
This suppresses the clause prevents the merging of the if when there is a compound else
Reviewers: klimek, djasper, JonasToth, alexfh, krasimir, reuk
Reviewed By: reuk
Subscribers: reuk, Higuoxing, jdoerfert, cfe-commits
Tags: #clang-tools-extra
Differential Revision: https://reviews.llvm.org/D59087
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356029
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Philip Reames [Wed, 13 Mar 2019 03:25:20 +0000 (03:25 +0000)]
[ImplicitNullChecks] Support unordered atomic accesses
Update the INC pass to allow folding unordered atomics. This is the first optimization unblocked by the changes landed from D57601.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356006
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Philip Reames [Wed, 13 Mar 2019 03:17:58 +0000 (03:17 +0000)]
[Tests] Expand implicit null check coverage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356004
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Evgeniy Stepanov [Wed, 13 Mar 2019 01:37:58 +0000 (01:37 +0000)]
Revert "[llvm] Skip over empty line table entries."
This reverts commit r355972.
See the discussion at https://reviews.llvm.org/D58952.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356001
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Craig Topper [Wed, 13 Mar 2019 00:43:03 +0000 (00:43 +0000)]
[X86] Enable printAliasInstr for the Intel assembly printer so that AAM and AAD will print without an immediate when the immediate is 10.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355997
91177308-0d34-0410-b5e6-
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Heejin Ahn [Wed, 13 Mar 2019 00:37:31 +0000 (00:37 +0000)]
[WebAssembly] Place 'try' and 'catch' correctly wrt EH_LABELs
Summary:
After instruction selection phase, possibly-throwing calls, which were
previously invoke, are wrapped in `EH_LABEL` instructions. For example:
```
EH_LABEL <mcsymbol .Ltmp0>
CALL_VOID @foo ...
EH_LABEL <mcsymbol .Ltmp1>
```
`EH_LABEL` is placed also in the beginning of EH pads:
```
bb.1 (landing-pad):
EH_LABEL <mcsymbol .Ltmp2>
...
```
And we'd like to maintian this relationship, so when we place a `try`,
```
TRY ...
EH_LABEL <mcsymbol .Ltmp0>
CALL_VOID @foo ...
EH_LABEL <mcsymbol .Ltmp1>
```
When we place a `catch`,
```
bb.1 (landing-pad):
EH_LABEL <mcsymbol .Ltmp2>
%0:except_ref = CATCH ...
...
```
Previously we didn't treat EH_LABELs specially, so `try` was placed
right before a call, and `catch` was placed in the beginning of an EH
pad.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58914
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355996
91177308-0d34-0410-b5e6-
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Hubert Tong [Wed, 13 Mar 2019 00:12:43 +0000 (00:12 +0000)]
Use AIX version detection at LLVM run-time
Summary:
AIX compilers define macros based on the version of the operating
system.
This patch implements updating of versionless AIX triples to include the
host AIX version. Also, the host triple detection in the build system is
adjusted to strip the AIX version information so that the run-time
detection is preferred.
Reviewers: xingxue, stefanp, nemanjai, jasonliu
Reviewed By: xingxue
Subscribers: mgorny, kristina, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58798
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355995
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Craig Topper [Tue, 12 Mar 2019 23:48:07 +0000 (23:48 +0000)]
[X86] Add ImmArg markings to intrinsics.
Remove test cases that checked for not crashing when immediate operands were passed not an immediate. These are now considered ill-formed in IR.
This was done by manually scanning the intrinsic file for llvm_i32_ty and llvm_i8_ty which are the predominant types we use for immediates. Most of them are on vector intrinsics. I might have missed some other intrinsics.
Differential Revision: https://reviews.llvm.org/D58302
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355993
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Jason Liu [Tue, 12 Mar 2019 22:01:10 +0000 (22:01 +0000)]
Add XCOFF triple object format type for AIX
This patch adds an XCOFF triple object format type into LLVM.
This XCOFF triple object file type will be used later by object file and assembly generation for the AIX platform.
Differential Revision: https://reviews.llvm.org/D58930
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355989
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Francis Visoiu Mistrih [Tue, 12 Mar 2019 21:22:27 +0000 (21:22 +0000)]
Reland "[Remarks] Add -foptimization-record-passes to filter remark emission"
Currently we have -Rpass for filtering the remarks that are displayed as
diagnostics, but when using -fsave-optimization-record, there is no way
to filter the remarks while generating them.
This adds support for filtering remarks by passes using a regex.
Ex: `clang -fsave-optimization-record -foptimization-record-passes=inline`
will only emit the remarks coming from the pass `inline`.
This adds:
* `-fsave-optimization-record` to the driver
* `-opt-record-passes` to cc1
* `-lto-pass-remarks-filter` to the LTOCodeGenerator
* `--opt-remarks-passes` to lld
* `-pass-remarks-filter` to llc, opt, llvm-lto, llvm-lto2
* `-opt-remarks-passes` to gold-plugin
Differential Revision: https://reviews.llvm.org/D59268
Original llvm-svn: 355964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355984
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Philip Reames [Tue, 12 Mar 2019 21:09:58 +0000 (21:09 +0000)]
[Test] Add tests for implicit null checks on atomic/volatile instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355983
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Philip Reames [Tue, 12 Mar 2019 21:05:31 +0000 (21:05 +0000)]
For faulting ops, include a comment w/the fault destination
A faulting_op is one that has specified behavior when a fault occurs, generally redirecting control flow to another location. This change just adds a comment to the assembly output which makes it both human readable, and machine checkable w/o having to parse the FaultMap section. This is used to split a test file into two parts, so that I can (in a near future commit) easily extend the test file to demonstrate another case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355982
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