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Adrian Prantl [Mon, 18 Sep 2017 21:27:44 +0000 (21:27 +0000)]
llvm-dwarfdump: add a --show-parents options when selectively dumping DIEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313567
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Adrian Prantl [Mon, 18 Sep 2017 21:27:42 +0000 (21:27 +0000)]
Fix typo in testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313566
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Konstantin Zhuravlyov [Mon, 18 Sep 2017 21:22:45 +0000 (21:22 +0000)]
AMDGPU: Start selecting s_xnor_{b32, b64}
Differential Revision: https://reviews.llvm.org/D37981
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313565
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Sanjay Patel [Mon, 18 Sep 2017 20:54:26 +0000 (20:54 +0000)]
[DAG, x86] allow store merging before and after legalization (PR34217)
rL310710 allowed store merging to occur after legalization to catch stores that are created late,
but this exposes a logic hole seen in PR34217:
https://bugs.llvm.org/show_bug.cgi?id=34217
We will miss merging stores if the target lowers vector extracts into target-specific operations.
This patch allows store merging to occur both before and after legalization if the target chooses
to get maximum merging.
I don't think the potential regressions in the other tests are relevant. The tests are for
correctness of weird IR constructs rather than perf tests, and I think those are still correct.
Differential Revision: https://reviews.llvm.org/D37987
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313564
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Craig Topper [Mon, 18 Sep 2017 20:49:13 +0000 (20:49 +0000)]
[X86] Make sure we still emit zext for GR32 to GR64 when the source of the zext is AssertZext
The AssertZext we might see in this case is only giving information about the lower 32 bits. It isn't providing information about the upper 32 bits. So we should emit a zext.
This fixes PR28540.
Differential Revision: https://reviews.llvm.org/D37729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313563
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Kostya Serebryany [Mon, 18 Sep 2017 20:48:35 +0000 (20:48 +0000)]
[libFuzzer] one more trophy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313562
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Adrian Prantl [Mon, 18 Sep 2017 19:55:00 +0000 (19:55 +0000)]
llvm-dwarfdump: Sink the handling of ShowChildren into DWARFDie::dump(). NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313560
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Alexey Bataev [Mon, 18 Sep 2017 19:33:30 +0000 (19:33 +0000)]
[SLP] Add a test for PR34635, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313559
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Craig Topper [Mon, 18 Sep 2017 19:21:21 +0000 (19:21 +0000)]
[X86] Don't emit COPY_TO_REG to ABCD registers before EXTRACT_SUBREG of sub_8bit
This is similar to D37843, but for sub_8bit. This fixes all of the patterns except for the 2 that emit only an EXTRACT_SUBREG. That causes a verifier error with global isel because global isel doesn't know to issue the ABCD when doing this extract on 32-bits targets.
Differential Revision: https://reviews.llvm.org/D37890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313558
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Craig Topper [Mon, 18 Sep 2017 19:21:19 +0000 (19:21 +0000)]
[X86] Don't emit COPY_TO_REG to ABCD registers before EXTRACT_SUBREG of sub_8bit_hi
I'm pretty sure that InstrEmitter::EmitSubregNode will take care of this itself by calling ConstrainForSubReg which in turn calls TRI->getSubClassWithSubReg.
I think Jakob Stoklund Olesen alluded to this in his commit message for r141207 which added the code to EmitSubregNode.
Differential Revision: https://reviews.llvm.org/D37843
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313557
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Evandro Menezes [Mon, 18 Sep 2017 19:00:38 +0000 (19:00 +0000)]
[AArch64] Adjust the cost model for Exynos M1 and M2
Refine the model of FP loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313555
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Evandro Menezes [Mon, 18 Sep 2017 19:00:36 +0000 (19:00 +0000)]
[AArch64] Adjust the cost model for Exynos M1 and M2
Refine the model of loads and stores using the register offset addressing
modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313554
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Evandro Menezes [Mon, 18 Sep 2017 19:00:31 +0000 (19:00 +0000)]
[AArch64] Adjust the cost model for Exynos M1 and M2
Fix formatting in the predicate function AArch64InstrInfo::isExynosShiftLeftFast().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313553
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Ahmed Bougacha [Mon, 18 Sep 2017 18:50:09 +0000 (18:50 +0000)]
[GlobalISel] Only build expensive remarks if they're enabled. NFC.
r313390 taught 'allowExtraAnalysis' to check whether remarks are
enabled at all. Use that to only do the expensive instruction printing
if they are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313552
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Sanjay Patel [Mon, 18 Sep 2017 18:07:50 +0000 (18:07 +0000)]
[x86] add tests for PR34217; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313548
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Simon Pilgrim [Mon, 18 Sep 2017 17:58:31 +0000 (17:58 +0000)]
[X86][AVX] Improve (i8 bitcast (v8i1 x)) handling for 256-bit vector compare results.
As commented on D37849, AVX1 targets were missing a chance to use vmovmskps for v8f32/v8i32 results for bool vector bitcasts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313547
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Sanjay Patel [Mon, 18 Sep 2017 17:33:47 +0000 (17:33 +0000)]
[x86] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313545
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Manoj Gupta [Mon, 18 Sep 2017 17:28:15 +0000 (17:28 +0000)]
[LoopVectorizer] Add more testcases for PR33804.
Summary:
Add test cases when float <-> pointer types conversion is triggered
in presence of load instructions.
Reviewers: Ayal, srhines, mkuper, rengolin
Reviewed By: rengolin
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D37967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313544
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Simon Pilgrim [Mon, 18 Sep 2017 16:45:05 +0000 (16:45 +0000)]
[SelectionDAG] Add BITCAST handling to ComputeNumSignBits for splatted sign bits.
For cases where we are BITCASTing to vectors of smaller elements, then if the entire source was a splatted sign (src's NumSignBits == SrcBitWidth) we can say that the dst's NumSignBit == DstBitWidth, as we're just splitting those sign bits across multiple elements.
We could generalize this but at the moment the only use case I have is to peek through bitcasts to vector comparison results.
Differential Revision: https://reviews.llvm.org/D37849
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313543
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Craig Topper [Mon, 18 Sep 2017 16:39:49 +0000 (16:39 +0000)]
[X86] Fix two more places to prefer VPERMQ/PD over VPERM2X128 when AVX2 is enabled
The shuffle combining and lowerVectorShuffleAsLanePermuteAndBlend were both still trying to use VPERM2XF128 for unary shuffles when AVX2 is enabled. VPERM2X128 takes two inputs meaning when we use it for a unary shuffle one of those inputs is left undefined creating a false dependency on whatever register gets allocated there.
If we have VPERMQ/PD we should prefer those since they only have a single input.
Differential Revision: https://reviews.llvm.org/D37947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313542
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Sanjay Patel [Mon, 18 Sep 2017 16:20:15 +0000 (16:20 +0000)]
[SLP] clean up for vector store case; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313541
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Sam Parker [Mon, 18 Sep 2017 14:46:14 +0000 (14:46 +0000)]
[AArch64] Add V8_2aOps feature to Cortex-A55 and 75
Add the missing hardware features the ProcA55 and ProcA75 feature.
These are already enabled via the target parser, but I had missed
them in the backend.
Differential Revision: https://reviews.llvm.org/D37974
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313535
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Alex Bradbury [Mon, 18 Sep 2017 14:33:39 +0000 (14:33 +0000)]
Add myself to CREDITS.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313534
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Sam Parker [Mon, 18 Sep 2017 14:28:51 +0000 (14:28 +0000)]
[ARM] Implement isTruncateFree
Implement the isTruncateFree hooks, lifted from AArch64, that are
used by TargetTransformInfo. This allows simplifycfg to reduce the
test case into a single basic block.
Differential Revision: https://reviews.llvm.org/D37516
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313533
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Simon Pilgrim [Mon, 18 Sep 2017 14:23:23 +0000 (14:23 +0000)]
[X86][SSE] Improve support for vselect(Cond, 0, X) -> ANDN(Cond, X)
As discussed on PR28925 and D37849.
Differential Revision: https://reviews.llvm.org/D37975
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313532
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Sjoerd Meijer [Mon, 18 Sep 2017 14:17:57 +0000 (14:17 +0000)]
[ARM] Fix for indexed dot product instruction descriptions
The indexed dot product instructions only accept the lower 16 D-registers as
the indexed register, but we were e.g. incorrectly accepting:
vudot.u8 d16,d16,d18[0]
Differential Revision: https://reviews.llvm.org/D37968
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313531
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Jonas Devlieghere [Mon, 18 Sep 2017 14:15:57 +0000 (14:15 +0000)]
[dwarfdump] Make .eh_frame an alias for .debug_frame
This patch makes the `.eh_frame` extension an alias for `.debug_frame`.
Up till now it was only possible to dump the section using objdump, but
not with dwarfdump. Since the two are essentially interchangeable, we
dump whichever of the two is present.
As a workaround, this patch also adds parsing for 3 currently
unimplemented CFA instructions: `DW_CFA_def_cfa_expression`,
`DW_CFA_expression`, and `DW_CFA_val_expression`. Because I lack the
required knowledge, I just parse the fields without actually creating
the instructions.
Finally, this also fixes the typo in the `.debug_frame` section name
which incorrectly contained a trailing `s`.
Differential revision: https://reviews.llvm.org/D37852
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313530
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Simon Pilgrim [Mon, 18 Sep 2017 13:32:33 +0000 (13:32 +0000)]
[X86][SSE] Add vselect with zero tests (PR28925)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313529
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Simon Pilgrim [Mon, 18 Sep 2017 12:55:54 +0000 (12:55 +0000)]
[X86] combineVSelectWithAllOnesOrZeros - cleanup variable names. NFCI.
We were reusing the 'false' select value 'is zero' variable name for the 'true' select value 'is zero' variable name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313528
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Nikolai Bozhenov [Mon, 18 Sep 2017 10:17:59 +0000 (10:17 +0000)]
[X86FixupBWInsts] More precise register liveness if no <imp-use> on MOVs.
Summary:
Subregister liveness tracking is not implemented for X86 backend, so
sometimes the whole super register is said to be live, when only a
subregister is really live. That might happen if the def and the use
are located in different MBBs, see added fixup-bw-isnt.mir test.
However, using knowledge of the specific instructions handled by the
bw-fixup-pass we can get more precise liveness information which this
change does.
Reviewers: MatzeB, DavidKreitzer, ab, andrew.w.kaylor, craig.topper
Reviewed By: craig.topper
Subscribers: n.bozhenov, myatsina, llvm-commits, hiraditya
Patch by Andrei Elovikov <andrei.elovikov@intel.com>
Differential Revision: https://reviews.llvm.org/D37559
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313524
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Mohammed Agabaria [Mon, 18 Sep 2017 06:49:54 +0000 (06:49 +0000)]
[X86][Codegen] adding masked gathers tests for avx2
related to patch: https://reviews.llvm.org/D35772
adding llvm gathers test before gathers codegen support.
Differential Revision: https://reviews.llvm.org/D37800
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313516
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Dean Michael Berris [Mon, 18 Sep 2017 06:08:46 +0000 (06:08 +0000)]
[XRay][tools] Support tail-call exits before we write them in the runtime
Summary:
This change adds support for explicit tail-exit records to be written by
the XRay runtime. This lets us differentiate the tail exit
records/events in the log, and allows us to treat those exit events
especially in the future. For now we allow printing those out in YAML
(and reading them in).
Reviewers: kpw, pelikan
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313514
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Craig Topper [Mon, 18 Sep 2017 05:50:54 +0000 (05:50 +0000)]
[X86] Strengthen some of the SD type constraints in X86InstrFragmentsSIMD.td
This effects the vector shift and rotates as well as some of the vector compares.
The changes to the shifts by immediates allows a few hundred bytes to be removed by removing type checks for the size of the immediate containing the shift/rotate amount.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313512
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Craig Topper [Mon, 18 Sep 2017 04:40:58 +0000 (04:40 +0000)]
[X86] Teach the execution domain fixing tables to use movlhps inplace of unpcklpd for the packed single domain.
MOVLHPS has a smaller encoding than UNPCKLPD in the legacy encodings. With VEX and EVEX encodings it doesn't matter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313509
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Craig Topper [Mon, 18 Sep 2017 03:29:54 +0000 (03:29 +0000)]
[X86] Teach execution domain fixing to convert between FP and int unpack instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313508
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Craig Topper [Mon, 18 Sep 2017 03:29:47 +0000 (03:29 +0000)]
[X86] Teach execution domain fixing to convert between VPERMILPS and VPSHUFD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313507
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Craig Topper [Mon, 18 Sep 2017 00:20:53 +0000 (00:20 +0000)]
[X86] Remove the X86ISD::MOVLHPD. Lowering doesn't use it and it's not a real instruction.
It was used in patterns, but we had the exact same patterns with Unpckl as well. So now just use Unpckl in the instruction patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313506
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Craig Topper [Sun, 17 Sep 2017 22:36:41 +0000 (22:36 +0000)]
[X86] Teach shuffle lowering to use MOVLHPS/MOVHLPS for lowering v4f32 unary shuffles with SSE1 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313504
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Craig Topper [Sun, 17 Sep 2017 22:36:39 +0000 (22:36 +0000)]
[X86] Add a couple more unary shuffles to the sse1 shuffle test.
These can be implemented with movlhps and movhlps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313503
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Craig Topper [Sun, 17 Sep 2017 18:59:32 +0000 (18:59 +0000)]
[X86] Synchronize a pattern between SSE1 and AVX/AVX512.
For some reason the SSE1 pattern expected a X86Movlhps pattern to have a v4f32 type, but AVX and AVX512 expected it to have a v4i32 type.
I'm not even sure this pattern is even reachable post SSE1, but I'm starting with fixing this obvious bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313495
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Craig Topper [Sun, 17 Sep 2017 18:59:30 +0000 (18:59 +0000)]
[X86] Colocate all of the X86VBroadcast patterns for v2i64 and v2f64. NFC
The memory patterns were near the MOVDDUP definition, but the non-memory patterns were near the broadcast instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313494
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Craig Topper [Sun, 17 Sep 2017 18:59:28 +0000 (18:59 +0000)]
[X86] Remove patterns for X86Movddup with v4i64 type. Lowering doesn't emit these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313493
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Craig Topper [Sun, 17 Sep 2017 18:59:26 +0000 (18:59 +0000)]
[X86] Remove isel patterns for X86Movhlps and X86Movlhps with integer types. Lowering doesn't emit these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313492
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Craig Topper [Sun, 17 Sep 2017 18:59:24 +0000 (18:59 +0000)]
[X86] Remove isel patterns for movlpd/movlps with integer types. Lowering doesn't emit these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313491
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Jatin Bhateja [Sun, 17 Sep 2017 18:16:26 +0000 (18:16 +0000)]
Adding test cases for PR34629 & PR34634.
Differential Revision: https://reviews.llvm.org/D37962
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313490
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Johan Engelen [Sun, 17 Sep 2017 18:11:26 +0000 (18:11 +0000)]
Revert "[ThinLTO] Avoid archive member collisions with old API"
This reverts commit r313488, because it breaks compilation on Android and breaks llvm-lto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313489
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Johan Engelen [Sun, 17 Sep 2017 17:38:26 +0000 (17:38 +0000)]
[ThinLTO] Avoid archive member collisions with old API
Summary:
ld64 on OSX uses the old ThinLTOCodegenerator API. When two modules have the same name in an archive (valid archive), a name collision happens for the modules' buffer identifiers.
This PR resolves this, by suffixing the module name with an increasing number such that the identifiers are guaranteed to be unique.
For a similar fix in LLD, see https://reviews.llvm.org/D25495
Reviewers: mehdi_amini, tejohnson
Reviewed By: mehdi_amini
Subscribers: inglorion, eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D37961
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313488
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Alex Bradbury [Sun, 17 Sep 2017 14:36:28 +0000 (14:36 +0000)]
[RISCV] Add support for disassembly
This Disassembly support allows for 'round-trip' testing, and rv32i-valid.s
has been updated appropriately.
Differential Revision: https://reviews.llvm.org/D23567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313486
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Alex Bradbury [Sun, 17 Sep 2017 14:27:35 +0000 (14:27 +0000)]
[RISCV] Add support for all RV32I instructions
This patch supports all RV32I instructions as described in the RISC-V manual.
A future patch will add support for pseudoinstructions and other instruction
expansions (e.g. 0-arg fence -> fence iorw, iorw).
Differential Revision: https://reviews.llvm.org/D23566
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313485
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Igor Breger [Sun, 17 Sep 2017 14:02:19 +0000 (14:02 +0000)]
[GlobalISel][X86] refactoring X86InstructionSelector.cpp .NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313484
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Igor Breger [Sun, 17 Sep 2017 11:34:17 +0000 (11:34 +0000)]
[GlobalISel][X86] Legalize i1 G_ADD/G_SUB/G_MUL/G_XOR/G_OR/G_AND instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313483
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Benjamin Kramer [Sun, 17 Sep 2017 11:19:53 +0000 (11:19 +0000)]
Remove uses of deprecated std::not1.
Lambdas are slightly more verbose, but also more readable. No
functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313482
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Benjamin Kramer [Sun, 17 Sep 2017 11:12:57 +0000 (11:12 +0000)]
Remove uses of deprecated std::pointer_to_unary_function.
It's removed in C++17. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313481
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Igor Breger [Sun, 17 Sep 2017 08:30:42 +0000 (08:30 +0000)]
[GlobalISel][X86] Use correct physical register in mir tests.NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313479
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Igor Breger [Sun, 17 Sep 2017 08:08:13 +0000 (08:08 +0000)]
[GlobalISel][X86] G_FCONSTANT support.
Summary: G_FCONSTANT support, port the implementation from X86FastIsel.
Reviewers: zvi, delena, guyblank
Reviewed By: delena
Subscribers: rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D37734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313478
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Craig Topper [Sun, 17 Sep 2017 06:09:32 +0000 (06:09 +0000)]
[X86] Remove integer X86ISD::SHUFP patterns. Lowering doesn't emit these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313477
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Craig Topper [Sun, 17 Sep 2017 05:06:05 +0000 (05:06 +0000)]
[X86] Add patterns to make blends with immediate control commutable during isel for load folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313476
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Craig Topper [Sun, 17 Sep 2017 05:06:03 +0000 (05:06 +0000)]
[X86] Remove some unused defaults from some multiclass parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313475
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Lang Hames [Sun, 17 Sep 2017 03:25:03 +0000 (03:25 +0000)]
[ORC] Hook up the LLVMOrcAddObjectFile function in the Orc C Bindings.
This can be used to add a relocatable object to the JIT session.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313474
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Don Hinton [Sun, 17 Sep 2017 00:24:43 +0000 (00:24 +0000)]
[ORC][Kaleidoscope] Update ORCJit tutorial.
Summary: Fix a few typos and update names to match current source.
Differential Revision: https://reviews.llvm.org/D37948
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313473
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Craig Topper [Sat, 16 Sep 2017 23:18:50 +0000 (23:18 +0000)]
[X86] Make PLCMULQDQ instructions commutable during isel to fold loads.
This adds new patterns and SDNodeXForm to enable the immediate to commuted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313472
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Craig Topper [Sat, 16 Sep 2017 23:18:48 +0000 (23:18 +0000)]
[X86] Add NoAVX predicates to the patterns for the legacy encoded PCLMUL and AES instructions.
Previously we were just relying on pattern order to define precedence. Which works, but isn't the best way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313471
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Zachary Turner [Sat, 16 Sep 2017 19:20:53 +0000 (19:20 +0000)]
Try to fix some failing bots.
It doesn't make sense to me why these bots are failing as the
traceback does not agree with the source code. It's possible
something is stale or there is some other mysterious error,
but in any case hopefully this fixes it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313469
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Zachary Turner [Sat, 16 Sep 2017 19:01:04 +0000 (19:01 +0000)]
[llvm-symbolizer] Fix coff-dwarf.test
This was a bug in the test that was only exposed as a result of
refactoring some code in lit configuration files. Previously,
llvm's lit configuration would only set the target-windows feature
if the system was also windows. Since cross-compilation is
a thing, this isn't correct. target-windows should be set
independently of system-windows.
Adding to that bug, this particular test then checked for
target-windows when it really meant "can I call a certain API on
the host machine", which is what system-windows is for.
Ultimately, this test only works if *both* the target and host
are Windows, so I've updated the test to reflect that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313468
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Zachary Turner [Sat, 16 Sep 2017 18:46:21 +0000 (18:46 +0000)]
Resubmit "Add a shared llvm.lit module that all test suites can use."
There were some issues surrounding Py2 / Py3 compatibility, but
I've now tested with both Py2 and Py3 and everything seems to
work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313467
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Zachary Turner [Sat, 16 Sep 2017 18:45:44 +0000 (18:45 +0000)]
[lit] Fix some Python 3 compatibility issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313466
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Craig Topper [Sat, 16 Sep 2017 17:51:55 +0000 (17:51 +0000)]
[X86] Remove some extra code that snuck into r313450.
The same code appears earlier in the function. This represents an earlier version of what became r313373 that I still had sitting in my local repo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313465
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Adrian Prantl [Sat, 16 Sep 2017 17:28:00 +0000 (17:28 +0000)]
llvm-dwarfdump: support a --show-children option
This will print all children of a DIE when selectively printing only
one DIE at a given offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313464
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Adrian Prantl [Sat, 16 Sep 2017 16:58:18 +0000 (16:58 +0000)]
llvm-dwarfdump: Add support for -debug-types=<offset>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313463
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Zachary Turner [Sat, 16 Sep 2017 15:48:30 +0000 (15:48 +0000)]
[lit] Fix the lit unit tests.
A few tests were manually constructing a LitConfig object, since
I added a new argument to it this was triggering some failures
I didn't detect. `ninja check-lit` passes now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313461
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Zachary Turner [Sat, 16 Sep 2017 15:31:34 +0000 (15:31 +0000)]
[lit] Add a single process mode.
This is helpful for debugging test failures since it removes
the multiprocessing pool from the picture. This will obviously
slow down the test suite by a few orders of magnitude, so it
should only be used for debugging specific failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313460
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George Rimar [Sat, 16 Sep 2017 14:29:51 +0000 (14:29 +0000)]
[llvm-readobj] - Teach tool to report error if some section is in multiple COMDAT groups at once.
readelf tool reports an error when output contains the same section
in multiple COMDAT groups. That can be useful.
Path teaches llvm-readobj to do the same.
Differential revision: https://reviews.llvm.org/D37567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313459
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Sanjay Patel [Sat, 16 Sep 2017 13:29:12 +0000 (13:29 +0000)]
[x86] enable storeOfVectorConstantIsCheap() target hook
This allows vector-sized store merging of constants in DAGCombiner using the existing code in MergeConsecutiveStores().
All of the twisted logic that decides exactly what vector operations are legal and fast for each particular CPU are
handled separately in there using the appropriate hooks.
For the motivating tests in merge-store-constants.ll, we already produce the same vector code in IR via the SLP vectorizer.
So this is just providing a backend backstop for code that doesn't go through that pass (-O1). More details in PR24449:
https://bugs.llvm.org/show_bug.cgi?id=24449 (this change should be the last step to resolve that bug)
Differential Revision: https://reviews.llvm.org/D37451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313458
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NAKAMURA Takumi [Sat, 16 Sep 2017 12:13:03 +0000 (12:13 +0000)]
Reformat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313457
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NAKAMURA Takumi [Sat, 16 Sep 2017 12:13:00 +0000 (12:13 +0000)]
llvm/IR/DiagnosticHandler.h: Add include guard, or -fmodules would be confused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313456
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Craig Topper [Sat, 16 Sep 2017 09:16:48 +0000 (09:16 +0000)]
[X86] Add isel patterns to be able to fold loads into VPERM2F128 even when the load is on the first input to the SDNode.
We just need to toggle bits 1 and 5 of the immediate and swap the sources. The peephole pass could trigger commuting/folding for this later, but its easy enough to fix in isel.
Disable the peephole pass on the main vperm2x128 test so we know we're doing this through isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313455
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Craig Topper [Sat, 16 Sep 2017 09:16:46 +0000 (09:16 +0000)]
[X86] Remove unused check lines that got left behind when I moved tests to the instrinsic upgrade file and regenerated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313454
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Craig Topper [Sat, 16 Sep 2017 08:15:52 +0000 (08:15 +0000)]
[X86] Remove VPERM2X128 isel patterns with 32-bit elements.
Now that the intrinsics are gone we only need 64-bit elements since that's what shuffle lowering uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313453
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Craig Topper [Sat, 16 Sep 2017 07:51:01 +0000 (07:51 +0000)]
[X86] Remove the vperm2f128 test file I just added in r313450.
I missed the we already had a pretty thorough test file for these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313451
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Craig Topper [Sat, 16 Sep 2017 07:36:14 +0000 (07:36 +0000)]
[X86] Remove VPERM2F128/VPERM2I128 intrinsics and autoupgrade to native shuffles.
I've moved the test cases from the InstCombine optimizations to the backend to keep the coverage we had there. It covered every possible immediate so I've preserved the resulting shuffle mask for each of those immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313450
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Craig Topper [Sat, 16 Sep 2017 07:13:39 +0000 (07:13 +0000)]
[X86] Fix some FileCheck lines that use the wrong prefix.
Assume they were moved during autoupgrading and not changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313448
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Chandler Carruth [Sat, 16 Sep 2017 02:13:35 +0000 (02:13 +0000)]
[git] Update the llvm git helper script to work correctly with the
latest Python versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313435
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Craig Topper [Sat, 16 Sep 2017 02:11:21 +0000 (02:11 +0000)]
[X86] Don't set reserved bits in the immediate in the test cases for vperm2f128.
I'm going to autoupgrade these intrinsics in a future commit. This bit will never be set in the resulting output so pre-removing the bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313434
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Craig Topper [Sat, 16 Sep 2017 01:43:21 +0000 (01:43 +0000)]
[X86] Remove slash in front of a CHECK line in a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313433
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Eric Beckmann [Sat, 16 Sep 2017 01:14:36 +0000 (01:14 +0000)]
Revert "Fix Bug 30978 by emitting cv file checksums."
This reverts commit
6389e7aa724ea7671d096f4770f016c3d86b0d54.
There is a bug in this implementation where the string value of the
checksum is outputted, instead of the actual hex bytes. Therefore the
checksum is incorrect, and this prevent pdbs from being loaded by visual
studio. Revert this until the checksum is emitted correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313431
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Zachary Turner [Sat, 16 Sep 2017 00:52:49 +0000 (00:52 +0000)]
Revert lit changes related to lit.llvm module.
It looks like this is going to be non-trivial to get working
in both Py2 and Py3, so for now I'm reverting until I have time
to fully test it under Python 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313429
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Zachary Turner [Sat, 16 Sep 2017 00:43:16 +0000 (00:43 +0000)]
[lit] Fix another Python 3 error.
Apparently we have a buildbot running Python 3. This is going
to be fun :-/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313428
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Zachary Turner [Sat, 16 Sep 2017 00:38:20 +0000 (00:38 +0000)]
[lit] Better check for integral value.
Some versions of python don't have 'long'. Use numbers.Number
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313427
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Zachary Turner [Sat, 16 Sep 2017 00:25:58 +0000 (00:25 +0000)]
Resubmit "[lit] Add a lit.llvm module that all llvm projects can use"
This was reverted alongside the revert of the lit/llvm-lit refactor,
but now that that has re-landed, I'm relanding this as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313426
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Craig Topper [Fri, 15 Sep 2017 23:53:43 +0000 (23:53 +0000)]
[X86] Remove usages of vperm2f intrinsics from fast isel tests to match what clang generates after r313418.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313424
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Vedant Kumar [Fri, 15 Sep 2017 23:14:22 +0000 (23:14 +0000)]
[llvm-cov] Fix a bot failure due to r313417
There's a type mismatch issue with the arguments to a call to std::min
introduced in r313417.
http://lab.llvm.org:8011/builders/clang-cmake-thumbv7-a15/builds/11174
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313422
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Craig Topper [Fri, 15 Sep 2017 23:05:51 +0000 (23:05 +0000)]
[X86] Remove GCCBuiltin names from perm2f128/perm2i128 intrinsics so we can provide a custom implementation in clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313420
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Adrian Prantl [Fri, 15 Sep 2017 23:04:04 +0000 (23:04 +0000)]
llvm-dwarfdump: Add support for -debug-info=<offset>.
This is the first of many commits that enable selectively dumping just
one record from the debug info.
This reapplies r313412 with some extra qualification to appease GCC and MSVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313419
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Vedant Kumar [Fri, 15 Sep 2017 23:00:02 +0000 (23:00 +0000)]
[llvm-cov] Avoid over-counting covered lines and regions
* Fix an unsigned integer overflow in the logic that computes the
number of uncovered lines in a function.
* When aggregating region and line coverage summaries, take into account
that different instantiations may have a different number of regions.
The new test case provides test coverage for both bugs. I also verified
this change by preparing a coverage report for a stage2 build of llc --
the new assertions should detect any outstanding over-counting bugs.
Fixes PR34613.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313417
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Vedant Kumar [Fri, 15 Sep 2017 23:00:01 +0000 (23:00 +0000)]
[llvm-cov] Make some summary info fields private. NFC.
There's a bug in the way the line and region summary objects are merged.
It would have been less likely to occur if those objects kept some data
private.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313416
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Vedant Kumar [Fri, 15 Sep 2017 23:00:00 +0000 (23:00 +0000)]
[llvm-cov] Remove a redundant field. NFC.
The "NotCovered" fields in the region and line summary structs are
redundant. We should remove them to make the code clearer.
As a follow-up, the "NotCovered" entries should be removed from the
reports as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313415
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Adrian Prantl [Fri, 15 Sep 2017 22:47:16 +0000 (22:47 +0000)]
Revert "llvm-dwarfdump: Add support for -debug-info=<offset>."
This reverts commit r313412 because of a g++ incompatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313413
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Adrian Prantl [Fri, 15 Sep 2017 22:37:56 +0000 (22:37 +0000)]
llvm-dwarfdump: Add support for -debug-info=<offset>.
This is the first of many commits that enable selectively dumping just
one record from the debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313412
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Guozhi Wei [Fri, 15 Sep 2017 22:28:12 +0000 (22:28 +0000)]
[TargetTransformInfo] Static alloca has 0 cost
Static alloca usually doesn't generate any machine instructions, so it has 0 cost.
Differential Revision: https://reviews.llvm.org/D37879
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313410
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Chandler Carruth [Fri, 15 Sep 2017 22:23:27 +0000 (22:23 +0000)]
[SLP] Revert r312791 and other necessary commits, except for TTI and
CostModel.
The original patch added support for horizontal min/max reductions to
the SLP vectorizer.
This patch causes LLVM to miscompile fairly simple signed min
reductions. I have attached a test progrom to http://llvm.org/PR34635
that shows the behavior change after this patch. We found this in a test
for the open source Eigen library, but also in other code.
Unfortunately, the revert is moderately challenging. It required
reverting:
r313042: [SLP] Test with multiple uses of conditional op and wrong parent.
r312853: [SLP] Fix buildbots, NFC.
r312793: [SLP] Fix the warning about paths not returning the value, NFC.
r312791: [SLP] Support for horizontal min/max reduction.
And even then, I had to completely skip reverting the changes to TTI and
CostModel because r312832 rewrote so much of this code. Plus, the cost
modeling changes aren implicated in the miscompile, so they should be
fine and will just not be used until this gets re-introduced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313409
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