OSDN Git Service
Craig Topper [Sun, 8 May 2016 07:10:54 +0000 (07:10 +0000)]
[X86] Lower 256-bit vector all-zero constants to v8i32 even with AVX1 only. Either way a 256-bit VXORPS will be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268873
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Craig Topper [Sun, 8 May 2016 07:10:50 +0000 (07:10 +0000)]
[X86] Add patterns for 256-bit non-temporal stores when only AVX1 is supported. While there, add a predicate to the SSE2 patterns to avoid an ordering dependency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268872
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Craig Topper [Sun, 8 May 2016 07:10:47 +0000 (07:10 +0000)]
[X86] No need to avoid selecting AVX_SET0 for 256-bit integer types when only AVX1 is supported. AVX_SET0 just expands to 256-bit VXORPS which is legal in AVX1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268871
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Weiming Zhao [Sun, 8 May 2016 05:11:54 +0000 (05:11 +0000)]
[ARM] Fix Scavenger assert due to underestimated stack size
(re-apply r268810 as it exposed an uninitialized variable in ARM MFI.
Patch 268868 should fix that.)
Summary:
Currently, when checking if a stack is "BigStack" or not, it doesn't count into spills and arguments. Therefore, LLVM won't reserve spill slot for this actually "BigStack". This may cause scavenger failure.
Reviewers: rengolin
Subscribers: vitalybuka, aemerson, rengolin, tberghammer, danalbert, srhines, llvm-commits
Differential Revision: http://reviews.llvm.org/D19896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268869
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Weiming Zhao [Sun, 8 May 2016 05:04:47 +0000 (05:04 +0000)]
Fix use-of-uninitialized-value of ARMMachineFunctionInfo
Summary: Explicitly initialize ArgumentStackSize to prevent the msan failure.
Reviewers: rengolin
Subscribers: aemerson, rengolin, llvm-commits
Differential Revision: http://reviews.llvm.org/D20051
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268868
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Simon Pilgrim [Sat, 7 May 2016 20:19:59 +0000 (20:19 +0000)]
Fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268867
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Simon Pilgrim [Sat, 7 May 2016 20:12:36 +0000 (20:12 +0000)]
[SelectionDAG] Added bitreverse(bitreverse(v)) --> v
Added bitreverse creation testing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268865
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Craig Topper [Sat, 7 May 2016 19:25:56 +0000 (19:25 +0000)]
[X86] Fix InstAliases to not allow FARCALL32i/FARCALL16i/FARJMP32i/FARJMP16i in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268863
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Simon Pilgrim [Sat, 7 May 2016 19:04:00 +0000 (19:04 +0000)]
[X86] Added BITREVERSE constant folding and identity tests
Identity tests are currently failing - this will be fixed soon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268862
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Simon Pilgrim [Sat, 7 May 2016 18:04:24 +0000 (18:04 +0000)]
[X86] Pulled out duplicate mask width calculation. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268861
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Simon Pilgrim [Sat, 7 May 2016 16:34:16 +0000 (16:34 +0000)]
[CostModel][X86] Split BSWAP/BITREVERSE cost tests from CTPOP/CTLZ/CTTZ 'bit count' cost tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268859
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Sanjay Patel [Sat, 7 May 2016 15:03:40 +0000 (15:03 +0000)]
[x86, BMI] add TLI hook for 'andn' and use it to simplify comparisons
For the sake of minimalism, this patch is x86 only, but I think that at least
PPC, ARM, AArch64, and Sparc probably want to do this too.
We might want to generalize the hook and pattern recognition for a target like
PPC that has a full assortment of negated logic ops (orc, nand).
Note that http://reviews.llvm.org/D18842 will cause this transform to trigger
more often.
For reference, this relates to:
https://llvm.org/bugs/show_bug.cgi?id=27105
https://llvm.org/bugs/show_bug.cgi?id=27202
https://llvm.org/bugs/show_bug.cgi?id=27203
https://llvm.org/bugs/show_bug.cgi?id=27328
Differential Revision: http://reviews.llvm.org/D19087
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268858
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NAKAMURA Takumi [Sat, 7 May 2016 08:43:11 +0000 (08:43 +0000)]
ErrorInfoBase::message(): Don't use raw_string_ostream's buffer, Msg, before closing. Use raw_string_ostream::str() to flush the buffer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268856
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Xinliang David Li [Sat, 7 May 2016 05:39:12 +0000 (05:39 +0000)]
[PM] code refactoring -- preparation for new PM porting /NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268851
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Mehdi Amini [Sat, 7 May 2016 05:07:47 +0000 (05:07 +0000)]
Fix stripDebugInfo: was modifying "DebugLoc" attached to the intrinsic after deleting it.
Fix MSAN build.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268849
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NAKAMURA Takumi [Sat, 7 May 2016 04:51:51 +0000 (04:51 +0000)]
MipsELFObjectWriter.cpp: Activate debug printer just for +Asserts. [-Wunused-function]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268848
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Mehdi Amini [Sat, 7 May 2016 04:10:52 +0000 (04:10 +0000)]
Refactor stripDebugInfo(Function) to handle intrinsic
This moves the code that handles stripping debug info intrinsic from
StripDebugInfo(Module) to StripDebugInfo(Function). The latter is
already walking every instructions so it makes sense to do it at the
same time.
This makes also stripDebugInfo(Function) as an API more useful: it
is really dropping every debug info in the Function.
Finally the existing code is trigerring an assertion when the Module
is not fully materialized.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268847
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Lang Hames [Sat, 7 May 2016 03:48:56 +0000 (03:48 +0000)]
[Orc] Fix missing rename from r268845.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268846
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Lang Hames [Sat, 7 May 2016 03:36:38 +0000 (03:36 +0000)]
[Orc] Rename OrcArchitectureSupport to OrcABISupport and add Win32 ABI support.
This enables lazy JITing on Windows x86-64.
Patch by David. Thanks David!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268845
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Vitaly Buka [Sat, 7 May 2016 02:10:59 +0000 (02:10 +0000)]
Revert r268832 "Refactor stripDebugInfo(Function) to handle intrinsic"
It breaks many bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268837
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Sanjoy Das [Sat, 7 May 2016 02:08:24 +0000 (02:08 +0000)]
[ValueTracking] Hoist some computation out of a loop; NFC
There is no need to match the comparison instruction repeatedly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268836
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Sanjoy Das [Sat, 7 May 2016 02:08:22 +0000 (02:08 +0000)]
Clean up comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268835
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Sanjoy Das [Sat, 7 May 2016 02:08:15 +0000 (02:08 +0000)]
Delete trailing whitespace; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268834
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Vitaly Buka [Sat, 7 May 2016 01:54:00 +0000 (01:54 +0000)]
Revert r268810 becase it brakes msan bot.
16802==WARNING: MemorySanitizer: use-of-uninitialized-value
lib/Target/ARM/ARMFrameLowering.cpp:1632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268833
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Mehdi Amini [Sat, 7 May 2016 01:42:36 +0000 (01:42 +0000)]
Refactor stripDebugInfo(Function) to handle intrinsic
This moves the code that handles stripping debug info intrinsic from
StripDebugInfo(Module) to StripDebugInfo(Function). The latter is
already walking every instructions so it makes sense to do it at the
same time.
This makes also stripDebugInfo(Function) as an API more useful: it
is really dropping every debug info in the Function.
Finally the existing code is trigerring an assertion when the Module
is not fully materialized.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268832
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Ahmed Bougacha [Sat, 7 May 2016 01:11:17 +0000 (01:11 +0000)]
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr.
This re-applies r268760, reverted in r268794.
Fixes http://llvm.org/PR27670
The original imp-defs assertion was way overzealous: forward all
implicit operands, except imp-defs of the new super-reg def (r268787
for GR64, but also possible for GR16->GR32), or imp-uses of the new
super-reg use.
While there, mark the source use as Undef, and add an imp-use of the
old source reg: that should cover any case of dead super-regs.
At the stage the pass runs, flags are unlikely to matter anyway;
still, let's be as correct as possible.
Also add MIR tests for the various interesting cases.
Original commit message:
Codesize is less (16) or equal (8), and we avoid partial
dependencies.
Differential Revision: http://reviews.llvm.org/D19999
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268831
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Ahmed Bougacha [Sat, 7 May 2016 01:11:10 +0000 (01:11 +0000)]
[X86] Register and initialize the FixupBW pass.
That lets us use it in MIR tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268830
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Kostya Serebryany [Fri, 6 May 2016 23:51:28 +0000 (23:51 +0000)]
[libFuzzer] modify the docs for startup/init
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268824
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Kostya Serebryany [Fri, 6 May 2016 23:41:11 +0000 (23:41 +0000)]
[libFuzzer] tweak the documentation about rss_limit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268822
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Kostya Serebryany [Fri, 6 May 2016 23:38:07 +0000 (23:38 +0000)]
[libFuzzer] enhance -rss_limit_mb and enable by default. Now it will print the OOM reproducer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268821
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Rong Xu [Fri, 6 May 2016 23:20:58 +0000 (23:20 +0000)]
[PGO] Use rsplit to parse value-data line in text profile file.
The value-data line is <PGOFuncName>:<Count_Value>. PGOFuncName might contain
':' for the internal linkage functions. We therefore need to use rsplit,
rather split, to extract the data from the line. This fixes the error when
merging a text profile file to an indexed profile file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268818
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Adrian Prantl [Fri, 6 May 2016 22:53:06 +0000 (22:53 +0000)]
Implement a safer bitcode upgrade for DISubprogram.
The bitcode upgrade I added for DISubprogram in r266446 was based on the
assumption that the CU node for the subprogram was already materialized by the
time the DISubprogram is visited. This assumption may not hold true as future
versions of LLVM may decide to write out bitcode in a different order. This
patch corrects this by introducing a versioning bit next to the distinct flag to
unambiguously differentiate the new from the old record layouts.
Note for people stabilizing LLVM out-of-tree: This patch introduces a bitcode
incompatibility with llvm trunk revisions from r266446 — this commit. (But
D19987 will ensure that it degrades gracefully).
http://reviews.llvm.org/D20004
rdar://problem/
26074194
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268816
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Matthias Braun [Fri, 6 May 2016 22:43:50 +0000 (22:43 +0000)]
DetectDeadLanes: Increase precision when detecting undef inputs
In case of COPY-like instruction we may be able to deduce that a certain
input is unused, based on the used lanes of the register defined by the
instruction.
This even works accross otherwise incompatible copies (no need to have
compatible lanemasks, completely unused operands are still completely
unused). It even makes sense to redo the analysis in this case since we
gained information for a case we previously stopped at because of the
incompatible masks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268815
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Matthias Braun [Fri, 6 May 2016 22:43:46 +0000 (22:43 +0000)]
DetectDeadLanes: Cleanup, assert on some impossible cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268814
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Zachary Turner [Fri, 6 May 2016 22:29:34 +0000 (22:29 +0000)]
Drop error when trying to fallback from PDB to DWARF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268813
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Justin Bogner [Fri, 6 May 2016 22:22:25 +0000 (22:22 +0000)]
cmake: Avoid continue, apparently that's new
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268812
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Simon Pilgrim [Fri, 6 May 2016 22:22:18 +0000 (22:22 +0000)]
[SLPVectorizer][X86] Regenerated SEXT/ZEXT cast vectorization tests
Added 256-bit vector test as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268811
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Weiming Zhao [Fri, 6 May 2016 22:20:13 +0000 (22:20 +0000)]
[ARM] Fix Scavenger assert due to underestimated stack size
(this is resubmit of r268529 with minor refactoring. r268529 was reverted
at r268536 due a memory sanitizer failure. I have not been able to
reproduce that failure and I checked all the variable used in my change
but I could not spot an issue. I did some refactoring and see if it will
give a clearer hint)
Summary:
Currently, when checking if a stack is "BigStack" or not, it doesn't count into spills and arguments. Therefore, LLVM won't reserve spill slot for this actually "BigStack". This may cause scavenger failure.
Reviewers: rengolin
Subscribers: vitalybuka, aemerson, rengolin, tberghammer, danalbert, srhines, llvm-commits
Differential Revision: http://reviews.llvm.org/D19896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268810
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Philip Reames [Fri, 6 May 2016 22:17:01 +0000 (22:17 +0000)]
Reapply 267210 with fix for PR27490
Original Commit Message
Extend load/store type canonicalization to handle unordered operations
Extend the type canonicalization logic to work for unordered atomic loads and stores. Note that while this change itself is fairly simple and low risk, there's a reasonable chance this will expose problems in the backends by suddenly generating IR they wouldn't have seen before. Anything of this nature will be an existing bug in the backend (you could write an atomic float load), but this will definitely change the frequency with which such cases are encountered. If you see problems, feel free to revert this change, but please make sure you collect a test case.
Note that the concern about lowering is now much less likely. PR27490 proved that we already *were* mucking with the types of ordered atomics and volatiles. As a result, this change doesn't introduce as much new behavior as originally thought.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268809
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Zachary Turner [Fri, 6 May 2016 22:15:42 +0000 (22:15 +0000)]
Make llvm-pdbdump print CV type records
This reuses the CVTypeDumper from libcodeview to dump full
information about type records within a PDB file.
Differential Revision: http://reviews.llvm.org/D20022
Reviewed By: rnk
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268808
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Kostya Serebryany [Fri, 6 May 2016 21:58:35 +0000 (21:58 +0000)]
[libFuzzer] add exeprimental -rss_limit_mb flag to fight against OOMs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268807
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Justin Bogner [Fri, 6 May 2016 21:57:30 +0000 (21:57 +0000)]
CMake: generate check targets for lit suites without their own lit.cfgs
Currently our cmake generates targets like check-llvm-unit and
check-llvm-transforms-loopunroll-x86, but not check-llvm-transforms or
check-llvm-transforms-adce. This is because the search for test suites
only lists the ones with a custom lit.cfg or lit.local.cfg.
Instead, we can do something a little smarter - any directory under
test that isn't called Inputs or inside a directory called Inputs is a
test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268806
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Matthias Braun [Fri, 6 May 2016 21:47:41 +0000 (21:47 +0000)]
LiveIntervalAnalysis: Fix handleMove() extending liverange for undef inputs
Fix handleMove() incorrectly extending liveranges when an undef input of
a vreg was moved past the (current) end of the liverange.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268805
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Philip Reames [Fri, 6 May 2016 21:43:51 +0000 (21:43 +0000)]
[GVN] PRE of unordered loads
Again, fairly simple. Only change is ensuring that we actually copy the property of the load correctly. The aliasing legality constraints were already handled by the FRE patches. There's nothing special about unorder atomics from the perspective of the PRE algorithm itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268804
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Simon Pilgrim [Fri, 6 May 2016 21:41:55 +0000 (21:41 +0000)]
[SLPVectorizer][X86] Added BSWAP/BITREVERSE vectorization tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268803
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Simon Pilgrim [Fri, 6 May 2016 21:33:01 +0000 (21:33 +0000)]
[SLPVectorizer][X86] Added CTPOP/CTLZ/CTTZ vectorization tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268800
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Quentin Colombet [Fri, 6 May 2016 21:21:50 +0000 (21:21 +0000)]
Revert "[X86] Add a new LOW32_ADDR_ACCESS_RBP register class."
This reverts commit r268796.
I believe it breaks test/CodeGen/X86/asm-mismatched-types.ll with:
Cannot emit physreg copy instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268799
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Zachary Turner [Fri, 6 May 2016 21:19:29 +0000 (21:19 +0000)]
Fix failing test due to merge conflict.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268798
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Quentin Colombet [Fri, 6 May 2016 21:10:53 +0000 (21:10 +0000)]
[X86] Add a new LOW32_ADDR_ACCESS_RBP register class.
ABIs like NaCl uses 32-bit addresses but have 64-bit frame.
The new register class reflects those constraints when choosing a
register class for a address access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268796
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Quentin Colombet [Fri, 6 May 2016 21:10:43 +0000 (21:10 +0000)]
[X86] Rename the X32_ADDR_ACCESS register class into LOW32_ADDR_ACCESS.
This register class may be used by any ABIs that uses x86_64 ISA while
using 32-bit addresses, not just in X32 cases. Make sure the name
reflects that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268795
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Nico Weber [Fri, 6 May 2016 21:07:02 +0000 (21:07 +0000)]
Revert r268760, it caused PR27670.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268794
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Zachary Turner [Fri, 6 May 2016 20:59:35 +0000 (20:59 +0000)]
Add missing include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268792
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Zachary Turner [Fri, 6 May 2016 20:51:57 +0000 (20:51 +0000)]
Port DebugInfoPDB over to using llvm::Error.
Differential Revision: http://reviews.llvm.org/D19940
Reviewed By: rnk
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268791
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Sanjoy Das [Fri, 6 May 2016 20:39:33 +0000 (20:39 +0000)]
[RS4GC] Fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268790
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Kevin Enderby [Fri, 6 May 2016 20:16:28 +0000 (20:16 +0000)]
Change GenericBinaryError to no longer include a FileName, which is then not
part of the error message.
As the caller is the one that needs to add the name of where the "object file"
comes from to the error message as the object file could be in an archive, or
coming from a slice of a Mach-O universal file or a buffer created by a JIT.
In the cases of a Mach-O universal file the architecture name may or may not
also need to be printed which is up to the tool code. For example if the tool
code is only selecting the host architecture slice then that architecture name
is never printed.
This patch is the change to the libObject code and there will be follow on
commits for changes to the code for each tool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268789
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Kostya Serebryany [Fri, 6 May 2016 20:14:48 +0000 (20:14 +0000)]
[libFuzzer] more trophies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268788
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Ahmed Bougacha [Fri, 6 May 2016 20:03:03 +0000 (20:03 +0000)]
[X86] Accept imp-defs of GR64 super-registers in FixupBW MOVrr.
Testcase will follow shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268787
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Marcin Koscielnicki [Fri, 6 May 2016 19:36:56 +0000 (19:36 +0000)]
[MSan] [X86] Fix vararg helper for fixed arguments in overflow area.
This fixes http://llvm.org/PR27646 on x86_64.
Differential Revision: http://reviews.llvm.org/D19997
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268783
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Artem Tamazov [Fri, 6 May 2016 19:32:38 +0000 (19:32 +0000)]
[AMDGPU][llvm-mc] Some refactoring of .td files
Some custom Operands and AsmOperandClasses moved to proper place.
No functional changes.
Differential Revision: http://reviews.llvm.org/D20012
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268780
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Adrian Prantl [Fri, 6 May 2016 19:26:47 +0000 (19:26 +0000)]
Refactor the Verifier so it can diagnose IR validation errors and debug
info metadata errors separately. (NFC)
This patch refactors the Verifier so it can diagnose IR validation errors
and debug info metadata errors separately.
The motivation behind this change is that broken (or outdated) debug info
can be "recovered" from by stripping the debug info.
The problem I'm trying to solve with this sequence of patches is that
historically we've done a really bad job at verifying debug info.
We want to be able to make the verifier stricter without having to worry
about breaking bitcode compatibility with existing producers. For example,
we don't necessarily want IR produced by an older version of clang to be
rejected by an LTO link just because of malformed debug info, and rather
provide an option to strip it. Note that merely outdated (but well-formed)
debug info would continue to be auto-upgraded in this scenario.
http://reviews.llvm.org/D19986
rdar://problem/
25818489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268778
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Krzysztof Parzyszek [Fri, 6 May 2016 19:13:38 +0000 (19:13 +0000)]
[Hexagon] Be careful about anti-dependencies with a call in packetizer
In a case like
J2_callr <ga:@foo>, %R0<imp-use>, ...
R0<def> = ...
the anti-dependency on R0 cannot be ignored and the two instructions
cannot be packetized together, since if they were, the assignment to
R0 would take place before the call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268776
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Philip Reames [Fri, 6 May 2016 18:46:45 +0000 (18:46 +0000)]
[GVN] Handle unordered atomics in cross block FRE
You'll note there are essentially no code changes here. Cross block FRE heavily reuses code from the block local FRE. All of the tricky parts were done as part of the previous patch and the refactoring that removed the original code duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268775
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Justin Bogner [Fri, 6 May 2016 18:42:16 +0000 (18:42 +0000)]
SDAG: Don't leave dangling dead nodes after SelectCodeCommon
Relying on the caller to clean up after we've replaced all uses of a
node won't work when we've migrated to the `void Select(...)` API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268774
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Eric Christopher [Fri, 6 May 2016 18:23:14 +0000 (18:23 +0000)]
The associated PR for this test was PR27135 not PR27132.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268772
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Quentin Colombet [Fri, 6 May 2016 18:22:48 +0000 (18:22 +0000)]
[X86] Get rid of X32_NOREX_ADDR_ACCESS register class.
According to H.J. Lu <hjl.tools@gmail.com>, this register class is never
used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268771
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Philip Reames [Fri, 6 May 2016 18:17:13 +0000 (18:17 +0000)]
[GVN] Do local FRE for unordered atomic loads
This patch is the first in a small series teaching GVN to optimize unordered loads aggressively. This change just handles block local FRE because that's the simplest thing which lets me test MDA, and the AvailableValue pieces. Somewhat suprisingly, MDA appears fine and only a couple of small changes are needed in GVN.
Once this is in, I'll tackle non-local FRE and PRE. The former looks like a natural extension of this, the later will require a couple of minor changes.
Differential Revision: http://reviews.llvm.org/D19440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268770
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Mehdi Amini [Fri, 6 May 2016 18:17:03 +0000 (18:17 +0000)]
Tweak the ThinLTO pass pipeline
Summary:
The original ThinLTO pipeline was derived from some
work I did tuning FullLTO on the test suite and SPEC. This
patch reduces the amount of work done in the "linker phase" of
the build, and extend the function simplifications passes
performed during the "compile phase". This helps the build time
by reducing the IR as much as possible during the compile phase
and limiting the work to be performed during the "link phase",
while keeping the performance "on par" with the existing pipeline.
Reviewers: tejohnson
Subscribers: llvm-commits, joker.eph
Differential Revision: http://reviews.llvm.org/D19773
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268769
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Sanjay Patel [Fri, 6 May 2016 18:07:46 +0000 (18:07 +0000)]
[SimplifyCFG] propagate branch metadata when creating select (retry r268550 / r268751 with possible fix)
Retrying r268550/r268751 which were reverted at r268577/r268765 due a memory sanitizer failure.
I have not been able to reproduce that failure, but I've taken another guess at fixing
the problem in this version of the patch and will watch for another failure.
Original commit message:
Unlike earlier similar fixes, we need to recalculate the branch weights
in this case.
Differential Revision: http://reviews.llvm.org/D19674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268767
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Sanjay Patel [Fri, 6 May 2016 17:51:37 +0000 (17:51 +0000)]
revert r268751 - caused same failures on msan bot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268765
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Simon Pilgrim [Fri, 6 May 2016 17:50:07 +0000 (17:50 +0000)]
[CostModel][X86] Tweak 'SSE2-only' test CPU as it was only disabling SSE41 not SSE3/SSSE3 etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268763
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Artem Tamazov [Fri, 6 May 2016 17:48:48 +0000 (17:48 +0000)]
[AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.
Added support for sendmsg(MSG[, OP[, STREAM_ID]]) syntax
in s_sendmsg and s_sendmsghalt instructions.
The syntax matches the SP3 assembler/disassembler rules.
That is why implicit inputs (like M0 and EXEC) are not printed
to disassembly output anymore.
sendmsg(...) allows only known message types and attributes,
even if literals are used instead of symbolic names.
However, raw literal (without "sendmsg") still can be used,
and that allows for any 16-bit value.
Tests updated/added.
Differential Revision: http://reviews.llvm.org/D19596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268762
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Simon Pilgrim [Fri, 6 May 2016 17:48:35 +0000 (17:48 +0000)]
[CostModel][X86] Added ctlz/cttz undef-zero costmodel tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268761
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Ahmed Bougacha [Fri, 6 May 2016 17:42:57 +0000 (17:42 +0000)]
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr.
Codesize is less (16) or equal (8), and we avoid partial dependencies.
Differential Revision: http://reviews.llvm.org/D19999
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268760
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Ahmed Bougacha [Fri, 6 May 2016 17:28:47 +0000 (17:28 +0000)]
[X86] Remove \brief in FixupBW. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268754
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Ahmed Bougacha [Fri, 6 May 2016 17:28:42 +0000 (17:28 +0000)]
[X86] Simplify FixupBW sub_8bit_hi-related logic. NFC.
Instead of passing around sizes and asking for subregs, we can check
the subreg indices we care about: sub_8bit_hi and sub_8bit.
Differential Revision: http://reviews.llvm.org/D20006
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268753
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Geoff Berry [Fri, 6 May 2016 17:12:38 +0000 (17:12 +0000)]
[AArch64] Fix test to specify triple and disable post-RA scheduling.
This should fix bot breakage caused by r268746:
[AArch64] Combine callee-save and local stack SP adjustment instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268752
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Sanjay Patel [Fri, 6 May 2016 17:07:47 +0000 (17:07 +0000)]
[SimplifyCFG] propagate branch metadata when creating select (retry r268550 with possible fix)
Retrying r268550 which was reverted at r268577 due a memory sanitizer failure.
I have not been able to reproduce that failure, but I've taken a guess at fixing
the problem in this version of the patch and will watch for another failure.
Original commit message:
Unlike earlier similar fixes, we need to recalculate the branch weights
in this case.
Differential Revision: http://reviews.llvm.org/D19674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268751
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Geoff Berry [Fri, 6 May 2016 16:34:59 +0000 (16:34 +0000)]
[AArch64] Combine callee-save and local stack SP adjustment instructions.
Summary:
If a function needs to allocate both callee-save stack memory and local
stack memory, we currently decrement/increment the SP in two steps:
first for the callee-save area, and then for the local stack area. This
changes the code to allocate them both at once at the very beginning/end
of the function. This has two benefits:
1) there is one fewer sub/add micro-op in the prologue/epilogue
2) the stack adjustment instructions act as a scheduling barrier, so
moving them to the very beginning/end of the function increases post-RA
scheduler's ability to move instructions (that only depend on argument
registers) before any of the callee-save stores
This change can cause an increase in instructions if the original local
stack SP decrement could be folded into the first store to the stack.
This occurs when the first local stack store is to stack offset 0. In
this case we are trading off one more sub instruction for one fewer sub
micro-op (along with benefits (2) and (3) above).
Reviewers: t.p.northover
Subscribers: aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D18619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268746
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Jun Bum Lim [Fri, 6 May 2016 15:08:57 +0000 (15:08 +0000)]
[AArch64] Decouple zero store promotion from narrow ld merge. NFC.
Summary: This change refactors to decouple the zero store promotion from the narrow ld merge and add a flag (enable-narrow-ld-merge=true) to control the narrow ld merge optimization.
Reviewers: jmolloy, t.p.northover, mcrosier
Subscribers: aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D19885
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268744
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Nikolay Haustov [Fri, 6 May 2016 14:59:04 +0000 (14:59 +0000)]
Revert "AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2."
This reverts commit
47486d52454d60cdf6becc0b2efe533c73794380.
It broke calling OpenCL kernel from another kernel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268739
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Simon Pilgrim [Fri, 6 May 2016 14:38:14 +0000 (14:38 +0000)]
[CostModel][X86] Added costmodel tests for vector ctpop/ctlz/cttz/bitreverse/bswap
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268738
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Daniel Sanders [Fri, 6 May 2016 14:37:24 +0000 (14:37 +0000)]
[mips] Fix inconsistent .cprestore behaviour between direct object emission and assembling.
Summary:
Direct object emission has an initialization order problem where an
InitMCObjectFile is called after MipsTargetELFStreamer determines whether
PIC is enabled by default or not. There doesn't seem to be point that
initializes all cases so split the responsibility between
MipsTargetELFStreamer and MipsAsmPrinter.
Reviewers: sdardis
Subscribers: dsanders, llvm-commits, sdardis
Differential Revision: http://reviews.llvm.org/D19728
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268737
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Chad Rosier [Fri, 6 May 2016 14:25:14 +0000 (14:25 +0000)]
[SimplifyCFG] Prefer a simplification based on a dominating condition.
Rather than merge two branches with a common destination.
Differential Revision: http://reviews.llvm.org/D19743
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268735
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Daniel Sanders [Fri, 6 May 2016 13:49:25 +0000 (13:49 +0000)]
[mips] Correct the ordering of HI/LO pairs in the relocation table.
Summary:
There seems to have been a misunderstanding as to the meaning of 'offset' in
the rules laid down by our ABI. The previous code believed that 'offset' meant
the offset within the section that the relocation is applied to. However, it
should have meant the offset from the symbol used in the relocation expression.
This patch adds two fields to ELFRelocationEntry and uses them to correct the
order of relocations for MIPS. These fields contain:
* The original symbol before shouldRelocateWithSymbol() is considered. This
ensures that R_MIPS_GOT16 is able to correctly distinguish between local and
external symbols, allowing us to tell whether %got() requires a matching
%lo() or not (local symbols require one, external symbols don't). It also
prevents confusing cases where the fuzzy matching rules cause things like
%hi(foo)/%lo(foo+3) and %hi(bar)/%lo(bar+1) to swap their %lo()'s.
* The original offset before shouldRelocateWithSymbol() is considered. The
existing Addend field is always zero when the object uses in place addends
(because it's already moved it to the encoding) but MIPS needs to use the
original offset to ensure that the linker correctly calculates the carry-in
bit for %hi() and %got().
IAS ensures that unmatchable %hi()/%got() relocations are placed at the end of
the table to ensure that the linker rejects the table (we're unable to report
such errors directly). The alternatives to this risk accidental matching
against inappropriate relocations which may silently compute incorrect values
due to an incorrect carry bit between the %lo() and %hi()/%got().
Reviewers: sdardis
Subscribers: dsanders, sdardis, rafael, llvm-commits
Differential Revision: http://reviews.llvm.org/D19718
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268733
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Daniel Sanders [Fri, 6 May 2016 13:23:51 +0000 (13:23 +0000)]
[mips][mips16] Use isUnconditionalBranch() in AnalyzeBranch() and constant island pass.
Summary:
This stops it misidentifying unconditional branches as conditional branches
which fixes a -verify-machineinstrs error about exiting a function via fall through.
Reviewers: sdardis
Subscribers: dsanders, sdardis, llvm-commits
Differential Revision: http://reviews.llvm.org/D19864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268731
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Daniel Sanders [Fri, 6 May 2016 12:57:26 +0000 (12:57 +0000)]
[mips][fastisel] Conditional moves do not have implicit operands.
Reviewers: sdardis
Subscribers: dsanders, sdardis, llvm-commits
Differential Revision: http://reviews.llvm.org/D19862
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268730
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Sam Kolton [Fri, 6 May 2016 11:31:17 +0000 (11:31 +0000)]
[TableGen] AsmMatcher: support for default values for optional operands
Summary:
This change allows to specify "DefaultMethod" for optional operand (IsOptional = 1) in AsmOperandClass that return default value for operand. This is used in convertToMCInst to set default values in MCInst.
Previously if you wanted to set default value for operand you had to create custom converter method. With this change it is possible to use standard converters even when optional operands presented.
Reviewers: tstellarAMD, ab, craig.topper
Subscribers: jyknight, dsanders, arsenm, nhaustov, llvm-commits
Differential Revision: http://reviews.llvm.org/D18242
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268726
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Ryan Govostes [Fri, 6 May 2016 11:22:11 +0000 (11:22 +0000)]
Fix whitespace and line wrapping. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268725
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Ryan Govostes [Fri, 6 May 2016 10:25:22 +0000 (10:25 +0000)]
[asan] add option to set shadow mapping offset
Allowing overriding the default ASAN shadow mapping offset with the
-asan-shadow-offset option, and allow zero to be specified for both offset and
scale.
Patch by Aaron Carroll <aaronc@apple.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268724
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Dylan McKay [Fri, 6 May 2016 10:12:31 +0000 (10:12 +0000)]
[AVR] Add a majority of the backend code
Summary: This adds the majority of the AVR backend.
Reviewers: hfinkel, dsanders, vkalintiris, arsenm
Subscribers: dylanmckay
Differential Revision: http://reviews.llvm.org/D17906
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268722
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Silviu Baranga [Fri, 6 May 2016 09:37:14 +0000 (09:37 +0000)]
Attempt to fix the modules builder by declaring SCEV in LoopUtils.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268720
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Nikolay Haustov [Fri, 6 May 2016 09:23:13 +0000 (09:23 +0000)]
AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2.
Summary:
Check calling convention in AMDGPUMachineFunction::isKernel
This will be used for AMDGPU_HSA_KERNEL symbol type in output ELF.
Also, in the future unused non-kernels may be optimized.
Reviewers: tstellarAMD, arsenm
Subscribers: arsenm, joker.eph, llvm-commits
Differential Revision: http://reviews.llvm.org/D19917
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268719
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Nikolay Haustov [Fri, 6 May 2016 09:07:29 +0000 (09:07 +0000)]
AMDGPU/SI: Add amdgpu_kernel calling convention. Part 1.
Summary:
This will be used for AMDGPU_HSA_KERNEL symbol type in output ELF.
Also, in the future unused non-kernels may be optimized.
For now, also accept SPIR_KERNEL for HCC frontend.
Also, add bitcode compatibility tests for missing calling conventions
except AVR_BUILTIN which doesn't have parse code.
Reviewers: tstellarAMD, arsenm
Subscribers: arsenm, joker.eph, llvm-commits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268717
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Mehdi Amini [Fri, 6 May 2016 08:25:33 +0000 (08:25 +0000)]
ThinLTO: fix assertion and refactor check for hidden use from inline ASM in a helper function
This test was crashing, and currently it breaks bootstrapping clang with debuginfo
Differential Revision: http://reviews.llvm.org/D20008
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268715
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Zlatko Buljan [Fri, 6 May 2016 08:24:14 +0000 (08:24 +0000)]
[mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions
Differential Revision: http://reviews.llvm.org/D15744
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268714
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Craig Topper [Fri, 6 May 2016 06:56:14 +0000 (06:56 +0000)]
[TableGen] Fix a memory leak when creating SwitchOpcodeMatchers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268712
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Craig Topper [Fri, 6 May 2016 06:21:27 +0000 (06:21 +0000)]
[TableGen] Remove isSafeToReorderWithPatternPredicate from DAGISelMatchers as its not used anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268711
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Xinliang David Li [Fri, 6 May 2016 05:49:19 +0000 (05:49 +0000)]
[PM] port IR based PGO prof-gen pass to new pass manager
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268710
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Peter Collingbourne [Fri, 6 May 2016 02:41:23 +0000 (02:41 +0000)]
BitcodeWriter: Simplify. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268707
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Craig Topper [Fri, 6 May 2016 02:37:59 +0000 (02:37 +0000)]
[TableGen] Remove getHash support from DAGISelMatcher. It hasn't been used for some time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268706
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