OSDN Git Service
Nikola Prica [Wed, 10 Jul 2019 11:17:48 +0000 (11:17 +0000)]
[ELF] Loose a condition for relocation with a symbol
Deleted code was introduced as a work around for a bug in the gold linker
(http://sourceware.org/PR16794). Test case that was given as a reason for
this part of code, the one on previous link, now works for the gold.
This condition is too strict and when a code is compiled with debug info
it forces generation of numerous relocations with symbol for architectures
that do not have relocation addend.
Reviewers: arsenm, espindola
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D64327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365618
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Simon Pilgrim [Wed, 10 Jul 2019 10:46:36 +0000 (10:46 +0000)]
[X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable support
This patch checks to see if the vector element loads are based off a dereferenceable pointer that covers the entire vector width, in which case we don't need to have element loads at both extremes of the vector width - just the start (base pointer) of it.
Another step towards partial vector loads......
Differential Revision: https://reviews.llvm.org/D64205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365614
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Simon Pilgrim [Wed, 10 Jul 2019 10:45:09 +0000 (10:45 +0000)]
Fix const/non-const lambda return type warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365613
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Simon Pilgrim [Wed, 10 Jul 2019 10:34:44 +0000 (10:34 +0000)]
Fix "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365612
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Serguei Katkov [Wed, 10 Jul 2019 10:25:22 +0000 (10:25 +0000)]
[SimpleLoopUnswitch] Don't consider unswitching `switch` insructions with one unique successor
Only instructions with two or more unique successors should be considered for unswitching.
Patch Author: Daniil Suchkov.
Reviewers: reames, asbirlea, skatkov
Reviewed By: skatkov
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D64404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365611
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Mikhail Maltsev [Wed, 10 Jul 2019 08:59:17 +0000 (08:59 +0000)]
[ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is present
Summary:
Use the same predicates as VSTMDB/VLDMIA since VPUSH/VPOP alias to
these.
Patch by Momchil Velikov.
Reviewers: ostannard, simon_tatham, SjoerdMeijer, samparker, t.p.northover, dmgreen
Reviewed By: dmgreen
Subscribers: javed.absar, kristof.beyls, hiraditya, dmgreen, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365604
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James Henderson [Wed, 10 Jul 2019 08:56:13 +0000 (08:56 +0000)]
[docs][llvm-dwarfdump] Normalise some wording
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365603
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George Rimar [Wed, 10 Jul 2019 08:40:11 +0000 (08:40 +0000)]
[test/Object/nm-trivial-object.test] - Remove 4 precompiled binaries.
This converts 5 precompiled binaries to YAMLs,
removes 4 from inputs and performs a cleanup.
Differential revision: https://reviews.llvm.org/D64246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365601
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Serguei Katkov [Wed, 10 Jul 2019 08:25:48 +0000 (08:25 +0000)]
[SimpleLoopUnswitch] Add a test case exposing a bug
This test exposes a bug in SimpleLoopUnswitch that leads to a crash on
assert(SuccessorsCount > 1 && "Cannot unswitch a condition without multiple distinct successors!");
when SimpleLoopUnswitch considers unswitching of a loop by a switch with one successor.
Fix will be submitted soon.
Patch Author: Daniil Suchkov.
Reviewers: reames, asbirlea, skatkov
Reviewed By: skatkov
Subscribers: zzheng, llvm-commits
Differential Revision: https://reviews.llvm.org/D64403
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365600
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Mikael Holmen [Wed, 10 Jul 2019 06:18:03 +0000 (06:18 +0000)]
Silence gcc warning by adding parentheses to condition [NFC]
Without this gcc 7.4.0 complains with
../include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h:457:54: error: suggest parentheses around '&&' within '||' [-Werror=parentheses]
isArtifactCast(TmpDef->getOpcode()) &&
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~
"Expecting copy or artifact cast here");
~
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365597
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Kristina Brooks [Wed, 10 Jul 2019 03:52:31 +0000 (03:52 +0000)]
Fix modular build issues caused by BitCodes.h
Consolidate llvm::BWH_* statics into an enum to fix
module build issues. This fixes the LLVM_Bitcode module,
getting rid of -Wmodules-ambiguous-internal-linkage.
Differential Revision: https://reviews.llvm.org/D64469
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365594
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Craig Topper [Wed, 10 Jul 2019 00:40:01 +0000 (00:40 +0000)]
[X86] Limit getTargetConstantFromNode to only work on NormalLoads not extending loads.
This seems to fix a failure reported by Jordan Rupprecht, but we
don't have a reduced test case yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365589
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Reid Kleckner [Wed, 10 Jul 2019 00:34:13 +0000 (00:34 +0000)]
[Support] Move llvm::MemoryBuffer to sys::fs::file_t
Summary:
On Windows, Posix integer file descriptors are a compatibility layer
over native file handles provided by the C runtime. There is a hard
limit on the maximum number of file descriptors that a process can open,
and the limit is 8192. LLD typically doesn't run into this limit because
it opens input files, maps them into memory, and then immediately closes
the file descriptor. This prevents it from running out of FDs.
For various reasons, I'd like to open handles to every input file and
keep them open during linking. That requires migrating MemoryBuffer over
to taking open native file handles instead of integer FDs.
Reviewers: aganea, Bigcheese
Reviewed By: aganea
Subscribers: smeenai, silvas, mehdi_amini, hiraditya, steven_wu, dexonsmith, dang, llvm-commits, zturner
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63453
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365588
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Tom Stellard [Wed, 10 Jul 2019 00:22:41 +0000 (00:22 +0000)]
AMDGPU/GlobalISel: Add support for wide loads >= 256-bits
Summary:
This adds support for the most commonly used wide load types:
<8xi32>, <16xi32>, <4xi64>, and <8xi64>
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: hiraditya, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, volkan, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D57399
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365586
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Matt Arsenault [Tue, 9 Jul 2019 23:34:29 +0000 (23:34 +0000)]
GlobalISel: Implement lower for G_FCOPYSIGN
In SelectionDAG AMDGPU treated these as legal, but this was mostly
because the bitcasts required for FP types were painful. Theoretically
the bitpattern should eventually match to bfi, so don't bother trying
to get the patterns to import.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365583
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Francis Visoiu Mistrih [Tue, 9 Jul 2019 23:20:01 +0000 (23:20 +0000)]
[Bitcode] Explicitly include Bitstream/BitCodes.h and BitstreamWriter.h
This fixes a modules issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365580
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Francis Visoiu Mistrih [Tue, 9 Jul 2019 23:16:59 +0000 (23:16 +0000)]
[docs][Remarks] Add documentation for remarks in LLVM
This adds documentation that describes remarks in LLVM.
It aims at explaining what remarks are, how to enable them, and what
users can do with the different modes.
It lists all the available flags in LLVM (excluding clang), and
describes the expected YAML structure as well as the tools that support
the YAML format today.
Differential Revision: https://reviews.llvm.org/D64355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365578
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Craig Topper [Tue, 9 Jul 2019 23:05:54 +0000 (23:05 +0000)]
[X86] Don't form extloads in combineExtInVec unless the load extension is legal.
This should prevent doing this on pre-sse4.1 targets or for 256
bit vectors without avx2.
I don't know of a failure from this. Op legalization will probably
take care of, but seemed better to be safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365577
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Matt Arsenault [Tue, 9 Jul 2019 22:48:04 +0000 (22:48 +0000)]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365575
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Stanislav Mekhanoshin [Tue, 9 Jul 2019 22:42:24 +0000 (22:42 +0000)]
[AMDGPU] gfx908 v_pk_fmac_f16 support
Differential Revision: https://reviews.llvm.org/D64433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365573
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Peter Collingbourne [Tue, 9 Jul 2019 22:37:51 +0000 (22:37 +0000)]
gn build: Merge r365536.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365572
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Peter Collingbourne [Tue, 9 Jul 2019 22:37:41 +0000 (22:37 +0000)]
gn build: Merge r365532.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365571
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Peter Collingbourne [Tue, 9 Jul 2019 22:37:25 +0000 (22:37 +0000)]
gn build: Merge r365541.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365570
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Peter Collingbourne [Tue, 9 Jul 2019 22:37:09 +0000 (22:37 +0000)]
gn build: Merge r365531.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365569
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Pavel Labath [Tue, 9 Jul 2019 22:36:43 +0000 (22:36 +0000)]
Add lldb type unit support to the release notes
Reviewers: JDevlieghere, teemperor
Subscribers: llvm-commits, lldb-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365568
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Matt Arsenault [Tue, 9 Jul 2019 22:19:13 +0000 (22:19 +0000)]
GlobalISel: Combine unmerge of merge with intermediate cast
This eliminates some illegal intermediate vectors when operations are
scalarized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365566
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Vedant Kumar [Tue, 9 Jul 2019 22:01:04 +0000 (22:01 +0000)]
[Profile] Support raw/indexed profiles larger than 4GB
rdar://
45955976
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365565
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Yuanfang Chen [Tue, 9 Jul 2019 21:53:33 +0000 (21:53 +0000)]
[llvm-objdump] Keep warning for --disassemble-functions in correct order.
relative to normal output when dumping archive files.
prepare for PR35351.
Reviewers: jhenderson, grimar, MaskRay, rupprecht
Reviewed by: MaskRay, jhenderson
Differential Revision: https://reviews.llvm.org/D64165
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365564
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Stanislav Mekhanoshin [Tue, 9 Jul 2019 21:43:09 +0000 (21:43 +0000)]
[AMDGPU] gfx908 mAI instructions, MC part
Differential Revision: https://reviews.llvm.org/D64446
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365563
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Nikita Popov [Tue, 9 Jul 2019 20:24:44 +0000 (20:24 +0000)]
[SLP] Optimize getSpillCost(); NFCI
For a given set of live values, the spill cost will always be the
same for each call. Compute the cost once and multiply it by the
number of calls.
(I'm not sure this spill cost modeling makes sense if there are
multiple calls, as the spill cost will likely be shared across
calls in that case. But that's how it currently works.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365552
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Peter Collingbourne [Tue, 9 Jul 2019 20:22:36 +0000 (20:22 +0000)]
hwasan: Improve precision of checks using short granule tags.
A short granule is a granule of size between 1 and `TG-1` bytes. The size
of a short granule is stored at the location in shadow memory where the
granule's tag is normally stored, while the granule's actual tag is stored
in the last byte of the granule. This means that in order to verify that a
pointer tag matches a memory tag, HWASAN must check for two possibilities:
* the pointer tag is equal to the memory tag in shadow memory, or
* the shadow memory tag is actually a short granule size, the value being loaded
is in bounds of the granule and the pointer tag is equal to the last byte of
the granule.
Pointer tags between 1 to `TG-1` are possible and are as likely as any other
tag. This means that these tags in memory have two interpretations: the full
tag interpretation (where the pointer tag is between 1 and `TG-1` and the
last byte of the granule is ordinary data) and the short tag interpretation
(where the pointer tag is stored in the granule).
When HWASAN detects an error near a memory tag between 1 and `TG-1`, it
will show both the memory tag and the last byte of the granule. Currently,
it is up to the user to disambiguate the two possibilities.
Because this functionality obsoletes the right aligned heap feature of
the HWASAN memory allocator (and because we can no longer easily test
it), the feature is removed.
Also update the documentation to cover both short granule tags and
outlined checks.
Differential Revision: https://reviews.llvm.org/D63908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365551
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Philip Reames [Tue, 9 Jul 2019 19:59:39 +0000 (19:59 +0000)]
[PoisonChecking] Flesh out complete todo list for full coverage
Note: I don't actually plan to implement all of the cases at the moment, I'm just documenting them for completeness. There's a couple of cases left which are practically useful for me in debugging loop transforms, and I'll probably stop there for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365550
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Craig Topper [Tue, 9 Jul 2019 19:55:28 +0000 (19:55 +0000)]
[X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCastBeneficial/isStoreBitCastBeneficial to allow X86 to bypass it
Basically the problem is that X86 doesn't set the Fast flag from
allowsMemoryAccess on certain CPUs due to slow unaligned memory
subtarget features. This prevents bitcasts from being folded into
loads and stores. But all vector loads and stores of the same width
are the same cost on X86.
This patch merges the allowsMemoryAccess call into isLoadBitCastBeneficial to allow X86 to skip it.
Differential Revision: https://reviews.llvm.org/D64295
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365549
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Reid Kleckner [Tue, 9 Jul 2019 19:51:58 +0000 (19:51 +0000)]
Fix build error for VC STL, use llvm::make_unique
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365548
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Stanislav Mekhanoshin [Tue, 9 Jul 2019 19:41:51 +0000 (19:41 +0000)]
[AMDGPU] gfx908 register file changes
Differential Revision: https://reviews.llvm.org/D64438
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365546
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Philip Reames [Tue, 9 Jul 2019 19:26:12 +0000 (19:26 +0000)]
[PoisonCheker] Support for out of bounds operands on shifts + insert/extractelement
These are sources of poison which don't come from flags, but are clearly documented in the LangRef. Left off support for scalable vectors for the moment, but should be easy to add if anyone is interested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365543
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Sean Fertile [Tue, 9 Jul 2019 19:21:01 +0000 (19:21 +0000)]
Boilerplate for producing XCOFF object files from the PowerPC backend.
Stubs out a number of the classes needed to produce a new object file format
(XCOFF) for the powerpc-aix target. For testing input is an empty module which
produces an object file with just a file header.
Differential Revision: https://reviews.llvm.org/D61694
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365541
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Simon Pilgrim [Tue, 9 Jul 2019 19:19:17 +0000 (19:19 +0000)]
[X86] LowerToHorizontalOp - use count_if to count non-UNDEF ops. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365540
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Philip Reames [Tue, 9 Jul 2019 18:56:41 +0000 (18:56 +0000)]
[PoisonChecking] Add validation rules for "exact" on sdiv/udiv
As directly stated in the LangRef, no ambiguity here...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365538
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Bob Haarman [Tue, 9 Jul 2019 18:50:55 +0000 (18:50 +0000)]
[ThinLTO] only emit used or referenced CFI records to index
Summary: We emit CFI_FUNCTION_DEFS and CFI_FUNCTION_DECLS to
distributed ThinLTO indices to implement indirect function call
checking. This change causes us to only emit entries for functions
that are either defined or used by the module we're writing the index
for (instead of all functions in the combined index), which can make
the indices substantially smaller.
Fixes PR42378.
Reviewers: pcc, vitalybuka, eugenis
Subscribers: mehdi_amini, hiraditya, dexonsmith, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63887
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365537
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Philip Reames [Tue, 9 Jul 2019 18:49:29 +0000 (18:49 +0000)]
Add a transform pass to make the executable semantics of poison explicit in the IR
Implements a transform pass which instruments IR such that poison semantics are made explicit. That is, it provides a (possibly partial) executable semantics for every instruction w.r.t. poison as specified in the LLVM LangRef. There are obvious parallels to the sanitizer tools, but this pass is focused purely on the semantics of LLVM IR, not any particular source language.
The target audience for this tool is developers working on or targetting LLVM from a frontend. The idea is to be able to take arbitrary IR (with the assumption of known inputs), and evaluate it concretely after having made poison semantics explicit to detect cases where either a) the original code executes UB, or b) a transform pass introduces UB which didn't exist in the original program.
At the moment, this is mostly the framework and still needs to be fleshed out. By reusing existing code we have decent coverage, but there's a lot of cases not yet handled. What's here is good enough to handle interesting cases though; for instance, one of the recent LFTR bugs involved UB being triggered by integer induction variables with nsw/nuw flags would be reported by the current code.
(See comment in PoisonChecking.cpp for full explanation and context)
Differential Revision: https://reviews.llvm.org/D64215
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365536
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Sean Fertile [Tue, 9 Jul 2019 18:44:28 +0000 (18:44 +0000)]
Try to appease the Windows build bots.
Several of the conditonal operators commited in llvm-svn: 365524 fail to compile
on the windows buildbots. Converting to an if and early return to try to fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365535
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Yonghong Song [Tue, 9 Jul 2019 18:35:46 +0000 (18:35 +0000)]
[BPF] Fix a typo in the file name
Fixed the file name from BPFAbstrctMemberAccess.cpp to
BPFAbstractMemberAccess.cpp.
Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365532
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Peter Collingbourne [Tue, 9 Jul 2019 18:30:38 +0000 (18:30 +0000)]
gn build: Merge r365503.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365530
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Michael Liao [Tue, 9 Jul 2019 18:22:48 +0000 (18:22 +0000)]
[unittest] Add the missing bogus machine register info initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365529
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Stanislav Mekhanoshin [Tue, 9 Jul 2019 18:10:06 +0000 (18:10 +0000)]
[AMDGPU] gfx908 target
Differential Revision: https://reviews.llvm.org/D64429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365525
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Sean Fertile [Tue, 9 Jul 2019 18:09:11 +0000 (18:09 +0000)]
[Object][XCOFF] Add support for 64-bit file header and section header dumping.
Adds a readobj dumper for 32-bit and 64-bit section header tables, and extend
support for the file-header dumping to include 64-bit object files. Also
refactors the binary file parsing to be done in a helper function in an attempt
to cleanup error handeling.
Differential Revision: https://reviews.llvm.org/D63843
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365524
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Sanjay Patel [Tue, 9 Jul 2019 18:06:16 +0000 (18:06 +0000)]
[InstCombine] add tests for trunc(load); NFC
I'm not sure if transforming any of these is valid as
a target-independent fold, but we might as well have
a few tests here to confirm or deny our position.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365523
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Matt Arsenault [Tue, 9 Jul 2019 17:54:34 +0000 (17:54 +0000)]
AMDGPU: Fix test failing since r365512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365521
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Jinsong Ji [Tue, 9 Jul 2019 17:53:09 +0000 (17:53 +0000)]
Revert "[HardwareLoops] NFC - move hardware loop checking code to isHardwareLoopProfitable()"
This reverts commit
d95557306585404893d610784edb3e32f1bfce18.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365520
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Steven Wu [Tue, 9 Jul 2019 17:47:14 +0000 (17:47 +0000)]
Add lit.local.cfg to llvm-objdump tests
Add configuration file to llvm-objdump tests to treat files with .yaml
extension as tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365519
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Nico Weber [Tue, 9 Jul 2019 17:19:47 +0000 (17:19 +0000)]
Remove a comment that has been obsolete since r327679
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365517
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Michael Liao [Tue, 9 Jul 2019 17:19:01 +0000 (17:19 +0000)]
[unittest] Add bogus register info.
Reviewers: dstenb
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64421
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365516
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Nico Weber [Tue, 9 Jul 2019 17:14:24 +0000 (17:14 +0000)]
Rename llvm/test/tools/llvm-pdbdump to llvm/test/tools/llvm-pdbutil
llvm-pdbdump was renamed to llvm-pdbutil long ago. This updates the test
to be where you'd expect them to be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365515
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Nico Weber [Tue, 9 Jul 2019 17:02:51 +0000 (17:02 +0000)]
Make pdbdump-objfilename test work again
- The test had extension .yaml, which lit doesn't execute in this
directory. Rename to .test to make it run, and move the yaml bits
into a dedicated file, like with all other tests in this dir.
- llvm-pdbdump got renamed to llvm-pdbutil long ago, update test.
- -dbi-module-info got renamed in r305032, update test for this too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365514
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Christudasan Devadasan [Tue, 9 Jul 2019 16:48:42 +0000 (16:48 +0000)]
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.
Function return instruction lowering, currently uses the fixed register pair s[30:31] for holding
the return address. It can be any SGPR pair other than the CSRs. Created an SGPR pair sub-register class
exclusive of the CSRs, and used this regclass while lowering the return instruction.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D63924
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365512
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Sam Elliott [Tue, 9 Jul 2019 16:24:16 +0000 (16:24 +0000)]
[RISCV] Fix ICE in isDesirableToCommuteWithShift
Summary:
There was an error being thrown from isDesirableToCommuteWithShift in
some tests. This was tracked down to the method being called before
legalisation, with an extended value type, not a machine value type.
In the case I diagnosed, the error was only hit with an instruction sequence
involving `i24`s in the add and shift. `i24` is not a Machine ValueType, it is
instead an Extended ValueType which was causing the issue.
I have added a test to cover this case, and fixed the error in the callback.
Reviewers: asb, luismarques
Reviewed By: asb
Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64425
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365511
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Amara Emerson [Tue, 9 Jul 2019 16:05:59 +0000 (16:05 +0000)]
[AArch64][GlobalISel] Optimize conditional branches followed by unconditional branches
If we have an icmp->brcond->br sequence where the brcond just branches to the
next block jumping over the br, while the br takes the false edge, then we can
modify the conditional branch to jump to the br's target while inverting the
condition of the incoming icmp. This means we can eliminate the br as an
unconditional branch to the fallthrough block.
Differential Revision: https://reviews.llvm.org/D64354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365510
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Simon Atanasyan [Tue, 9 Jul 2019 15:48:16 +0000 (15:48 +0000)]
[mips] Show error in case of using FP64 mode on pre MIPS32R2 CPU
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365508
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Simon Atanasyan [Tue, 9 Jul 2019 15:48:05 +0000 (15:48 +0000)]
[mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC
Support for 64-bit coprocessors on a 32-bit architecture
was added in `MIPS32 R2`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365507
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David Bolvansky [Tue, 9 Jul 2019 15:31:36 +0000 (15:31 +0000)]
[NFC] Fixed tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365506
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Simon Pilgrim [Tue, 9 Jul 2019 15:28:57 +0000 (15:28 +0000)]
[DAGCombine] LoadedSlice - keep getOffsetFromBase() uint64_t offset. NFCI.
Keep the uint64_t type from getOffsetFromBase() to stop truncation/extension overflow warnings in MSVC in alignment math.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365504
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Yonghong Song [Tue, 9 Jul 2019 15:28:41 +0000 (15:28 +0000)]
[BPF] Support for compile once and run everywhere
Introduction
============
This patch added intial support for bpf program compile once
and run everywhere (CO-RE).
The main motivation is for bpf program which depends on
kernel headers which may vary between different kernel versions.
The initial discussion can be found at https://lwn.net/Articles/773198/.
Currently, bpf program accesses kernel internal data structure
through bpf_probe_read() helper. The idea is to capture the
kernel data structure to be accessed through bpf_probe_read()
and relocate them on different kernel versions.
On each host, right before bpf program load, the bpfloader
will look at the types of the native linux through vmlinux BTF,
calculates proper access offset and patch the instruction.
To accommodate this, three intrinsic functions
preserve_{array,union,struct}_access_index
are introduced which in clang will preserve the base pointer,
struct/union/array access_index and struct/union debuginfo type
information. Later, bpf IR pass can reconstruct the whole gep
access chains without looking at gep itself.
This patch did the following:
. An IR pass is added to convert preserve_*_access_index to
global variable who name encodes the getelementptr
access pattern. The global variable has metadata
attached to describe the corresponding struct/union
debuginfo type.
. An SimplifyPatchable MachineInstruction pass is added
to remove unnecessary loads.
. The BTF output pass is enhanced to generate relocation
records located in .BTF.ext section.
Typical CO-RE also needs support of global variables which can
be assigned to different values to different hosts. For example,
kernel version can be used to guard different versions of codes.
This patch added the support for patchable externals as well.
Example
=======
The following is an example.
struct pt_regs {
long arg1;
long arg2;
};
struct sk_buff {
int i;
struct net_device *dev;
};
#define _(x) (__builtin_preserve_access_index(x))
static int (*bpf_probe_read)(void *dst, int size, const void *unsafe_ptr) =
(void *) 4;
extern __attribute__((section(".BPF.patchable_externs"))) unsigned __kernel_version;
int bpf_prog(struct pt_regs *ctx) {
struct net_device *dev = 0;
// ctx->arg* does not need bpf_probe_read
if (__kernel_version >= 41608)
bpf_probe_read(&dev, sizeof(dev), _(&((struct sk_buff *)ctx->arg1)->dev));
else
bpf_probe_read(&dev, sizeof(dev), _(&((struct sk_buff *)ctx->arg2)->dev));
return dev != 0;
}
In the above, we want to translate the third argument of
bpf_probe_read() as relocations.
-bash-4.4$ clang -target bpf -O2 -g -S trace.c
The compiler will generate two new subsections in .BTF.ext,
OffsetReloc and ExternReloc.
OffsetReloc is to record the structure member offset operations,
and ExternalReloc is to record the external globals where
only u8, u16, u32 and u64 are supported.
BPFOffsetReloc Size
struct SecLOffsetReloc for ELF section #1
A number of struct BPFOffsetReloc for ELF section #1
struct SecOffsetReloc for ELF section #2
A number of struct BPFOffsetReloc for ELF section #2
...
BPFExternReloc Size
struct SecExternReloc for ELF section #1
A number of struct BPFExternReloc for ELF section #1
struct SecExternReloc for ELF section #2
A number of struct BPFExternReloc for ELF section #2
struct BPFOffsetReloc {
uint32_t InsnOffset; ///< Byte offset in this section
uint32_t TypeID; ///< TypeID for the relocation
uint32_t OffsetNameOff; ///< The string to traverse types
};
struct BPFExternReloc {
uint32_t InsnOffset; ///< Byte offset in this section
uint32_t ExternNameOff; ///< The string for external variable
};
Note that only externs with attribute section ".BPF.patchable_externs"
are considered for Extern Reloc which will be patched by bpf loader
right before the load.
For the above test case, two offset records and one extern record
will be generated:
OffsetReloc records:
.long .Ltmp12 # Insn Offset
.long 7 # TypeId
.long 242 # Type Decode String
.long .Ltmp18 # Insn Offset
.long 7 # TypeId
.long 242 # Type Decode String
ExternReloc record:
.long .Ltmp5 # Insn Offset
.long 165 # External Variable
In string table:
.ascii "0:1" # string offset=242
.ascii "__kernel_version" # string offset=165
The default member offset can be calculated as
the 2nd member offset (0 representing the 1st member) of struct "sk_buff".
The asm code:
.Ltmp5:
.Ltmp6:
r2 = 0
r3 = 41608
.Ltmp7:
.Ltmp8:
.loc 1 18 9 is_stmt 0 # t.c:18:9
.Ltmp9:
if r3 > r2 goto LBB0_2
.Ltmp10:
.Ltmp11:
.loc 1 0 9 # t.c:0:9
.Ltmp12:
r2 = 8
.Ltmp13:
.loc 1 19 66 is_stmt 1 # t.c:19:66
.Ltmp14:
.Ltmp15:
r3 = *(u64 *)(r1 + 0)
goto LBB0_3
.Ltmp16:
.Ltmp17:
LBB0_2:
.loc 1 0 66 is_stmt 0 # t.c:0:66
.Ltmp18:
r2 = 8
.loc 1 21 66 is_stmt 1 # t.c:21:66
.Ltmp19:
r3 = *(u64 *)(r1 + 8)
.Ltmp20:
.Ltmp21:
LBB0_3:
.loc 1 0 66 is_stmt 0 # t.c:0:66
r3 += r2
r1 = r10
.Ltmp22:
.Ltmp23:
.Ltmp24:
r1 += -8
r2 = 8
call 4
For instruction .Ltmp12 and .Ltmp18, "r2 = 8", the number
8 is the structure offset based on the current BTF.
Loader needs to adjust it if it changes on the host.
For instruction .Ltmp5, "r2 = 0", the external variable
got a default value 0, loader needs to supply an appropriate
value for the particular host.
Compiling to generate object code and disassemble:
0000000000000000 bpf_prog:
0: b7 02 00 00 00 00 00 00 r2 = 0
1: 7b 2a f8 ff 00 00 00 00 *(u64 *)(r10 - 8) = r2
2: b7 02 00 00 00 00 00 00 r2 = 0
3: b7 03 00 00 88 a2 00 00 r3 = 41608
4: 2d 23 03 00 00 00 00 00 if r3 > r2 goto +3 <LBB0_2>
5: b7 02 00 00 08 00 00 00 r2 = 8
6: 79 13 00 00 00 00 00 00 r3 = *(u64 *)(r1 + 0)
7: 05 00 02 00 00 00 00 00 goto +2 <LBB0_3>
0000000000000040 LBB0_2:
8: b7 02 00 00 08 00 00 00 r2 = 8
9: 79 13 08 00 00 00 00 00 r3 = *(u64 *)(r1 + 8)
0000000000000050 LBB0_3:
10: 0f 23 00 00 00 00 00 00 r3 += r2
11: bf a1 00 00 00 00 00 00 r1 = r10
12: 07 01 00 00 f8 ff ff ff r1 += -8
13: b7 02 00 00 08 00 00 00 r2 = 8
14: 85 00 00 00 04 00 00 00 call 4
Instructions #2, #5 and #8 need relocation resoutions from the loader.
Signed-off-by: Yonghong Song <yhs@fb.com>
Differential Revision: https://reviews.llvm.org/D61524
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365503
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Simon Pilgrim [Tue, 9 Jul 2019 15:24:19 +0000 (15:24 +0000)]
[ADT] Remove MSVC-only "no two-phase name lookup" typename path.
Now that we've dropped VS2015 support (D64326) we can use the regular codepath as VS2017+ correctly handles it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365502
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David Bolvansky [Tue, 9 Jul 2019 15:12:01 +0000 (15:12 +0000)]
[NFC] Added tests for D64285
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365501
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Chen Zheng [Tue, 9 Jul 2019 14:56:17 +0000 (14:56 +0000)]
[HardwareLoops] NFC - move hardware loop checking code to isHardwareLoopProfitable()
Differential Revision: https://reviews.llvm.org/D64197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365497
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David Green [Tue, 9 Jul 2019 14:43:17 +0000 (14:43 +0000)]
[ARM] Add test for MVE and no floats. NFC
Adds a simple test that MVE with no floating point will be promoted correctly
to software float calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365496
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Sanjay Patel [Tue, 9 Jul 2019 14:43:03 +0000 (14:43 +0000)]
[InferFunctionAttrs] add more tests for derefenceable; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365495
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Petar Avramovic [Tue, 9 Jul 2019 14:36:17 +0000 (14:36 +0000)]
[MIPS GlobalISel] Register bank select for G_PHI. Select i64 phi
Select gprb or fprb when def/use register operand of G_PHI is
used/defined by either:
copy to/from physical register or
instruction with only one mapping available for that use/def operand.
Integer s64 phi is handled with narrowScalar when mapping is applied,
produced artifacts are combined away. Manually set gprb to all register
operands of instructions created during narrowScalar.
Differential Revision: https://reviews.llvm.org/D64351
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365494
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Matt Arsenault [Tue, 9 Jul 2019 14:30:57 +0000 (14:30 +0000)]
AMDGPU/GlobalISel: Prepare some tests for store selection
Mostsly these would fail due to trying to use SI with a flat
operation. Implementing global loads with MUBUF is more work than
flat, so these won't be handled in the initial load selection.
Others fail because store of s64 won't initially work, as the current
set of patterns expect everything to be turned into v2i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365493
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Petar Avramovic [Tue, 9 Jul 2019 14:30:29 +0000 (14:30 +0000)]
[MIPS GlobalISel] Regbanks for G_SELECT. Select i64, f32 and f64 select
Select gprb or fprb when def/use register operand of G_SELECT is
used/defined by either:
copy to/from physical register or
instruction with only one mapping available for that use/def operand.
Integer s64 select is handled with narrowScalar when mapping is applied,
produced artifacts are combined away. Manually set gprb to all register
operands of instructions created during narrowScalar.
For selection of floating point s32 or s64 select it is enough to set
fprb of appropriate size and selectImpl will do the rest.
Differential Revision: https://reviews.llvm.org/D64350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365492
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Matt Arsenault [Tue, 9 Jul 2019 14:30:02 +0000 (14:30 +0000)]
AMDGPU/GlobalISel: Fix test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365491
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James Henderson [Tue, 9 Jul 2019 14:20:58 +0000 (14:20 +0000)]
[docs][llvm-dwarfdump] Fix wording
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365489
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Matt Arsenault [Tue, 9 Jul 2019 14:17:31 +0000 (14:17 +0000)]
AMDGPU/GlobalISel: Legalize more concat_vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365488
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Matt Arsenault [Tue, 9 Jul 2019 14:13:09 +0000 (14:13 +0000)]
AMDGPU/GlobalISel: Improve regbankselect for icmp s16
Account for 64-bit scalar eq/ne when available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365487
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Matt Arsenault [Tue, 9 Jul 2019 14:10:43 +0000 (14:10 +0000)]
AMDGPU/GlobalISel: Make s16 G_ICMP legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365486
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Matt Arsenault [Tue, 9 Jul 2019 14:05:11 +0000 (14:05 +0000)]
AMDGPU/GlobalISel: Select G_SUB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365484
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Matt Arsenault [Tue, 9 Jul 2019 14:02:26 +0000 (14:02 +0000)]
AMDGPU/GlobalISel: Select G_UNMERGE_VALUES
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365483
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Matt Arsenault [Tue, 9 Jul 2019 14:02:20 +0000 (14:02 +0000)]
AMDGPU/GlobalISel: Select G_MERGE_VALUES
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365482
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Nico Weber [Tue, 9 Jul 2019 13:58:18 +0000 (13:58 +0000)]
gn build: Merge r365453
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365481
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Simon Pilgrim [Tue, 9 Jul 2019 13:07:48 +0000 (13:07 +0000)]
[CodeGen] AccelTable - remove non-constexpr (MSVC) Atom defs
Now that we've dropped VS2015 support (D64326) we can enable the constexpr variables on MSVC builds as VS2017+ correctly handles them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365477
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Simon Atanasyan [Tue, 9 Jul 2019 12:55:55 +0000 (12:55 +0000)]
[mips] Implement sge/sgeu pseudo instructions
The `sge/sgeu Dst, Src1, Src2/Imm` pseudo instructions set register
`Dst` to 1 if register `Src1` is greater than or equal `Src2/Imm` and
to 0 otherwise.
Differential Revision: https://reviews.llvm.org/D64314
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365476
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Simon Atanasyan [Tue, 9 Jul 2019 12:55:42 +0000 (12:55 +0000)]
[mips] Implement sgt/sgtu pseudo instructions with immediate operand
The `sgt/sgtu Dst, Src1, Src2/Imm` pseudo instructions set register
`Dst` to 1 if register `Src1` is greater than `Src2/Imm` and to 0 otherwise.
Differential Revision: https://reviews.llvm.org/D64313
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365475
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James Henderson [Tue, 9 Jul 2019 12:41:39 +0000 (12:41 +0000)]
[docs][llvm-objdump] Make some wording improvements/simplifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365474
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Tim Northover [Tue, 9 Jul 2019 12:36:36 +0000 (12:36 +0000)]
OpaquePtr: pass type to CreateLoad. NFC.
This is the one place in LLVM itself that used the deprecated API for
CreateLoad, so I just added the type in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365472
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Simon Pilgrim [Tue, 9 Jul 2019 12:20:04 +0000 (12:20 +0000)]
[ADT] Enable ArrayRef/StringRef is_assignable tests on MSVC
Now that we've dropped VS2015 support (D64326) we can enable these static_asserts on MSVC builds as VS2017+ correctly handles them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365471
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Djordje Todorovic [Tue, 9 Jul 2019 12:06:21 +0000 (12:06 +0000)]
[NFC][AsmPrinter] Fix the formatting for the rL365467
In addition, fix the build failure for the 'unused'
variable. The variable was used inside the 'LLVM_DEBUG()'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365469
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Tim Northover [Tue, 9 Jul 2019 11:35:35 +0000 (11:35 +0000)]
OpaquePtr: add Type parameter to Loads analysis API.
This makes the functions in Loads.h require a type to be specified
independently of the pointer Value so that when pointers have no structure
other than address-space, it can still do its job.
Most callers had an obvious memory operation handy to provide this type, but a
SROA and ArgumentPromotion were doing more complicated analysis. They get
updated to merge the properties of the various instructions they were
considering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365468
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Djordje Todorovic [Tue, 9 Jul 2019 11:33:56 +0000 (11:33 +0000)]
[DwarfDebug] Dump call site debug info
Dump the DWARF information about call sites and call site parameters into
debug info sections.
The patch also provides an interface for the interpretation of instructions
that could load values of a call site parameters in order to generate DWARF
about the call site parameters.
([13/13] Introduce the debug entry values.)
Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>
Differential Revision: https://reviews.llvm.org/D60716
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365467
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Alex Bradbury [Tue, 9 Jul 2019 10:56:18 +0000 (10:56 +0000)]
[RISCV] Fix RISCVTTIImpl::getIntImmCost for immediates where getMinSignedBits() > 64
APInt::getSExtValue will assert if getMinSignedBits() > 64. This can happen,
for instance, if examining an i128. Avoid this assertion by checking
Imm.getMinSignedBits() <= 64 before doing
getTLI()->isLegalAddImmediate(Imm.getSExtValue()). We could directly check
getMinSignedBits() <= 12 but it seems better to reuse the isLegalAddImmediate
helper for this.
Differential Revision: https://reviews.llvm.org/D64390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365462
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James Henderson [Tue, 9 Jul 2019 10:40:50 +0000 (10:40 +0000)]
[docs][llvm-nm] Improve some wording
In particular, the --debug-syms switch really doesn't have anything to
do with debuggers, so I've updated the document accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365461
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Bjorn Pettersson [Tue, 9 Jul 2019 10:27:51 +0000 (10:27 +0000)]
[SelectionDAG] Simplify some calls to getSetCCResultType. NFC
DAGTypeLegalizer and SelectionDAGLegalize has helper
functions wrapping the call to TLI.getSetCCResultType(...).
Use those helpers in more places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365456
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Bjorn Pettersson [Tue, 9 Jul 2019 10:24:50 +0000 (10:24 +0000)]
[LegalizeTypes] Fix saturation bug for smul.fix.sat
Summary:
Make sure we use SETGE instead of SETGT when checking
if the sign bit is zero at SMULFIXSAT expansion.
The faulty expansion occured when doing "expand" of
SMULFIXSAT and the scale was exactly matching the
size of the smaller type. For example doing
i64 Z = SMULFIXSAT X, Y, 32
and expanding X/Y/Z into using two i32 values.
The problem was that we sometimes did not saturate
to min when overflowing.
Here is an example using Q3.4 numbers:
Consider that we are multiplying X and Y.
X = 0x80 (-8.0 as Q3.4)
Y = 0x20 (2.0 as Q3.4)
To avoid loss of precision we do a widening
multiplication, getting a 16 bit result
Z = 0xF000 (-16.0 as Q7.8)
To detect negative overflow we should check if
the five most significant bits in Z are less than -1.
Assume that we name the 4 most significant bits
as HH and the next 4 bits as HL. Then we can do the
check by examining if
(HH < -1) or (HH == -1 && "sign bit in HL is zero").
The fault was that we have been doing the check as
(HH < -1) or (HH == -1 && HL > 0)
instead of
(HH < -1) or (HH == -1 && HL >= 0).
In our example HH is -1 and HL is 0, so the old
code did not trigger saturation and simply truncated
the result to 0x00 (0.0). With the bugfix we instead
detect that we should saturate to min, and the result
will be set to 0x80 (-8.0).
Reviewers: leonardchan, bevinh
Reviewed By: leonardchan
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64331
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365455
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Simon Pilgrim [Tue, 9 Jul 2019 10:10:48 +0000 (10:10 +0000)]
Retire VS2015 Support
As proposed here: https://lists.llvm.org/pipermail/llvm-dev/2019-June/133147.html
This patch raises the minimum supported version to build LLVM/Clang to Visual Studio 2017.
Differential Revision: https://reviews.llvm.org/D64326
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365452
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James Henderson [Tue, 9 Jul 2019 10:03:12 +0000 (10:03 +0000)]
[docs][llvm-dwarfdump] Make some option descriptions clearer and more precise
Some of the wording in the doc (taken largely from the help text), was a
little imprecise in some cases, so this patch makes it a little more
precise.
Reviewed by: JDevlieghere, probinson
Differential Revision: https://reviews.llvm.org/D64332
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365451
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Haojian Wu [Tue, 9 Jul 2019 09:57:45 +0000 (09:57 +0000)]
[llvm-profdata] Don't make the output overwrite the input file.
Some file systems may not allow this behavior, the test fails on our internal
system ("Permission denied").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365450
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Guillaume Chatelet [Tue, 9 Jul 2019 09:53:36 +0000 (09:53 +0000)]
Fixing @llvm.memcpy not honoring volatile.
This is explicitly not addressing target-specific code, or calls to memcpy.
Summary: https://bugs.llvm.org/show_bug.cgi?id=42254
Reviewers: courbet
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63215
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365449
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Jeremy Morse [Tue, 9 Jul 2019 09:38:03 +0000 (09:38 +0000)]
Revert r364515 and r364524
Jordan reports on llvm-commits a performance regression with r364515,
backing the patch out while it's investigated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365448
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Kai Luo [Tue, 9 Jul 2019 09:12:17 +0000 (09:12 +0000)]
[NFC][PowerPC] Added a test to show current codegen of MachinePRE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365447
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Djordje Todorovic [Tue, 9 Jul 2019 08:36:34 +0000 (08:36 +0000)]
Reland "[LiveDebugValues] Emit the debug entry values"
Emit replacements for clobbered parameters location if the parameter
has unmodified value throughout the funciton. This is basic scenario
where we can use the debug entry values.
([12/13] Introduce the debug entry values.)
Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>
Differential Revision: https://reviews.llvm.org/D58042
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365444
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