OSDN Git Service
Adhemerval Zanella [Thu, 6 Jun 2019 12:38:11 +0000 (12:38 +0000)]
AArch64] Handle ISD::LRINT and ISD::LLRINT for float16
This patch is a follow up for D62018 to add lrint/llrint
support for float16.
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62863
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362700
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Thu, 6 Jun 2019 12:35:46 +0000 (12:35 +0000)]
Revert "[SCEV] Use wrap flags in InsertBinop"
This reverts commit r362687. Miscompiles llvm-profdata during selfhost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362699
91177308-0d34-0410-b5e6-
96231b3b80d8
Adhemerval Zanella [Thu, 6 Jun 2019 11:53:26 +0000 (11:53 +0000)]
[AArch64] Handle ISD::LROUND and ISD::LLROUND for float16
This patch is a follow up for D61391 to add lround/llround
support for float16.
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362698
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 6 Jun 2019 11:15:36 +0000 (11:15 +0000)]
[X86][SSE] Add nonuniform constant vector test for PR42105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362697
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Thu, 6 Jun 2019 10:37:06 +0000 (10:37 +0000)]
Include what you use in LanaiAsmParser.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362696
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 6 Jun 2019 10:21:18 +0000 (10:21 +0000)]
[DAGCombine] Cleanup isNegatibleForFree/GetNegatedExpression. NFCI.
Prep work for PR42105 - clang-format, use auto for cast and merge nested if()s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362695
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 6 Jun 2019 10:15:26 +0000 (10:15 +0000)]
Fix whitespace indentation. NFCI.
Tabs are not our friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362694
91177308-0d34-0410-b5e6-
96231b3b80d8
Luis Marques [Thu, 6 Jun 2019 10:12:28 +0000 (10:12 +0000)]
[RISCV] Disable test/Analysis/CostModel/RISCV tests if RISCV backend not built
Adds missing lit.local.cfg. Fixes rL362691.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362693
91177308-0d34-0410-b5e6-
96231b3b80d8
Petar Avramovic [Thu, 6 Jun 2019 10:00:41 +0000 (10:00 +0000)]
[MIPS GlobalISel] Select sqrt
Select G_FSQRT for MIPS32.
Differential Revision: https://reviews.llvm.org/D62905
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362692
91177308-0d34-0410-b5e6-
96231b3b80d8
Luis Marques [Thu, 6 Jun 2019 09:47:53 +0000 (09:47 +0000)]
[RISCV] Add CostModel GEP tests
Differential Revision: https://reviews.llvm.org/D61185
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362691
91177308-0d34-0410-b5e6-
96231b3b80d8
Petar Avramovic [Thu, 6 Jun 2019 09:22:37 +0000 (09:22 +0000)]
[MIPS GlobalISel] Select fabs
Select G_FABS for MIPS32.
Differential Revision: https://reviews.llvm.org/D62903
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362690
91177308-0d34-0410-b5e6-
96231b3b80d8
Petar Avramovic [Thu, 6 Jun 2019 09:16:58 +0000 (09:16 +0000)]
[MIPS GlobalISel] Select fpext and fptrunc
Select G_FPEXT and G_FPTRUNC for MIPS32.
Differential Revision: https://reviews.llvm.org/D62902
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362689
91177308-0d34-0410-b5e6-
96231b3b80d8
Petar Avramovic [Thu, 6 Jun 2019 09:02:24 +0000 (09:02 +0000)]
[MIPS GlobalISel] Select floor and ceil
Select G_FFLOOR and G_FCEIL for MIPS32.
Differential Revision: https://reviews.llvm.org/D62901
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362688
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Parker [Thu, 6 Jun 2019 08:56:26 +0000 (08:56 +0000)]
[SCEV] Use wrap flags in InsertBinop
If the given SCEVExpr has no (un)signed flags attached to it, transfer
these to the resulting instruction or use them to find an existing
instruction.
Differential Revision: https://reviews.llvm.org/D61934
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362687
91177308-0d34-0410-b5e6-
96231b3b80d8
Dylan McKay [Thu, 6 Jun 2019 08:06:50 +0000 (08:06 +0000)]
[AVR] Fix the 'load.ll' test after r362351
In that commit, the 'load.ll' test was modified, but still failed.
This commit updates the test so that it now passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362684
91177308-0d34-0410-b5e6-
96231b3b80d8
Amara Emerson [Thu, 6 Jun 2019 07:58:37 +0000 (07:58 +0000)]
[AArch64][GlobalISel] Add manual selection support for G_ZEXTLOADs to s64.
We already get support for G_ZEXTLOAD to s32 from the importer, but it can't
deal with the SUBREG_TO_REG in the pattern. Tweaking the existing manual
selection code for G_LOAD to handle an additional SUBREG_TO_REG when dealing
with G_ZEXTLOAD isn't much work.
Also add tests to check the imported pattern selections to s32 work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362681
91177308-0d34-0410-b5e6-
96231b3b80d8
Amara Emerson [Thu, 6 Jun 2019 07:33:47 +0000 (07:33 +0000)]
[AArch64][GlobalISel] Add the new changes to fix PR42129 that were supposed to go into r362666.
The changes weren't staged so ended up just re-commiting the unmodified reverted change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362677
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 6 Jun 2019 05:41:27 +0000 (05:41 +0000)]
[X86] Don't turn avx masked.load with constant mask into masked.load+vselect when passthru value is all zeroes.
This is intended to enable the use of an immediate blend or
more optimal instruction. But if the passthru is zero we don't
need any additional instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362675
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 6 Jun 2019 05:41:22 +0000 (05:41 +0000)]
[X86] Add test case for masked load with constant mask and all zeros passthru.
avx/avx2 masked loads only support all zeros for passthru in hardware.
So we have to emit a blend for all other values. We have an optimization
that tries to optimize this blend if the mask is constant. But we
don't need to perform this optimization if the passthru value is zero
which doesn't need the blend at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362674
91177308-0d34-0410-b5e6-
96231b3b80d8
Amara Emerson [Wed, 5 Jun 2019 23:46:16 +0000 (23:46 +0000)]
Revert "Revert "[AArch64][GlobalISel] Optimize G_FCMP + G_SELECT pairs when G_SELECT is fp""
When looking through copies, make sure to not try to find the vreg def of a physreg.
Normally getVRegDef will return nullptr in this case, but if there happens to be
multiple defs then it will assert.
This fixes PR42129.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362666
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 5 Jun 2019 22:37:50 +0000 (22:37 +0000)]
AMDGPU: Don't fix emergency stack slot at offset 0
This forced the caller to be aware of this, which is an ugly ABI
feature.
Partially reverts r295877. The original reasons for doing this are
mostly fixed. Alloca is now in a non-0 address space, so it should be
OK to have 0 as a valid pointer. Since we treat the absolute address
as the pointer value, this part only really needed to apply to
kernels.
Since r357093, we avoid the need to increment/decrement the offset
register in more cases, and since r354816 the scavenger can fail
without spilling, so it's less critical that we try to avoid an offset
that fits in the MUBUF offset.
Restrict to callable functions for now to split this into 2 steps to
limit thte number of test updates and in case anything breaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362665
91177308-0d34-0410-b5e6-
96231b3b80d8
Cameron McInally [Wed, 5 Jun 2019 22:37:05 +0000 (22:37 +0000)]
[MSAN] Add unary FNeg visitor to the MemorySanitizer
Differential Revision: https://reviews.llvm.org/D62909
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362664
91177308-0d34-0410-b5e6-
96231b3b80d8
Ulrich Weigand [Wed, 5 Jun 2019 22:33:10 +0000 (22:33 +0000)]
Allow target to handle STRICT floating-point nodes
The ISD::STRICT_ nodes used to implement the constrained floating-point
intrinsics are currently never passed to the target back-end, which makes
it impossible to handle them correctly (e.g. mark instructions are depending
on a floating-point status and control register, or mark instructions as
possibly trapping).
This patch allows the target to use setOperationAction to switch the action
on ISD::STRICT_ nodes to Legal. If this is done, the SelectionDAG common code
will stop converting the STRICT nodes to regular floating-point nodes, but
instead pass the STRICT nodes to the target using normal SelectionDAG
matching rules.
To avoid having the back-end duplicate all the floating-point instruction
patterns to handle both strict and non-strict variants, we make the MI
codegen explicitly aware of the floating-point exceptions by introducing
two new concepts:
- A new MCID flag "mayRaiseFPException" that the target should set on any
instruction that possibly can raise FP exception according to the
architecture definition.
- A new MI flag FPExcept that CodeGen/SelectionDAG will set on any MI
instruction resulting from expansion of any constrained FP intrinsic.
Any MI instruction that is *both* marked as mayRaiseFPException *and*
FPExcept then needs to be considered as raising exceptions by MI-level
codegen (e.g. scheduling).
Setting those two new flags is straightforward. The mayRaiseFPException
flag is simply set via TableGen by marking all relevant instruction
patterns in the .td files.
The FPExcept flag is set in SDNodeFlags when creating the STRICT_ nodes
in the SelectionDAG, and gets inherited in the MachineSDNode nodes created
from it during instruction selection. The flag is then transfered to an
MIFlag when creating the MI from the MachineSDNode. This is handled just
like fast-math flags like no-nans are handled today.
This patch includes both common code changes required to implement the
new features, and the SystemZ implementation.
Reviewed By: andrew.w.kaylor
Differential Revision: https://reviews.llvm.org/D55506
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362663
91177308-0d34-0410-b5e6-
96231b3b80d8
Petr Hosek [Wed, 5 Jun 2019 22:27:31 +0000 (22:27 +0000)]
Revert "[AArch64][GlobalISel] Optimize G_FCMP + G_SELECT pairs when G_SELECT is fp"
This reverts commit r362435 as this triggers ICE, see PR42129 for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362662
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 5 Jun 2019 22:20:47 +0000 (22:20 +0000)]
AMDGPU: Invert frame index offset interpretation
Since the beginning, the offset of a frame index has been consistently
interpreted backwards. It was treating it as an offset from the
scratch wave offset register as a frame register. The correct
interpretation is the offset from the SP on entry to the function,
before the prolog. Frame index elimination then should select either
SP or another register as an FP.
Treat the scratch wave offset on kernel entry as the pre-incremented
SP. Rely more heavily on the standard hasFP and frame pointer
elimination logic, and clean up the private reservation code. This
saves a copy in most callee functions.
The kernel prolog emission code is still kind of a mess relying on
checking the uses of physical registers, which I would prefer to
eliminate.
Currently selection directly emits MUBUF instructions, which require
using a reference to some register. Use the register chosen for SP,
and then ignore this later. This should probably be cleaned up to use
pseudos that don't refer to any specific base register until frame
index elimination.
Add a workaround for shaders using large numbers of SGPRs. I'm not
sure these cases were ever working correctly, since as far as I can
tell the logic for figuring out which SGPR is the scratch wave offset
doesn't match up with the shader input initialization in the shader
programming guide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362661
91177308-0d34-0410-b5e6-
96231b3b80d8
Joseph Tremoulet [Wed, 5 Jun 2019 21:30:10 +0000 (21:30 +0000)]
[EarlyCSE] Add tests for negated min/max/abs [NFC]
Summary:
I'm planning to update the hashing logic to recognize their equivalence
in a subsequent change (D62644).
Reviewers: spatel
Reviewed By: spatel
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62918
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362657
91177308-0d34-0410-b5e6-
96231b3b80d8
Mircea Trofin [Wed, 5 Jun 2019 21:28:13 +0000 (21:28 +0000)]
[CallSite removal] Refactoring llvm::InlineFunction APIs
Summary:
This change only unifies the API previous API pair accepting
CallInst and InvokeInst, thus making it easier to refactor
inliner pass ode to CallBase. The implementation of the unified
API still relies on the CallSite implementation.
Reviewers: eraman, chandlerc, jdoerfert
Reviewed By: jdoerfert
Subscribers: jdoerfert, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62283
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362656
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 5 Jun 2019 21:26:52 +0000 (21:26 +0000)]
[InstCombine] simplify code for bitcast of insertelement; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362655
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 5 Jun 2019 21:15:52 +0000 (21:15 +0000)]
NewGVN: Handle addrspacecast
The AllConstant check needs to be moved out of the if/else if chain to
avoid a test regression. The "there is no SimplifyZExt" comment
puzzles me, since there is SimplifyCastInst. Additionally, the
Simplify* calls seem to not see the operand as constant, so this needs
to be tried if the simplify failed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362653
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 5 Jun 2019 21:00:31 +0000 (21:00 +0000)]
[X86] Fix mistake that marked VADDSSrrb_Int/VADDSDrrb_Int/VMULSSrrb_Int/VMULSDrrb_Int as commutable.
One of the sources controls the pass through value for the upper bits
of the result so we can't really commute it.
In practice this problem isn't a functional issue because we would
only try to commute this instruction in order to fold a load. But
we can't do embedded rounding and fold a load at the same time. So
the load fold would never succeed so I don't think we would ever
commute or at least keep the version after commuting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362647
91177308-0d34-0410-b5e6-
96231b3b80d8
Whitney Tsang [Wed, 5 Jun 2019 20:42:47 +0000 (20:42 +0000)]
[LOOPINFO] Extend Loop object to add utilities to get the loop bounds,
step, and loop induction variable.
Summary: This PR extends the loop object with more utilities to get loop
bounds, step, and loop induction variable. There already exists passes
which try to obtain the loop induction variable in their own pass, e.g.
loop interchange. It would be useful to have a common area to get these
information.
/// Example:
/// for (int i = lb; i < ub; i+=step)
/// <loop body>
/// --- pseudo LLVMIR ---
/// beforeloop:
/// guardcmp = (lb < ub)
/// if (guardcmp) goto preheader; else goto afterloop
/// preheader:
/// loop:
/// i1 = phi[{lb, preheader}, {i2, latch}]
/// <loop body>
/// i2 = i1 + step
/// latch:
/// cmp = (i2 < ub)
/// if (cmp) goto loop
/// exit:
/// afterloop:
///
/// getBounds
/// getInitialIVValue --> lb
/// getStepInst --> i2 = i1 + step
/// getStepValue --> step
/// getFinalIVValue --> ub
/// getCanonicalPredicate --> '<'
/// getDirection --> Increasing
/// getInductionVariable --> i1
/// getAuxiliaryInductionVariable --> {i1}
/// isCanonical --> false
Reviewers: kbarton, hfinkel, dmgreen, Meinersbur, jdoerfert, syzaara,
fhahn
Reviewed By: kbarton
Subscribers: tvvikram, bmahjour, etiotto, fhahn, jsji, hiraditya,
llvm-commits
Tag: LLVM
Differential Revision: https://reviews.llvm.org/D60565
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362644
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Wed, 5 Jun 2019 20:38:17 +0000 (20:38 +0000)]
InstCombine: correctly change byval type attribute alongside call args.
When the byval attribute has a type, it must match the pointee type of
any parameter; but InstCombine was not updating the attribute when
folding casts of various kinds away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362643
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Wed, 5 Jun 2019 20:37:47 +0000 (20:37 +0000)]
IR: make getParamByValType Just Work. NFC.
Most parts of LLVM don't care whether the byval type is derived from an
explicit Attribute or from the parameter's pointee type, so it makes
sense for the main access function to just return the right value.
The very few users who do care (only BitcodeReader so far) can find out
how it's specified by accessing the Attribute directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362642
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 5 Jun 2019 20:32:32 +0000 (20:32 +0000)]
AMDGPU: Remove amdgpu-max-work-group-size attribute
This has been deprecated for a long time, and mesa recently switched
to amdgpu-flat-work-group-size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362641
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 5 Jun 2019 20:32:25 +0000 (20:32 +0000)]
AMDGPU: Fix using 2 different enums for same operand flags
These enums are really for the same namespace of flags set on
arbitrary MachineOperands, so merge them to avoid value collisions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362640
91177308-0d34-0410-b5e6-
96231b3b80d8
Dan Gohman [Wed, 5 Jun 2019 20:01:01 +0000 (20:01 +0000)]
[WebAssembly] Limit PIC support to the Emscripten target
The current PIC support currently only works with Emscripten, so
disable it for other targets.
This is the PIC portion of https://reviews.llvm.org/D62542.
Reviewed By: dschuff, sbc100
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362638
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 5 Jun 2019 18:55:54 +0000 (18:55 +0000)]
[X86][SSE] Add vector tests to cover more isNegatibleForFree/GetNegatedExpression cases (PR42105)
Some already combine correctly, but vector constant analysis is weak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362633
91177308-0d34-0410-b5e6-
96231b3b80d8
Cameron McInally [Wed, 5 Jun 2019 18:50:07 +0000 (18:50 +0000)]
[NFC][Reassociate] Fix mistake in
468b2ad
Missed 2 'fast fsub(0.0,X) -> fneg(X)' changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362631
91177308-0d34-0410-b5e6-
96231b3b80d8
Cameron McInally [Wed, 5 Jun 2019 18:35:54 +0000 (18:35 +0000)]
[NFC][Reassociate] Add unary fneg tests to fast-basictest.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362630
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 5 Jun 2019 18:25:09 +0000 (18:25 +0000)]
[X86] Add the vector integer min/max instructions to isAssociativeAndCommutative.
As far as I know these should be freely reassociatable just like
the floating point MAXC/MINC instructions.
The *reduce* test changes are largely regressions and caused by
the "generic" CPU we default to not having a scheduler model.
The machine-combiner-int-vec.ll test shows the positive benefits
of this change.
Differential Revision: https://reviews.llvm.org/D62787
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362629
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Wed, 5 Jun 2019 18:00:59 +0000 (18:00 +0000)]
[Tests] Add poison inference tests for indvars showing both existing transforms, and some room for improvement
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362628
91177308-0d34-0410-b5e6-
96231b3b80d8
Cameron McInally [Wed, 5 Jun 2019 18:00:27 +0000 (18:00 +0000)]
[NFC][Reassociate] Regenerate CHECKs for fast-basictest.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362627
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 5 Jun 2019 17:26:29 +0000 (17:26 +0000)]
Fix shadow local variable warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362622
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Wed, 5 Jun 2019 17:14:32 +0000 (17:14 +0000)]
[dsymutil] Support more than 4 architectures
When running dsymutil on a fat binary, we use temporary files in a small
vector of size four. When processing more than 4 architectures, this
resulted in a user-after-move, because the temporary files got moved to
the heap. Instead of storing an optional temp file, we now use a unique
pointer, so the location of the actual temp file doesn't change.
We could test this by checking in 5 binaries for 5 different
architectures, but this seems wasteful, especially since the number of
elements in the small vector is arbitrary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362621
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 5 Jun 2019 16:40:57 +0000 (16:40 +0000)]
[x86] split more 256-bit stores of concatenated vectors
As suggested in D62498 - collectConcatOps() matches both
concat_vectors and insert_subvector patterns, and we see
more test improvements by using the more general match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362620
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 5 Jun 2019 16:14:14 +0000 (16:14 +0000)]
[X86][AVX] Generalize split256BitStore to splitVectorStore. NFCI.
Enables us to use this to split 512-bit vectors in future patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362617
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 5 Jun 2019 16:11:57 +0000 (16:11 +0000)]
[X86][SSE] Add additional nt-load test cases as discussed on D62910
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362616
91177308-0d34-0410-b5e6-
96231b3b80d8
Whitney Tsang [Wed, 5 Jun 2019 15:32:56 +0000 (15:32 +0000)]
Revert "Title: [LOOPINFO] Extend Loop object to add utilities to get the loop"
This reverts commit
d34797dfc26c61cea19f45669a13ea572172ba34.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362615
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Wed, 5 Jun 2019 15:29:50 +0000 (15:29 +0000)]
[llvm-readobj] - Remove TODOs from gnu-hash-symbols.test and demangle.test test cases.
We can remove this TODOs now.
Differential revision: https://reviews.llvm.org/D62846
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362614
91177308-0d34-0410-b5e6-
96231b3b80d8
Dinar Temirbulatov [Wed, 5 Jun 2019 15:26:28 +0000 (15:26 +0000)]
[SLP] Fix regression in broadcasts caused by operand reordering patch D59973.
This patch fixes a regression caused by the operand reordering refactoring patch https://reviews.llvm.org/D59973 .
The fix changes the strategy to Splat instead of Opcode, if broadcast opportunities are found.
Please see the lit test for some examples.
Committed on behalf of @vporpo (Vasileios Porpodas)
Differential Revision: https://reviews.llvm.org/D62427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362613
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 5 Jun 2019 14:58:04 +0000 (14:58 +0000)]
[LoopUtils][SLPVectorizer] clean up management of fast-math-flags
Instead of passing around fast-math-flags as a parameter, we can set those
using an IRBuilder guard object. This is no-functional-change-intended.
The motivation is to eventually fix the vectorizers to use and set the
correct fast-math-flags for reductions. Examples of that not behaving as
expected are:
https://bugs.llvm.org/show_bug.cgi?id=23116 (should be able to reduce with less than 'fast')
https://bugs.llvm.org/show_bug.cgi?id=35538 (possible miscompile for -0.0)
D61802 (should be able to reduce with IR-level FMF)
Differential Revision: https://reviews.llvm.org/D62272
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362612
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Wed, 5 Jun 2019 14:43:58 +0000 (14:43 +0000)]
[LoopInfo] Fix unused variable warning. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362610
91177308-0d34-0410-b5e6-
96231b3b80d8
Whitney Tsang [Wed, 5 Jun 2019 14:34:12 +0000 (14:34 +0000)]
Title: [LOOPINFO] Extend Loop object to add utilities to get the loop
bounds, step, and loop induction variable.
Summary: This PR extends the loop object with more utilities to get loop
bounds, step, and loop induction variable. There already exists passes
which try to obtain the loop induction variable in their own pass, e.g.
loop interchange. It would be useful to have a common area to get these
information.
/// Example:
/// for (int i = lb; i < ub; i+=step)
/// <loop body>
/// --- pseudo LLVMIR ---
/// beforeloop:
/// guardcmp = (lb < ub)
/// if (guardcmp) goto preheader; else goto afterloop
/// preheader:
/// loop:
/// i1 = phi[{lb, preheader}, {i2, latch}]
/// <loop body>
/// i2 = i1 + step
/// latch:
/// cmp = (i2 < ub)
/// if (cmp) goto loop
/// exit:
/// afterloop:
///
/// getBounds
/// getInitialIVValue --> lb
/// getStepInst --> i2 = i1 + step
/// getStepValue --> step
/// getFinalIVValue --> ub
/// getCanonicalPredicate --> '<'
/// getDirection --> Increasing
/// getInductionVariable --> i1
/// getAuxiliaryInductionVariable --> {i1}
/// isCanonical --> false
Reviewers: kbarton, hfinkel, dmgreen, Meinersbur, jdoerfert, syzaara,
fhahn
Reviewed By: kbarton
Subscribers: tvvikram, bmahjour, etiotto, fhahn, jsji, hiraditya,
llvm-commits
Tag: LLVM
Differential Revision: https://reviews.llvm.org/D60565
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362609
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 5 Jun 2019 14:08:11 +0000 (14:08 +0000)]
[NFC][Codegen][X86] Add AVX2 runline for '(X & (C l>> Y)) ==/!= 0' tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362606
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 5 Jun 2019 14:08:01 +0000 (14:08 +0000)]
UpdateTestChecks: hexagon support
Summary:
These tests are being affected by an upcoming patch,
so having an understandable (autogenerated) diff is helpful.
This target, again, prefers `-march`:
```
llvm/test/CodeGen/Hexagon$ grep -r triple | wc -l
467
llvm/test/CodeGen/Hexagon$ grep -r march | wc -l
1167
```
Reviewers: RKSimon, kparzysz
Reviewed By: kparzysz
Subscribers: xbolva00, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362605
91177308-0d34-0410-b5e6-
96231b3b80d8
Petar Avramovic [Wed, 5 Jun 2019 14:03:13 +0000 (14:03 +0000)]
[MIPS GlobalISel] Select fcmp
Select floating point compare for MIPS32.
Differential Revision: https://reviews.llvm.org/D62721
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362603
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Wed, 5 Jun 2019 13:16:53 +0000 (13:16 +0000)]
[yaml2obj] - Change how we handle implicit sections.
We have a few sections that can be added implicitly to the output:
".dynsym", ".dynstr", ".symtab", ".strtab" and ".shstrtab".
Problem appears when such section is listed explicitly in YAML.
In that case it's content is written twice:
first time during writing of regular sections listed in the document
and second time during special handling.
Because of that their file offsets can become unexpectedly broken:
(yaml file for sample below lists .dynsym explicitly before .text.foo)
Before patch:
[Nr] Name Type Address Offset
Size EntSize Flags Link Info Align
[ 0] NULL
0000000000000000 00000000
0000000000000000 0000000000000000 0 0 0
[ 1] .dynsym DYNSYM
0000000000000100 00000250
0000000000000030 0000000000000018 A 6 0 8
[ 2] .text.foo PROGBITS
0000000000000200 00000200
0000000000000000 0000000000000000 AX 0 0 0
After patch:
Section Headers:
[Nr] Name Type Address Offset
Size EntSize Flags Link Info Align
[ 0] NULL
0000000000000000 00000000
0000000000000000 0000000000000000 0 0 0
[ 1] .dynsym DYNSYM
0000000000000100 00000200
0000000000000030 0000000000000018 A 6 0 8
[ 2] .text.foo PROGBITS
0000000000000200 00000230
0000000000000000 0000000000000000 AX 0 0 0
This patch reorganizes our code and fixes the issue described.
Differential revision: https://reviews.llvm.org/D62809
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362602
91177308-0d34-0410-b5e6-
96231b3b80d8
Sjoerd Meijer [Wed, 5 Jun 2019 13:11:51 +0000 (13:11 +0000)]
[ARM] Allow "-march=foo+fp" to vary with foo
This is the LLVM part of this change, the Clang part contains the full
description in its commit message.
Differential Revision: https://reviews.llvm.org/D60697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362600
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 5 Jun 2019 12:56:53 +0000 (12:56 +0000)]
[X86][AVX] combineX86ShuffleChain - combine shuffle(extractsubvector(x),extractsubvector(y))
We already handle the case where we combine shuffle(extractsubvector(x),extractsubvector(x)), this relaxes the requirement to permit different sources as long as they have the same value type.
This causes a couple of cases where the VPERMV3 binary shuffles occur at a wider width than before, which I intend to improve in future commits - but as only the subvector's mask indices are defined, these will broadcast so we don't see any increase in constant size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362599
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Wed, 5 Jun 2019 12:05:54 +0000 (12:05 +0000)]
gn build: Merge r362578
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362598
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Wed, 5 Jun 2019 11:37:53 +0000 (11:37 +0000)]
[llvm-objdump] - Disassemble non-executable sections if specifically requested.
This is https://bugs.llvm.org/show_bug.cgi?id=41897.
Previously -d + -j .data had no effect, that wasn't consistent with GNU,
which proccesses .data in that case. With this patch we follow this behavior.
Diffeential revision: https://reviews.llvm.org/D62848
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362596
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 5 Jun 2019 10:59:04 +0000 (10:59 +0000)]
[TargetLowering] SimplifyDemandedBits - pull out shift value type. NFCI.
Will be used more in an upcoming patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362595
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 5 Jun 2019 10:55:55 +0000 (10:55 +0000)]
[X86][SSE] Add some nt-store test cases inspired by PR42123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362594
91177308-0d34-0410-b5e6-
96231b3b80d8
Serge Guelton [Wed, 5 Jun 2019 10:32:28 +0000 (10:32 +0000)]
Sanitize llvm-size help
Remove irrelevant options from standard help output.
New output:
OVERVIEW: llvm object size dumper
USAGE: llvm-size [options] <input files>
OPTIONS:
Generic Options:
--help - Display available options (--help-hidden for more)
--help-list - Display list of available options (--help-list-hidden for more)
--version - Display the version of this program
llvm-size Options:
Specify output format
-A - System V format
-B - Berkeley format
-m - Darwin -m format
--arch=<string> - architecture(s) from a Mach-O file to dump
--common - Print common symbols in the ELF file. When using Berkely format, this is added to bss.
Print size in radix:
-o - Print size in octal
-d - Print size in decimal
-x - Print size in hexadecimal
--format=<value> - Specify output format
=sysv - System V format
=berkeley - Berkeley format
=darwin - Darwin -m format
-l - When format is darwin, use long format to include addresses and offsets.
--radix=<value> - Print size in radix
=8 - Print size in octal
=10 - Print size in decimal
=16 - Print size in hexadecimal
--totals - Print totals of all objects - Berkeley format only
Differential Revision: https://reviews.llvm.org/D62482
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362593
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 5 Jun 2019 10:04:05 +0000 (10:04 +0000)]
[IPO] Disabled 'default only' switch statements to fix MSVC warnings.
@jdoerfert Looks like these are placeholders for incoming abstract attributes patches so I've just commented the code out, even though this is usually frowned upon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362592
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Wed, 5 Jun 2019 08:58:00 +0000 (08:58 +0000)]
Include what you use in PPCFrameLowering.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362590
91177308-0d34-0410-b5e6-
96231b3b80d8
Stefan Granitz [Wed, 5 Jun 2019 08:29:24 +0000 (08:29 +0000)]
[CMake] Export CMAKE_CONFIGURATION_TYPES for the LLVM build-tree
Summary: Useful info for standalone builds of subprojects. If a multi-configuration generator was used for the provided LLVM build-tree, standalone builds should consider actual subdirectories per configuration in `find_program()` (e.g. looking for `llvm-lit` or `llvm-tblgen`).
Reviewers: labath, beanz, mgorny
Subscribers: lldb-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362588
91177308-0d34-0410-b5e6-
96231b3b80d8
Yevgeny Rouban [Wed, 5 Jun 2019 05:46:40 +0000 (05:46 +0000)]
Resubmit "[CorrelatedValuePropagation] Fix prof branch_weights metadata handling for SwitchInst"
This reverts commit
5b32f60ec31ce136edac6f693538aeb6039f4ad0.
The fix is in commit
4f9e68148bd0dada2d6997625432385918ac2e2c.
This patch fixes the CorrelatedValuePropagation pass to keep
prof branch_weights metadata of SwitchInst consistent.
It makes use of SwitchInstProfUpdateWrapper.
New tests are added.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D62126
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362583
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Liao [Wed, 5 Jun 2019 04:18:12 +0000 (04:18 +0000)]
Suppress false-positive GCC -Wreturn-type warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362582
91177308-0d34-0410-b5e6-
96231b3b80d8
Rui Ueyama [Wed, 5 Jun 2019 03:04:46 +0000 (03:04 +0000)]
Read .note.gnu.property sections and emit a merged .note.gnu.property section.
This patch also adds `--require-cet` option for the sake of testing.
The actual feature for IBT-aware PLT is not included in this patch.
This is a part of https://reviews.llvm.org/D59780. Submitting this
first should make it easy to work with a related change
(https://reviews.llvm.org/D62609).
Differential Revision: https://reviews.llvm.org/D62853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362579
91177308-0d34-0410-b5e6-
96231b3b80d8
Johannes Doerfert [Wed, 5 Jun 2019 03:02:24 +0000 (03:02 +0000)]
[Attributor] Pass infrastructure and fixpoint framework
NOTE: Note that no attributes are derived yet. This patch will not go in
alone but only with others that derive attributes. The framework is
split for review purposes.
This commit introduces the Attributor pass infrastructure and fixpoint
iteration framework. Further patches will introduce abstract attributes
into this framework.
In a nutshell, the Attributor will update instances of abstract
arguments until a fixpoint, or a "timeout", is reached. Communication
between the Attributor and the abstract attributes that are derived is
restricted to the AbstractState and AbstractAttribute interfaces.
Please see the file comment in Attributor.h for detailed information
including design decisions and typical use case. Also consider the class
documentation for Attributor, AbstractState, and AbstractAttribute.
Reviewers: chandlerc, homerdin, hfinkel, fedor.sergeev, sanjoy, spatel, nlopes, nicholas, reames
Subscribers: mehdi_amini, mgorny, hiraditya, bollu, steven_wu, dexonsmith, dang, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59918
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362578
91177308-0d34-0410-b5e6-
96231b3b80d8
Johannes Doerfert [Wed, 5 Jun 2019 03:00:06 +0000 (03:00 +0000)]
[NFC][FnAttrs] Stress tests for attribute deduction
This commit is a preparation of upcoming patches on attribute deduction.
It will shorten the diffs and make it clear what we inferred before.
Reviewers: chandlerc, homerdin, hfinkel, fedor.sergeev, sanjoy, spatel, nlopes
Subscribers: bollu, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59903
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362577
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Wed, 5 Jun 2019 02:36:40 +0000 (02:36 +0000)]
[PowerPC] Collapse RLDICL/RLDICR into RLDIC when possible
Generally speaking, we lower to an optimal rotate sequence for nodes visible in
the SDAG. However, there are instances where the two rotates are not visible at
ISEL time - most notably those in a very common sequence when lowering switch
statements to jump tables.
A common situation is a switch on a 32-bit integer. This value has to have the
upper 32 bits cleared and because jump table offsets are word offsets, the value
needs to be shifted left by 2 bits. We currently emit the clear and the left
shift as two separate instructions, but this is not needed as we can lower it to
a single RLDIC.
This patch just cleans that up.
Differential revision: https://reviews.llvm.org/D60402
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362576
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Wed, 5 Jun 2019 02:09:03 +0000 (02:09 +0000)]
[PowerPC][NFC] Add codegen test for consecutive stores of vector elements
NFC commit of a test case in order for the subsequent review to show differences
in codegen.
Differential revision: https://reviews.llvm.org/D62843
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362573
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Wed, 5 Jun 2019 01:36:48 +0000 (01:36 +0000)]
[llvm-objdump/llvm-readobj/obj2yaml/yaml2obj] Support DT_PPC_GOT and DT_PPC_OPT
In glibc, DT_PPC_GOT indicates that PowerPC32 Secure PLT ABI is used.
I plan to use it in D62464.
DT_PPC_OPT currently indicates if a TLSDESC inspired TLS optimization is
enabled.
Reviewed By: grimar, jhenderson, rupprecht
Differential Revision: https://reviews.llvm.org/D62851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362569
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Wed, 5 Jun 2019 01:31:43 +0000 (01:31 +0000)]
Initial support for IBM MASS vector library
This is the LLVM portion of patch https://reviews.llvm.org/D59881.
The clang portion is to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362568
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Desaulniers [Wed, 5 Jun 2019 01:28:55 +0000 (01:28 +0000)]
[TargetTransformInfo] assert on nullptr
Summary:
This was flagged in https://www.viva64.com/en/b/0629/ under "Snippet No.
38".
Add an assertion, since it's unlikely that this parameter is nullptr.
Reviewers: RKSimon, fhahn
Reviewed By: RKSimon
Subscribers: fhahn, llvm-commits, RKSimon, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362567
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 5 Jun 2019 01:00:34 +0000 (01:00 +0000)]
[X86] Cleanup convertIntLogicToFPLogic a little. NFCI
-Use early returns to reduce indentation
-Replace multipe ifs with a switch.
-Replace an assert with an llvm_unreachable default in the switch.
-Check that the FP type we're going to use for the
X86ISD::FAND/FOR/FXOR is legal rather than checking that the
integer type matches the width of a legal scalar fp type. This all
runs after legalization so it shouldn't really matter, but making
sure we're using a valid type in the X86ISD node is really
whats important.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362565
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 4 Jun 2019 23:35:07 +0000 (23:35 +0000)]
svn propset svn:executable on utils/prepare-code-coverage-artifact.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362561
91177308-0d34-0410-b5e6-
96231b3b80d8
Amara Emerson [Tue, 4 Jun 2019 23:11:42 +0000 (23:11 +0000)]
[AArch64] FastISel: fix test to specify -fast-isel when -fast-isel-abort=1 is used.
This test has been inadvertently been GISel, and now assert due to incompatible flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362559
91177308-0d34-0410-b5e6-
96231b3b80d8
Cameron McInally [Tue, 4 Jun 2019 23:01:36 +0000 (23:01 +0000)]
[Scalarizer] Add UnaryOperator visitor to scalarization pass
Differential Revision: https://reviews.llvm.org/D62858
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362558
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Brachet [Tue, 4 Jun 2019 22:17:27 +0000 (22:17 +0000)]
[test][llvm-objcopy] Test llvm-objcopy with standard streams
Differential Revision: https://reviews.llvm.org/D62817
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362556
91177308-0d34-0410-b5e6-
96231b3b80d8
Amara Emerson [Tue, 4 Jun 2019 21:51:34 +0000 (21:51 +0000)]
[AArch64][GlobalISel] Make extloads to i64 legal.
Although we had the support in the prelegalizer combiner to generate the
G_SEXTLOAD or G_ZEXTLOAD ops, the legalizer definitions for arm64 had them as
lowering back to separate ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362553
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 4 Jun 2019 21:47:50 +0000 (21:47 +0000)]
[X86] Add avx512bw to the avx512 machine-combiner-int-vec.ll to ensure we use zmm for v32i16/v64i8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362552
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 4 Jun 2019 21:26:46 +0000 (21:26 +0000)]
[X86] Add vector min/max reassociation tests to machine-combiner-int-vec.ll. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362550
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 4 Jun 2019 21:26:36 +0000 (21:26 +0000)]
[X86] Add 512-bit test cases to machine-combiner-int-vec.ll. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362549
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Tue, 4 Jun 2019 21:08:20 +0000 (21:08 +0000)]
[WebAssembly] Fix ISel crash on sext_inreg/extract type mismatch
Summary:
Adjusts the index and adds a bitcast around the vector operand of
EXTRACT_VECTOR_ELT so that its lane type matches the source type of
its parent sext_inreg. Without this bitcast the ISel patterns do not
match and ISel fails.
Reviewers: aheejin
Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62646
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362547
91177308-0d34-0410-b5e6-
96231b3b80d8
Johannes Doerfert [Tue, 4 Jun 2019 20:34:43 +0000 (20:34 +0000)]
[SelectionDAG][FIX] Allow "returned" arguments to be bit-casted
Summary:
An argument that is return by a function but bit-casted before can still
be annotated as "returned". Make sure we do not crash for this case.
Reviewers: sunfish, stephenwlin, niravd, arsenm
Subscribers: wdng, hiraditya, bollu, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59917
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362546
91177308-0d34-0410-b5e6-
96231b3b80d8
Johannes Doerfert [Tue, 4 Jun 2019 20:21:46 +0000 (20:21 +0000)]
Introduce Value::stripPointerCastsSameRepresentation
This patch allows current users of Value::stripPointerCasts() to force
the result of the function to have the same representation as the value
it was called on. This is useful in various cases, e.g., (non-)null
checks.
In this patch only a single call site was adjusted to fix an existing
misuse that would cause nonnull where they may be wrong. Uses in
attribute deduction and other areas, e.g., D60047, are to be expected.
For a discussion on this topic, please see [0].
[0] http://lists.llvm.org/pipermail/llvm-dev/2018-December/128423.html
Reviewers: hfinkel, arsenm, reames
Subscribers: wdng, hiraditya, bollu, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61607
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362545
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 4 Jun 2019 19:10:08 +0000 (19:10 +0000)]
llvm-undname: Correctly demangle vararg parameters
FunctionSignatureNode already had an IsVariadic field,
but it wasn't used anywhere yet. Set it and use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362541
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 4 Jun 2019 18:49:05 +0000 (18:49 +0000)]
llvm-undname: More coverage-related cleanups
- The loop in demangleFunctionParameterList() only exits
on Error, @, and Z. All 3 cases were handled, so the
rest of the function is DEMANGLE_UNREACHABLE.
- The loop in demangleTemplateParameterList() always returns
on Error, so there's no need to check for that in the loop
header and after the loop.
- Add test cases for invalid function parameter manglings.
- Add a (redundant) test case for a simple template parameter
list mangling.
- Add a test case pointing out that varargs functions aren't
demangled correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362540
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Tue, 4 Jun 2019 18:48:43 +0000 (18:48 +0000)]
Revert r362472 as it is breaking PPC build bots
The patch https://reviews.llvm.org/rL362472 broke PPC LNT buildbots.
Reverting it to bring the bots back to green.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362539
91177308-0d34-0410-b5e6-
96231b3b80d8
Alina Sbirlea [Tue, 4 Jun 2019 18:45:15 +0000 (18:45 +0000)]
[Utils] Clean another duplicated util method.
Summary:
Following the cleanup in D48202, method foldBlockIntoPredecessor has the
same behavior. Replace its uses with MergeBlockIntoPredecessor.
Remove foldBlockIntoPredecessor.
Reviewers: chandlerc, dmgreen
Subscribers: jlebar, javed.absar, zzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62751
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362538
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 4 Jun 2019 18:06:28 +0000 (18:06 +0000)]
llvm-undname: Add test coverage for demangleInitFiniStub()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362536
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 4 Jun 2019 18:03:07 +0000 (18:03 +0000)]
[X86] Mutate fceil/ffloor/ftrunc/fnearbyint/frint into X86ISD::RNDSCALE during PreProcessIselDAG to cut down on pattern permutations
We already need to have patterns for X86ISD::RNDSCALE to support software intrinsics. But we currently have 5 sets of patterns for the 5 rounding operations. For of these 6 patterns we have to support 3 vectors widths, 2 element sizes, sse/vex/evex encodings, load folding, and broadcast load folding. This results in a fair amount of bytes in the isel table.
This patch adds code to PreProcessIselDAG to morph the fceil/ffloor/ftrunc/fnearbyint/frint to X86ISD::RNDSCALE. This way we can remove everything, but the intrinsic pattern while still allowing the operations to be considered Legal for DAGCombine and Legalization. This shrinks the DAGISel by somewhere between 9K and 10K.
There is one complication to this, the STRICT versions of these nodes are currently mutated to their none strict equivalents at isel time when the node is visited. This won't be true in the future since that loses the chain ordering information. For now I've also added support for the non-STRICT nodes to Select so we can change the STRICT versions there after they've been mutated to their non-STRICT versions. We'll probably need a STRICT version of RNDSCALE or something to handle this in the future. Which will take us back to needing 2 sets of patterns for strict and non-strict, but that's still better than the 11 or 12 sets of patterns we'd need.
We can probably do something similar for scalar, but I haven't looked at it yet.
Differential Revision: https://reviews.llvm.org/D62757
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362535
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Tue, 4 Jun 2019 18:01:07 +0000 (18:01 +0000)]
[X86] Fold single-use variable into assert. NFC.
Avoids an unused variable warning in Release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362534
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 4 Jun 2019 17:44:18 +0000 (17:44 +0000)]
[DAGCombiner][X86] Fold (not (neg X)) -> (add X, -1)
This is a special case of a more general transform (not (sub Y, X)) -> (add X, ~Y). InstCombine knows the general form. I've restricted to the special case to fix the motivating case PR42118. I tried handling any case where Y was constant, but got some changes on some Mips tests that I couldn't quickly prove where beneficial.
Fixes PR42118
Differential Revision: https://reviews.llvm.org/D62828
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362533
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Tue, 4 Jun 2019 17:29:55 +0000 (17:29 +0000)]
[Tests] Autogen a test so future changes are visible
Oddly, I had to change a value name from "tmp0" to "bc0" to get the autogened test to pass. I'm putting this down to an oddity of update_test_checks or FileCheck, but don't understand it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362532
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 4 Jun 2019 17:05:34 +0000 (17:05 +0000)]
[NFC][Codegen][PowerPC] Autogenerate shift-cmp.ll test
Being affected by upcoming patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362529
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 4 Jun 2019 17:05:06 +0000 (17:05 +0000)]
[NFC][Codegen][AMDGPU] Autogenerate commute-shifts.ll test
Being affected by upcoming patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362528
91177308-0d34-0410-b5e6-
96231b3b80d8