OSDN Git Service
Chinmay Sawarkar [Wed, 20 Apr 2016 03:16:50 +0000 (20:16 -0700)]
defconfig: msm64: msm: Enable v4l2 video driver
Enable v4l2 video driver on msmcobalt for decode
and encode sessions.
Change-Id: Ibda63abad6a469c0a5f738c51ee1e740d0f1ce7a
Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
Vikash Garodia [Sat, 14 May 2016 00:43:26 +0000 (17:43 -0700)]
ARM: dts: msm: Enable VMEM node
Enable VMEM node and configure the
size as per msmcobalt.
CRs-Fixed:
1008076
Change-Id: I8bbb827e6fcddb12bf452279f5f7d60b614c2915
Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
Shashank Mittal [Tue, 3 May 2016 19:54:13 +0000 (12:54 -0700)]
defconfig: arm64: enable common log driver for msmcobalt
Common log driver can be used to register entries for memory dump table.
Change-Id: I75be0d467c8f7c2db854987598770f9798688e51
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Shashank Mittal [Tue, 3 May 2016 19:47:16 +0000 (12:47 -0700)]
defconfig: arm64: enable DCC device driver
Set MSM_DCC config to enable support for Data Capture and Compare(DCC)
device.
Change-Id: Ibc2de3c142b8df4ac86e4628199726750f19dac3
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Shashank Mittal [Thu, 25 Feb 2016 19:24:09 +0000 (11:24 -0800)]
memory-dump: add support to allocate memory for scan dumps
Add support to allocate memory for CPU scan dumps. This momeory can be
used to save CPU scan dumps at the time of a crash.
Change-Id: I9d644f18882729d187075e885bc2e8c02c5caf36
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Shashank Mittal [Thu, 10 Mar 2016 22:31:29 +0000 (14:31 -0800)]
ARM: dts: msm: add DCC device on msmcobalt
Add node to add support for Data Capture and Compare (DCC) device on
msmcobalt.
DCC block can be used to capture user programmed memory mapped registers
or to run CRC on user programmed memory region.
Change-Id: I1d302e51693315998d915ca44f739fb58ef9e4a5
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Sureshnaidu Laveti [Fri, 13 May 2016 23:48:38 +0000 (16:48 -0700)]
ARM: dts: msm: Add clock rates in camera node for all boards
Adding clock rates to camera node instead of statically
reading from sensor driver so that clock names and
rates can be read from camera node using common software on chip
API and if needed it can be overrided with the values obtained from
userspace sensor drivers.
Change-Id: Icf950194191cbd0887740d692bb88cc650430fb8
Signed-off-by: Sureshnaidu Laveti <lsuresh@codeaurora.org>
Xiaogang Cui [Fri, 9 Oct 2015 08:33:08 +0000 (16:33 +0800)]
soc: qcom: dcc: add check if sram data oversteps
If the size of captured data oversteps over SRAM boundary then
it causes corruption of configuration data. Add boundary check
while programming configuration linked list in SRAM, to avoid
this problem.
Change-Id: Idd33f53560585fdbfee4d3822fd93d6f3a365e17
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Xiaogang Cui [Thu, 5 Nov 2015 06:00:36 +0000 (11:30 +0530)]
soc: qcom: dcc: update errno of dcc probe failure
Acorrding to function really_probe, the ENODEV will not throw
any error message. Changing ENODEV to EINVAL to notify error
message if probe fails.
Change-Id: Ia3187fadd4f0073e5e141595810bb8b3c7aab429
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Xiaogang Cui [Fri, 16 Oct 2015 09:16:22 +0000 (17:16 +0800)]
soc: qcom: dcc: update xpu probe logic to fix failure
TZ image which has registered SCM_SVC_DISABLE_XPU sevice maybe used by
none-dcc-xpu device. Update the xpu check logic to fix the probe
failure issue.
Change-Id: Id2b38d93e7c12648292546592144eda1e82d76be
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Shashank Mittal [Wed, 24 Jun 2015 00:11:22 +0000 (17:11 -0700)]
soc: qcom: dcc: add support for DCC XPU lock/unlock request
Add support to request TZ to lock and unlock DCC XPU.
DCC XPU is unlocked before accessing DCC and is locked back again after
configuring DCC.
Change-Id: I8815f65551df0b80f7ecdcaa338a50db8d9b04f5
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Ram Chandrasekar [Wed, 11 May 2016 18:43:42 +0000 (12:43 -0600)]
ARM: dts: msm: Disable LMH driver probe for msmhamster rumi
Tsens controller wont be able to send any temperature data in RUMI.
This will block LMH driver in HLOS during profile switch.
Disable LMH driver probe for RUMI to avoid this profile switch.
CRs-Fixed:
1015361
Change-Id: I729af5235109cf8b09d4c89a339a4b4f14926d26
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Shashank Mittal [Wed, 20 May 2015 22:30:13 +0000 (15:30 -0700)]
soc: qcom: dcc: replace readx_poll_timeout with readl_poll_timeout
Use readl_poll_timeout instead of readx_poll_timeout because
readl_poll_timeout already uses __raw_readl to read IO register.
Change-Id: I86d93bc63cf3282e360eed29732a708ee02cf6df
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Shashank Mittal [Thu, 14 May 2015 00:01:45 +0000 (17:01 -0700)]
soc: qcom: dcc: change configuration programming interface
Currently user needs to provide base, offset, and length to program
a configuration in DCC.
To simplify user input, this change requires user to provide just start
address and length. Driver is going to calculate most optimized base,
offset and length to configure user request in SRAM.
Change-Id: Ic1b7b2d4d4ed4baa9e8d33a2b60c10d2e799b211
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Shashank Mittal [Fri, 15 May 2015 03:03:07 +0000 (20:03 -0700)]
soc: qcom: dcc: add support to send SW trigger on/off req to RPM
Add support to request RPM to turn on/off DCC SW trigger.
This request can be used to enable/disable DDR training data verification
before DDR frequency switch.
After receiving enable request RPM assumes that DCC is configured in CRC
mode to verify DDR training data. Hence it starts to send SW trigger to
DCC to run CRC on configured data before DDR frequency switch.
Change-Id: I491bc3e41e11a5366162c65907f41f7cbcdd7809
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Shashank Mittal [Mon, 11 May 2015 21:57:24 +0000 (14:57 -0700)]
soc: qcom: dcc: add support for CRC mode
In CRC mode DCC can perform CRC on configuration data or system memory
after receiving SW or HW trigger.
Change-Id: Iab0a6ffa92ef6e311054756cfe85d1b2b91743c9
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Shashank Mittal [Fri, 15 May 2015 18:13:50 +0000 (11:13 -0700)]
soc: qcom: dcc: fix uninitialized variable bug in dcc_ll_cfg function
Fix bug due to use of uninitialized 'prev_off' variable.
Change-Id: I773f64209b395eb9f2fc82a53d4a2f1b79b081eb
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Shashank Mittal [Tue, 14 Apr 2015 01:39:59 +0000 (18:39 -0700)]
soc: qcom: dcc: add support for DCC driver
DCC (Data Capture and Compare) is a DMA engine which is used to save
configuration data or system memory contents during catastrophic failure
or SW trigger.
It can also perform CRC over the same configuration or memory space.
Change-Id: Ic8a804250ab8b7ac501bd186d2e6f7506bb9b21a
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Osvaldo Banuelos [Mon, 9 May 2016 18:55:24 +0000 (11:55 -0700)]
ARM: dts: msm: Enable Silver frequency scaling up to SVS on msmcobalt
Add the necessary frequency configuration to the OSM and CPUfreq
device nodes to allow frequency scaling of the Silver cluster in
msmcobalt to SVS Fmax.
Change-Id: I8153e1c2ad9cb320a4c116593b15898dbe2f6ca2
CRs-Fixed:
1014894
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Osvaldo Banuelos [Thu, 12 May 2016 00:24:17 +0000 (17:24 -0700)]
ARM: dts: msm: restrict VDD_APC voltages to NOM for CPR rev 0 on msmcobalt
Raise the VDD_APC0 and VDD_APC1 CPR floor voltages to be equal to
the Nominal ceiling voltage on CPR revision 0 parts. Also, increase
the number of supported fuse combos to 8, to support up to 8 CPR
revisions using a single speed bin. This ensures stable operation
on some msmcobalt CPR revision 0 parts that cannot operate
reliably with SVS2/SVS voltages and has no impact to CPR rev 1 and
greater parts.
Change-Id: I6913a168596b34f527f689360f93fdf15b7d2f10
CRs-Fixed:
1014782
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Adrian Salido-Moreno [Tue, 10 May 2016 19:15:44 +0000 (12:15 -0700)]
msm: mdss: account for multirect when enumerating pipe formats
The pipe format enumeration is not accounting for multi-rect on the
pipe list. Update the loop enumerating formats to account for multiple
rectangles per pipe.
Change-Id: Ief1980e2888525434e876f7cec4357403ca20cb1
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Joonwoo Park [Wed, 11 May 2016 22:05:57 +0000 (15:05 -0700)]
sched: use correct Kconfig macro name CONFIG_SCHED_HMP_CSTATE_AWARE
Fix macro name so CONFIG_SCHED_HMP_CSTATE_AWARE=y to take effect.
Change-Id: I0218b36b2d74974f50a173a0ac3bc59156c57624
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Puja Gupta [Tue, 10 May 2016 23:09:19 +0000 (16:09 -0700)]
soc: qcom: pil: Fix error path sequence
Fix the clock error path sequence.
CRs-Fixed:
1015492
Change-Id: I20eeadbfcdae16ce9c2feb8b882471683766ec4f
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
Ram Chandrasekar [Wed, 11 May 2016 16:55:30 +0000 (10:55 -0600)]
ARM: dts: msm: Disable LMH driver probe for msmcobalt rumi
Tsens controller wont be able to send any temperature data in RUMI.
This will block LMH driver in HLOS during profile switch.
Disable LMH driver probe for RUMI to avoid this profile switch and
lock up.
CRs-Fixed:
1015361
Change-Id: Id54c09e0cf2c3701c10c71d6688417d3f5d4c08e
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Joonwoo Park [Fri, 13 May 2016 21:08:40 +0000 (14:08 -0700)]
Revert "sched: set HMP scheduler's default initial task load to 100%"
This reverts commit
28f67e5a50d7c1bfc ("sched: set HMP scheduler's
default initial task load to 100%") since 100% of init task load
makes too much of power inefficiency on some targets.
CRs-fixed:
1006303
Change-Id: I81b4ba8fdc2e2fe1b40f18904964098fa558989b
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Aravind Venkateswaran [Wed, 11 May 2016 22:17:20 +0000 (15:17 -0700)]
clk: msm: mdss: fix pclk_src_mux clock ops for DSI PLL on msmcobalt
The DSI pixel clock path in the DSI PLL has a mux clock (pclk_src_mux)
which allows the pixel clock to be either sourced out of the VCO clock
or the bitclock. In the current code, the ops for this mux clock is
overloaded incorrectly which results in the pixel clock being always
sourced out of the bit clock. Fix this by using the default mux clock
ops for this clock.
Change-Id: I39c23b52d17994e28bd3b0d93e8e3dabdb687940
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Chris Lew [Fri, 6 May 2016 02:59:53 +0000 (19:59 -0700)]
soc: qcom: glink: Fix race condition in dummy xprt cleanup
In glink_core_channel_cleaup there is a race condition while
traversing the channels list. This change holds the xprt
channel spinlock during the list manipulation.
CRs-Fixed: 988266
Change-Id: Idcff59ca1483fd98173255d6258e6771d91dec19
Signed-off-by: Chris Lew <clew@codeaurora.org>
Joonwoo Park [Thu, 12 May 2016 21:18:18 +0000 (14:18 -0700)]
defconfig: msm: enable CONFIG_SCHED_DEBUG
Enable CONFIG_SCHED_DEBUG for debugging purpose.
CRs-fixed:
1006303
Change-Id: Iceee806479bc41d7aa32cb78b6ede59cb85fc259
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Runmin Wang [Thu, 12 May 2016 23:49:31 +0000 (16:49 -0700)]
Revert "defconfig: enable msm serial console on msmcortex perf config"
This reverts commit
7b1a1d226391 ("defconfig: enable msm serial console
on msmcortex perf config").
We do not need this change since USB issue is fixed. No longer need
console to connect or disconnect USB.
CRs-Fixed:
1015006
Change-Id: I49154af38f0c59f6add8a38ebbc06f7dcfc85373
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Adrian Salido-Moreno [Tue, 3 May 2016 20:23:31 +0000 (13:23 -0700)]
msm: mdss: fix wb format enumeration
Enumeration for writeback is not properly done because not all
information from device tree has been retrieved before setting up
supported formats. Moved this call until all data has been retrieved
from device tree and hw pre initialization.
Change-Id: Id228bf7ec564669fa8e9e739e27052de0133cc4d
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Shashank Mittal [Tue, 21 Apr 2015 19:01:58 +0000 (12:01 -0700)]
qcom: memory_dump: add support to dump DCC data.
Data Capture and Compare (DCC) is a DMA engine, to capture or to
perform CRC over configuration data or system memory.
Add ids for DCC registers and sram data.
Change-Id: If76ef1325b1be623626742b0f0172a1675f21d63
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Prasad Sodagudi [Tue, 12 May 2015 04:35:14 +0000 (10:05 +0530)]
soc: qcom: common_log: Fix a memory leak in common_log driver
Fix the memory leak in common_log_register_log_buf() function
when registering log_first_idx with the memory with dump v2 driver.
Also use kmemleak_not_leak when msm_dump_data_register() calls
are successful to ensure that kmemleak doesn't report it as a memory
leak.
CRs-Fixed: 832905
Change-Id: I36eaeebf821f64dd7503ec823aca3c7aec846bd0
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Sarangdhar Joshi [Fri, 22 May 2015 18:50:19 +0000 (11:50 -0700)]
qcom: common_log: add support to dump rpm code ram
Allocate memory to dump RPM CODE RAM at the time of crash.
Change-Id: I5062d65a095538a508944315e6cc06f430382bf5
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Shashank Mittal [Wed, 20 May 2015 21:37:36 +0000 (14:37 -0700)]
qcom: common_log: add support to dump VSENSE registers
Allocate memory to dump VSENSE registers at the time of crash.
Change-Id: Ibd896873bc40b723071c66ca7cf1a4bc9b38ad5e
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Neeti Desai [Fri, 19 Sep 2014 01:16:27 +0000 (18:16 -0700)]
qcom: common_log: add support to dump PMIC registers
Register for dumping 4KB of memory to dump PMIC
registers which can be parsed in case of device crash.
Change-Id: Idbf26d6241ab9a87e4dcea42723428289f2a869d
Signed-off-by: Neeti Desai <neetid@codeaurora.org>
[spjoshi@codeaurora.org: fix merge conflict]
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
[mittals@codeaurora.org: fix merge conflict]
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Wu Jin [Fri, 7 Mar 2014 07:51:12 +0000 (15:51 +0800)]
common_log: add common_log support snapshot
This snapshot is taken as of msm-3.10 commit:
78c36fa0ef (Merge "msm: mdss: Prevent backlight update during
continuous splash")
Common log registers the kernel log buffer address with the
memory dump driver so that the __log_buf can be collected from
ramdumps without the need of an external System.map file.
Change-Id: Ibeb74ca064e78fe7522e46b3c32bb362082d5d24
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
[spjoshi@codeaurora.org: fix merge conflict]
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
[mittals@codeaurora.org: fix merge conflict]
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Tony Truong [Wed, 16 Dec 2015 21:35:47 +0000 (13:35 -0800)]
ARM: dts: msm: create PCIe devicetree node for msmcobalt
Create and add PCIe resources such as register bases, clocks,
regulators, GPIOs, etc. to msmcobalt devicetree and pinctrl
devicetree.
Change-Id: I7a41ed6dd0f78cba140a15661d44b2f6c2745e39
Signed-off-by: Tony Truong <truong@codeaurora.org>
Tony Truong [Thu, 14 Apr 2016 01:15:41 +0000 (18:15 -0700)]
defconfig: msm: enable PCIe bus driver in msmcobalt defconfig
Enable MSM PCIe bus driver in defconfig for msmcobalt.
Change-Id: I44ece35ed1d8dda4d8139dfb54adc7a2e9c49383
Signed-off-by: Tony Truong <truong@codeaurora.org>
Tony Truong [Thu, 12 May 2016 00:51:00 +0000 (17:51 -0700)]
msm: pcie: update misc register offsets on msmcobalt
Some msmcobalt PCIe configuration registers have different
offsets than other chipsets. Update these offsets so
that PCIe can be correctly configured on msmcobalt.
Change-Id: I42c7f545a48e6a431ccdba062399776e8c1c64f2
Signed-off-by: Tony Truong <truong@codeaurora.org>
Tony Truong [Wed, 11 May 2016 00:31:11 +0000 (17:31 -0700)]
msm: pcie: add device and vendor ID for PCIe on msmcobalt
Add device and vendor ID for PCIe on msmcobalt based on PCIe
core's configurations. This value is required to enable
PCIe low power management features.
Change-Id: I972c35c79327e3baa38573318ed0909d4daa9516
Signed-off-by: Tony Truong <truong@codeaurora.org>
Tony Truong [Fri, 6 May 2016 02:06:08 +0000 (19:06 -0700)]
msm: pcie: retrieve PCIe SMMU SID base from DT
SMMU SIDs allocated for PCIe varies across chipsets.
Thus, add support to retrieve the base SID from
PCIe devicetree node so that PCIe bus driver can
use it to calculate and assign to each PCI device.
Change-Id: I7651f2cbc53587f5b48501855260c87af2a2db01
Signed-off-by: Tony Truong <truong@codeaurora.org>
Tony Truong [Mon, 9 May 2016 23:36:50 +0000 (16:36 -0700)]
msm: pcie: update PCIe PHY registers and sequences for msmcobalt
PCIe PHY on msmcobalt has different register offsets and does not
support the same PHY sequences as other platforms. Thus, update
the PHY register offsets and sequences for msmcobalt.
Change-Id: If87bd507228476fee9713f88c06a1cf04b13f163
Signed-off-by: Tony Truong <truong@codeaurora.org>
David Keitel [Mon, 9 May 2016 21:27:48 +0000 (14:27 -0700)]
trace: cpu_freq_switch: use tracefs instead of debugfs
Rather than using debugfs, switch to tracefs which trace
moved to in kernel 4.4.
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
Change-Id: I52ef7d45cabb20cc61fbd2fb3ef5016b041bc56c
Tony Truong [Tue, 12 Apr 2016 18:58:22 +0000 (11:58 -0700)]
msm: pcie: add support to get PCIe PHY init sequence from DT
PCIe PHY varies between each chipset. Thus, the PHY init sequence on
each of these chipsets are also different. Therefore, add the support
to read PCIe PHY init sequence from devicetree.
Change-Id: I21c2ce2b7d3bf1541a5d3580db4bc40497701095
Signed-off-by: Tony Truong <truong@codeaurora.org>
Alan Kwong [Fri, 13 May 2016 13:42:55 +0000 (09:42 -0400)]
msm: sde: Add error code for unsupported rotator version
Although rotator driver checks for hardware version, and rejects
unsupported version. But it does not return error code to indicate
error condition, and causes driver crash.
This fix adds error code to unsupported version, so upper layer can
properly handling the condition.
CRs-Fixed:
1015335
Change-Id: If83199b5990a3623b1018058d2164862352902b7
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
Osvaldo Banuelos [Fri, 8 Apr 2016 21:28:55 +0000 (14:28 -0700)]
ARM: dts: msm: Disable OSM vred FSM for msmcobalt
Disable the OSM vred FSM until core-count adjustments are enabled
for the CPRh VDD_APC0 and VDD_APC1 devices.
Change-Id: I467f49edbc65449f29f761c6b873ca702d24fa72
CRs-Fixed:
1014894
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Alan Kwong [Tue, 3 May 2016 20:18:48 +0000 (16:18 -0400)]
ARM: dts: msm: Add rotator clocks MNOC AHB/AXI for msmcobalt
Add additional required clocks to mdss device tree to enable
mmss smmu and ahb access for rotator.
CRs-Fixed:
1008505
Change-Id: I5bfc16e3d6ac3c6052b8dca55b42b57480ec650e
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
Lior David [Tue, 10 May 2016 07:47:37 +0000 (10:47 +0300)]
AndroidKernel.mk: additional fixes for multi-kernel tree
Fixes 2 problems related to multi-kernel tree support:
1. Copying of modules to /system/lib/modules is broken when building
in a multi-kernel tree. This is because INSTALL_MOD_PATH is not
set correctly. When building a multi-kernel tree, the output
directory is one additional directory deep, so modules end up
under <out>/obj/system/lib/modules instead of
<out>/system/lib/modules. Fix this by using BUILD_ROOT_LOC
which is set appropriately for multi-kernel and standard trees.
2. When running "make kernelconfig" on a multi-kernel tree,
the generated defconfig is copied to the wrong location,
since it uses the old-style location under kernel, instead
of kernel/<kernel name>.
Change-Id: I90563104a5b6219472eaeae1964fc34b52586536
CRs-Fixed:
1014872
Signed-off-by: Lior David <liord@codeaurora.org>
David Collins [Thu, 12 May 2016 00:00:28 +0000 (17:00 -0700)]
ARM: dts: msm: restrict VDD_GFX voltage to Nom for CPR Rev 0 on msmcobalt
Some MSMCOBALT parts with CPR revision 0 are unable to operate at
low voltage. Therefore, raise the CPR floor voltage to be equal
to the Nominal ceiling voltage for all corners. Also increase
the ceiling voltages for corners accordingly to ensure that the
ceiling >= floor voltage requirement is met.
Change-Id: I346a909984519c2522503f842d449c6f3217b746
CRs-Fixed:
1014407
Signed-off-by: David Collins <collinsd@codeaurora.org>
Hemant Kumar [Wed, 11 May 2016 20:38:49 +0000 (13:38 -0700)]
ARM: dts: msm: Enable super speed mode support on msmcobalt
Enable ssphy and update the qmp phy initialization sequence
to enumerate in super speed mode. By default Lane A is
selected for super speed mode.
Change-Id: Ibd5fdd0a1f48ecd8a828d187ac86513e3f48ae6f
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Abhijit Kulkarni [Wed, 4 May 2016 02:03:37 +0000 (19:03 -0700)]
ARM: dts: msm: Add mnoc_ahb clock for msmcobalt
Add mmss_mnoc_ahb clock to mdss device tree as this clock needs to be
turned on before turning on ahb_clk.
CRs-Fixed:
1008505
Change-Id: I43ccff9774d098d551c4ba25ad5678fee13aca1f
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Kuirong Wang [Mon, 9 May 2016 21:35:30 +0000 (14:35 -0700)]
ASoC: msm: Add USB audio via ADSP support
Add new USB rx and tx afe ports and routing to different
fe dais to enable USB audio via ADSP.
Change-Id: I4f82ba27becee1f3b62c410be0d00876961f9b18
Signed-off-by: Vidyakumar Athota <vathota@codeaurora.org>
Signed-off-by: Kuirong Wang <kuirongw@codeaurora.org>
Steve Muckle [Thu, 13 Nov 2014 23:51:49 +0000 (15:51 -0800)]
arm64: enable HAVE_IRQ_TIME_ACCOUNTING for arm64
The only dependency for irq time accounting is a sufficiently high
resolution timer. Plenty of arm64 platforms will have this, so enable
this feature.
CRs-Fixed:
1013947
Change-Id: Id675a541a6813a14ae0b7e1bb66670bf7467a97f
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
[satyap@codeaurora.org: trivial merge conflict resolution.]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Runmin Wang [Tue, 3 May 2016 23:59:13 +0000 (16:59 -0700)]
defconfig: Enable CPUSS dump driver
Enable CPUSS dump driver to dump cpu subsystem during crash.
CRs-Fixed:
1011333
Change-Id: Id4a8bca3eb77db4f998c790f1927fe373684048a
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Runmin Wang [Tue, 3 May 2016 23:31:23 +0000 (16:31 -0700)]
soc: qcom: Add snapshot of the cpuss driver
This snapshot is taken as of msm-3.18 commit
dacccc6.
CRs-Fixed:
1011333
Change-Id: I4ed06b5602220ed4e30bd37a0633ccb3454f7d43
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Sreelakshmi Gownipalli [Tue, 19 Apr 2016 20:16:15 +0000 (13:16 -0700)]
diag: Use correct index while accessing DCI channel
Use correct index value while accessing DCI channel status.
Change-Id: I97456326a40c6d24c208307a9e8e6a55fc5b9d59
Signed-off-by: Sreelakshmi Gownipalli <sgownipa@codeaurora.org>
Deepak Katragadda [Tue, 10 May 2016 23:29:54 +0000 (16:29 -0700)]
clk: msm: clock-gcc-cobalt: Add reset capability to PCIE pipe clock
Instead of having a separate reset clock for PCIE 0 reset, tag the
BCR register with the gcc_pcie_0_pipe_clk directly.
CRs-Fixed:
1014989
Change-Id: Icbc3a4a237bd0ac75fbef0857238e18cfb0ca533
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Deepak Katragadda [Mon, 9 May 2016 22:38:55 +0000 (15:38 -0700)]
clk: msm: clock-gcc-cobalt: Update the pcie_aux_clk_src frequency
The pcie_aux_clk_src needs to run at XO frequency instead
of at 1MHz. Update the clock driver to support that.
CRs-Fixed:
1013278
Change-Id: Id8a92b0f36f71ed50726504d1e5b3feab4cfa512
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Runmin Wang [Thu, 12 May 2016 22:01:01 +0000 (15:01 -0700)]
pinctrl: qcom: Fix the base address of various GPIOs
Update the base address of GPIOs to the correct value.
CRs-Fixed:
1014950
Change-Id: Id232492bd458dac04e89a94ed5a85092223ebff6
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Jeykumar Sankaran [Mon, 29 Feb 2016 20:09:15 +0000 (12:09 -0800)]
ARM: dts: msm: separate control and config offsets for PPB
This change separates the control and config register offset nodes
for ping pong blocks. Its not necessary every ping pong
blocks to have both control and config registers.
Change-Id: Ide998ad71abccb35d899f9e1f6093949acb95b09
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Ram Chandrasekar [Thu, 5 May 2016 21:14:03 +0000 (15:14 -0600)]
msm: thermal: Update the min frequency update logic
With LMH DCVSh hardware, the current check will use cpufreq to
limit both scaling min and max frequency. But cpufreq should be
used only for scaling min frequency.
Update the check to use cpufreq only to limit scaling min frequency.
Change-Id: I38de1699a7cdd5bc3fecef80dd34c4d22d2fd200
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Ram Chandrasekar [Thu, 5 May 2016 19:17:15 +0000 (13:17 -0600)]
msm: thermal: Avoid updating the scaling max frequency to cpufreq
With LMH DCVSh hardware, thermal driver can directly vote in the
hardware to limit the scaling max frequency. Voting to the cpufreq
driver along side the hardware, will introduce software delay when
removing the mitigation.
So avoid voting the scaling max frequency to the cpufreq when LMH DCVSh
is available.
Change-Id: I8a5f913ae41263b06af99b0ee802b4fa68312f33
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Ram Chandrasekar [Thu, 12 May 2016 15:28:38 +0000 (09:28 -0600)]
defconfig: msmcortex: Enable bcl driver
Enable bcl peripheral driver. The driver will interact
with the bcl peripheral to get the battery current, battery
voltage and set and receive thresholds for the same.
CRs-Fixed:
1010115
Change-Id: I7168c754e939ef9da001bcac52a5b802dea40b41
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Kuirong Wang [Sat, 7 May 2016 21:36:48 +0000 (14:36 -0700)]
ARM: dts: msm: Add slimbus_6_rx back-end dai-link for msmcobalt
Add slimbus_6_rx back-end dai-link for msmcobalt to enable
independent backend for different devices during audio playback.
Change-Id: If22cadbcfac92f8243a3b6d3201935a839cd701a
Signed-off-by: Kuirong Wang <kuirongw@codeaurora.org>
Kuirong Wang [Wed, 4 May 2016 21:40:05 +0000 (14:40 -0700)]
ARM: dts: msm: Add USB audio via ADSP support for msmcobalt
Add device tree entries for USB audio rx and tx to
support USB audio via ADSP on msmcobalt platform.
Change-Id: I345aa2369d18e2137ce79676049bb59d715d1ee0
Signed-off-by: Kuirong Wang <kuirongw@codeaurora.org>
Sridhar Ancha [Thu, 28 Apr 2016 16:32:23 +0000 (22:02 +0530)]
msm: ipa: Add NETIF_F_SG to RMNET_IPA's hw features
GSO segmented packets are getting linearized
before being sent to rmnet_ipa interface since SG
feature is not enabled.
Add NETIF_F_SG to IPA's HW features so that
ethtool can be used to enable it.
Change-Id: I7b321c796935febb3fa3e9ae520fd65e00da507c
Acked-by: Chaitanya Pratapa <cpratapa@qti.qualcomm.com>
Signed-off-by: Sridhar Ancha <sancha@codeaurora.org>
Viswanadha Raju Thotakura [Wed, 11 May 2016 22:32:16 +0000 (15:32 -0700)]
msm: camera: Increase wait timeout time for kernel probe
Camera sensor probe happens in camera daemon, because
of delayed start of camera daemon, timeout happens and
camera server is notified with 0 cameras, this is
temporary solution.
CRs-Fixed:
1014373
Change-Id: I957b9744f6f627a74f805933012429c41b910e92
Signed-off-by: Viswanadha Raju Thotakura <viswanad@codeaurora.org>
Aravind Venkateswaran [Wed, 11 May 2016 21:07:08 +0000 (14:07 -0700)]
ARM: dts: msm: fix panel mode selection GPIO specification
Commit
a240321fd68894659859861b96a618af8370efbb ("ARM: dts: msm: define
primary display interface for msmcobalt CDP") used an incorrect binding
to specify the panel mode selection gpio state for the nt35597 WQXGA
dual dsi panel. Fix this to ensure that the panel mode gpio state is set
correctly.
Change-Id: I895642c231d980633801d094c8f329d209370c88
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Ram Chandrasekar [Mon, 25 Apr 2016 22:38:47 +0000 (16:38 -0600)]
ARM: dts: msm: Add default configs for bcl in msmcobalt
Add default battery mitigation configurations for msmcobalt
CRs-Fixed:
1010115
Change-Id: I13f1825f2eb04d606464d1092c222c8269084107
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Ram Chandrasekar [Thu, 7 Apr 2016 17:18:31 +0000 (11:18 -0600)]
ARM: dts: msm: Configure bcl peripheral driver for PMIcobalt
Configure the bcl peripheral driver with the details about the
register address, interrupt and interrupt clear polling delay for
PMIcobalt.
CRs-Fixed:
1010115
Change-Id: I521ee6c715525bd401630ec7948e5746682de6da
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Viswanadha Raju Thotakura [Fri, 6 May 2016 21:01:27 +0000 (14:01 -0700)]
ARM: dts: msm: Correct camera nodes for msmcobalt
Correct the pinctrl nodes for actuator, change the CCI
source for auxiliary camera node, add eeprom1 node for
auxiliary sensor.
CRs-Fixed:
1014373
Change-Id: Icd9f1478c797fbdbd76d96c3069e5baa2c30ff61
Signed-off-by: Viswanadha Raju Thotakura <viswanad@codeaurora.org>
Ram Chandrasekar [Fri, 11 Mar 2016 21:29:09 +0000 (14:29 -0700)]
power: bcl_peripheral: Support new bcl peripheral
Add support for the new version of bcl peripheral introduced
in PMIcobalt.
The new support includes,
1. support the new address space
2. set the new Ibat too high threshold
3. set the new vbat low comparator threshold
4. set the new vbat too low comparator threshold
5. enable the LMH DCVSh monitor algorithm, when the
thresholds are configured.
CRs-Fixed:
1010115
Change-Id: I6dad908bbc673ff1b7f7d3d05fecdfc8f48b5815
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Ram Chandrasekar [Sat, 7 May 2016 00:29:46 +0000 (18:29 -0600)]
power: bcl: snapshot of battery_current_limit driver
This snapshot is taken as of msm-3.18 commit
978d23c.
Accommodate the changes in the input arguments for
power_supply_register() API and use
power_supply_get_property() API to get the SoC information
from BMS.
CRs-Fixed:
1010115
Change-Id: I1af565ffd3b61e424aca1cbd5ec6cbef8d89f1fa
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
David Dai [Thu, 5 May 2016 23:45:09 +0000 (16:45 -0700)]
ARM: dts: msm: Add mnoc ahb bus fab for msmcobalt
Add mnoc ahb fab used by clients to request for different
speeds on configuration paths.
CRs-Fixed:
1013346
Change-Id: Ic5f3598644a6d93796b8613117e42ff692168c3c
Signed-off-by: David Dai <daidavid1@codeaurora.org>
David Dai [Thu, 5 May 2016 19:24:14 +0000 (12:24 -0700)]
ARM: dts: msm: use msmbus_bimc node for bimc_fab for msm_cobalt
To prevent a 0 vote on to bimc_clk from late clock init,
there must be a non zero vote on bimc_clk's child as opposed
to itself, vote on the child clock node as opposed to the parent.
CRs-Fixed:
1013348
Change-Id: Id3a9fa3238ce0f04737a7b98aa897ec83ecdc8e2
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Runmin Wang [Tue, 10 May 2016 17:53:18 +0000 (10:53 -0700)]
defconfig: enable CONFIG_DEVMEM and CONFIG_DEVKMEM
Add support to access system's memory.
CRs-Fixed:
1013668
Change-Id: I7cafb74373efbc611bc894bdf3b351aae7e03da5
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Banajit Goswami [Wed, 15 Jul 2015 22:36:49 +0000 (15:36 -0700)]
ASoC: soc-core: change debug level for debugfs fail message
Debugfs directory creation failure are not critical error.
However, the failure messages might be misleading and might
be interpreted as geniune failure in ASoC functionality.
Mark the failure messages as debug level.
Change-Id: Id61c81753d493b6508cbe87c59077adda4675ada
Signed-off-by: Banajit Goswami <bgoswami@codeaurora.org>
Osvaldo Banuelos [Wed, 27 Apr 2016 17:24:56 +0000 (10:24 -0700)]
clk: msm: osm: initialize PLL test control register
Program the PLL test control register for the power
cluster clock in agreement with hardware guidelines.
Change-Id: I102fd544ea0571d31d2ef9232195d4adbddda6d7
CRs-Fixed:
1009203
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Aravind Venkateswaran [Wed, 11 May 2016 21:38:13 +0000 (14:38 -0700)]
msm: mdss: dsi: fix configuration for mode selection GPIO
Configure the mode selection GPIO as direction output in order to
correctly configure the panel operating mode.
Change-Id: Ic79850674c42f3c59512467dbb608942b98cf74a
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Abhijit Kulkarni [Thu, 5 May 2016 18:45:43 +0000 (11:45 -0700)]
msm: mdss: fix qseed3 op_mode register programming
Initialize the op_mode register and program the direction_enable
field in this register correctly
CRs-Fixed:
1008505
Change-Id: I2dbcb8eb1ef5c6e0ebcbfb9f298a14344fbe7ce3
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Siddartha Mohanadoss [Wed, 11 May 2016 19:21:21 +0000 (12:21 -0700)]
defconfig: arm64: msmcortex: Enable VADC_HC and BTM driver
Enable VADC_HC and BTM peripheral driver on PMcobalt
to support reading and setting thresholds on ADC
channel such as voltage phone power(vph_pwr) and
thermistors.
Change-Id: I783d87714145f58fefc9e1e6a09d1ecfab56744b
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
Abhijeet Dharmapurikar [Thu, 21 Jan 2016 18:58:22 +0000 (10:58 -0800)]
regmap: improve debugfs interface to dump specific addresses
The current method of cat-ing register file dumps the entire
address space. One can use dd command to dump a subrange within
the address space. However one needs to know the string length
of each line which is derived from max address, the character
length of each register entry and the format.
Provide simple means to dump a range by allowing user to specify
the start address and the count of registers. When the data is read
convert the dump address to a starting position in the file. Similarly
if the file offset goes beyond the dump range return 0 to indicate
that the data is already dumped.
Also provide means to write to a register address.
CRs-Fixed:
1001770
Change-Id: I3466ce89007d127151f6760328edad116d679db8
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Sagar Dharia [Tue, 12 Apr 2016 20:14:33 +0000 (14:14 -0600)]
slim: ngd: retention support in power-collapse
Support retention by checking interrupt status rather than logical
address register. During retention, interrupt status is zero'ed but
logical address may be retained to avoid report-present generation.
Change-Id: I9e7f24c5f4eb722643bf3fac2d5c898ad107dd24
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Arun Menon [Wed, 5 Feb 2014 21:44:21 +0000 (13:44 -0800)]
[media] v4l: Update v4l2 32bit structures
Update v4l2_event32 structure with updated elements
from v4l2_event structure. Also copy and update
reserved and other fields during 32 bit ioctl handling.
CRs-Fixed:
1013345
Change-Id: I3038a2c0c7f2b7f13c412dc04890744d8dbe37ee
Signed-off-by: Arun Menon <avmenon@codeaurora.org>
Shashank Mittal [Thu, 21 Apr 2016 16:41:27 +0000 (09:41 -0700)]
defconfig: arm64: enable Coresight drivers for msmcobalt
Enable Coresight drivers for msmcoblt. These devices can be used to
configure and enable trace functionality on msmcobalt.
Change-Id: Ib4b50d7df15114d417898c36b229441766bd5b42
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Sunil Khatri [Fri, 29 Apr 2016 15:29:46 +0000 (09:29 -0600)]
msm: kgsl: Add property to determine GPU bitness
Add the property to determine GPU bitness which
is used by the clients via KGSL ioctl.
Certain clients of KGSL such as Open-CL driver
need to know explicitly about the GPU mode.
Change-Id: I77523d7816edb9776014aaf3aa85321af0d20aaf
Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
Jordan Crouse [Fri, 29 Apr 2016 15:29:27 +0000 (09:29 -0600)]
msm: kgsl: Use the crash dumper to read HLSQ/shader memory on 5XX
The host AHB aperture for reading the HSLQ/SP/TP and shader memory
blocks might be blocked on A5XX targets so use the CP crash dump
utility to read them instead. Downside if the crashdumper goes boom
we'll have to skip those registers in the fallback.
Change-Id: Ic0dedbad3c7b485c696198bdfcb78d45e929ec22
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Hareesh Gundu [Fri, 29 Apr 2016 15:29:15 +0000 (09:29 -0600)]
msm: kgsl: Add effuses read capabilities for A505 GPU
A505 GPU is having two different frequency plans, for
loading a specific frequency plan add speed bin read
information capability to A505.
Change-Id: I259020d7e4613d043e213ab2cb41e80ceb11f46a
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Sunil Khatri [Fri, 29 Apr 2016 15:28:51 +0000 (09:28 -0600)]
msm: kgsl: Do not allocate memory for profiling and sync commands
Do not allocate memory for IB descriptors for commands
of types profiling buffers, sync and markers.
This fixes the memory leak due to allocation of
memory for such commands and these were never freed.
CRs-Fixed: 996651
Change-Id: Ib168d60ad89e0fd55cd1f10b773b7cdaa7400ace
Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
Shrenuj Bansal [Fri, 29 Apr 2016 15:28:02 +0000 (09:28 -0600)]
msm: kgsl: Add 1M and 8K pools to the allocator
This change includes the below:
- Add 1M and 8k pools and structure the allocator to use all pools
from the largest page to the smallest
- Reserve a set number of pages for each of these pools at init time
- When allocating, use the reserved pools and then fall back to
allocating from system memory using only 8k and 4k pages
- Remove maximums on the pool sizes
- Zero the memory when we create the pool initially and add pages
back to the pool on free
CRs-Fixed: 995735
Change-Id: I9440bad62d3e13b434902f167c9d23467b1c4235
Signed-off-by: Shrenuj Bansal <shrenujb@codeaurora.org>
Sridhar Ancha [Fri, 29 Apr 2016 13:31:03 +0000 (19:01 +0530)]
msm: ipa: Fix to polling mode
When IPA clock is enabled, suspend bit is cleared
and if pipe is non-empty EOT is posted internally.
At the same time, there is a possibility that SPS
driver posts EOT. This can result into incorrect
state of polling state and switch to intr mode is
tried repeatedly. Make a change to check if we are
in intr mode already in addition to the polling state.
Change-Id: I1af08605f7d2d234b0e5a4e3c8928db6cff5c7b4
Acked-by: Chaitanya Pratapa <cpratapa@qti.qualcomm.com>
Signed-off-by: Sridhar Ancha <sancha@codeaurora.org>
Chun Zhang [Tue, 1 Mar 2016 10:34:54 +0000 (02:34 -0800)]
leds: leds-qpnp-flash-v2: create v2 QPNP flash LED driver
There is a new Qualcomm Technology Inc. Plug-n-play(QPNP) PMIC chip,
which introduces brand new flash LED hardware. The new hardware
comes with up to 3 LEDs support, different register mapping layout,
and different torch enablement requirement. Therefore, a new driver
is introduced to cover this need.
Change-Id: Ic878f1a946955edff3a9228e7fe54b7a525e37b1
Signed-off-by: Chun Zhang <chunz@codeaurora.org>
Signed-off-by: Mohan Pallaka <mpallaka@codeaurora.org>
Chinmay Sawarkar [Wed, 20 Apr 2016 03:49:58 +0000 (20:49 -0700)]
ARM: dts: msm: Clock fixes and Secure context banks for msmcobalt
Update the Venus clock frequency for different Venus load. There
were kernel panic as the BIMC clocks were OFF. Add the bimc_smmu
gdsc to turn ON the BIMC clocks. Add secure context banks.
Change-Id: I120ce95ea20434b41ac88a5d686b994630516435
Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
Skylar Chang [Thu, 5 May 2016 06:16:41 +0000 (23:16 -0700)]
defconfig: msm: enable rndis_ipa on cobalt
enable rndis_ipa on cobalt build to support
IPA-offload data path.
Change-Id: I98c462b56dbe01930456a16d5eeb6646b0a2db83
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
Mohan Pallaka [Fri, 6 May 2016 00:05:04 +0000 (17:05 -0700)]
ARM: dts: msm: update touch screen resolution
Change the touch screen to match WQHD display
Change-Id: Ia0b77f23b26941ea2a53451ae61c46aa0ada731c
Signed-off-by: Mohan Pallaka <mpallaka@codeaurora.org>
Phani Kumar Uppalapati [Wed, 4 May 2016 17:33:42 +0000 (10:33 -0700)]
slimbus: Add API to get matching ID table
Add API in slimbus driver for clients to get the
matching ID table which helps in accessing driver
data and name fields.
CRs-fixed: 975738
Change-Id: I09c9f1de74e348b032d215cbb0fb9ba6c7aecf18
Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
Hemant Kumar [Thu, 5 May 2016 04:23:59 +0000 (21:23 -0700)]
usb: gadget: f_gsi: Call ipa_usb_init_teth_prot() from gsi_bind
Currently ipa_usb_init_teth_prot() is called before gsi_bind()
gets called as a result of usb_add_function() call. gsi_bind()
is polulating ipa_init_params which is passed to
ipa_usb_init_teth_prot(). Since usb_add_function() is getting
called later after gsi_bind_config() returns, ipa_init_params
remains unpopulated and results into ipa_usb_init_teth_prot()
returning failure. Fix this issue by moving the call to
gsi_bind(). This also matches to ipa_usb_deinit_teth_prot()
call in gsi_unbind().
CRs-Fixed:
1013830
Change-Id: I824d3fa62e2736962680ae1c883b9a2916346331
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Hemant Kumar [Tue, 10 May 2016 22:23:00 +0000 (15:23 -0700)]
usb: dwc3: Fix dep name handling upon ep disable
dep name needs to be updated only for non-gsi endpoints
since gsi endpoints are statically assigned. Due to merge
from previous kernel dep name is updated twice upon ep
disable. This is causing gsi ep names to get modified
resulting into failure in finding the original gsi ep name
upon function bind. Hence update the dep name only once
at the end of ep disable and skip it for gsi eps.
CRs-Fixed:
1013830
Change-Id: Iea9282cc8fb4f13d066d25c63ccb1da1881c0a8a
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Hemant Kumar [Tue, 10 May 2016 22:16:51 +0000 (15:16 -0700)]
usb: gadget: f_gsi: Use gsi ep ops to disable endpoint
gsi driver does not call the gadget API usb_ep_enable()
instead uses gsi ep operation call back to enable gsi ep.
As a result ep->enabled flag remains clear. Later function
driver calls usb_ep_disble() API from gadget framework and
ep disable operation gets skipped. This causes start transfer
command to fail next time when gsi ep gets enabled. Fix this
issue by calling gsi ep disable operation instead of calling
gadget API.
CRs-Fixed:
1013830
Change-Id: I06570dec368b430321ec196a5e4338f657c43b42
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Hemant Kumar [Tue, 10 May 2016 22:01:44 +0000 (15:01 -0700)]
usb: dwc3: Add support for gsi endpoint disable operation
gsi driver does not call the gadget API usb_ep_enable()
instead uses gsi ep operation call back to enable gsi ep.
As a result ep->enabled flag remains clear. Later function
driver calls usb_ep_disble() API from gadget framework and
ep disable operation gets skipped. Fix this by adding gsi ep
operation for ep disable. This makes the enable and
disable ep operations both handled by gsi ep ops.
CRs-Fixed:
1013830
Change-Id: I5caa9a839b9fdd144af0a59a7c605777f7a3a659
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>