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Eric Anholt [Thu, 19 Feb 2015 20:19:44 +0000 (12:19 -0800)]
vc4: Move qir_uniform() and the constant-value versions to vc4_qir.c/h.
I may want them in optimization passes, and they're not really particular
to the program translation stage.
Eric Anholt [Thu, 19 Feb 2015 20:58:53 +0000 (12:58 -0800)]
vc4: Enforce one-uniform-per-instruction after optimization.
This lets us more intelligently decide which uniform values should be put
into temporaries, by choosing the most reused values to push to temps
first.
total uniforms in shared programs: 13457 -> 13433 (-0.18%)
uniforms in affected programs: 1524 -> 1500 (-1.57%)
total instructions in shared programs: 40198 -> 40019 (-0.45%)
instructions in affected programs: 6027 -> 5848 (-2.97%)
I noticed this opportunity because with the NIR work, some programs were
happening to make different uniform copy propagation choices that
significantly increased instruction counts.
Eric Anholt [Thu, 19 Feb 2015 20:16:25 +0000 (12:16 -0800)]
vc4: Rename add_uniform() to qir_uniform().
Eric Anholt [Fri, 20 Feb 2015 07:34:37 +0000 (23:34 -0800)]
vc4: Shut up runtime warnings about new pipe caps.
Matt Turner [Thu, 12 Feb 2015 01:42:43 +0000 (01:42 +0000)]
i965/vec4: Add and use byte-MOV instruction for unpack 4x8.
Previously we were using a B/UB source in an Align16 instruction, which
is illegal. It for some reason works on all platforms, except Broadwell.
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86811
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Tue, 10 Feb 2015 06:54:51 +0000 (22:54 -0800)]
i965/blorp: Emit MADs.
Low hanging fruit: cuts a couple of instructions.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Tue, 10 Feb 2015 05:26:14 +0000 (21:26 -0800)]
i965/blorp: Optimize clamping tex coords.
Each emit_cond_mov() emits a CMP of its first to arguments using the
specified conditional mod, followed by a predicated MOV of the fifth
argument into the fourth. In all four cases here, it was just
implementing MIN/MAX which we can do in a single SEL instruction.
Also reorder the instructions for a slightly better schedule.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Tue, 10 Feb 2015 05:11:46 +0000 (21:11 -0800)]
i965: Use greater-equal cmod to implement maximum.
The docs specifically call out SEL with .l and .ge as the
implementations of MIN and MAX respectively. Among other things, SEL
with these conditional mods are commutative.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Tue, 10 Feb 2015 06:21:21 +0000 (22:21 -0800)]
i965: Don't emit saturates for instructions without destinations.
We were special casing OPCODE_END but no other instructions that have no
destination, like OPCODE_KIL, leading us to emitting MOVs with null
destinations.
total instructions in shared programs:
5705243 ->
5701539 (-0.06%)
instructions in affected programs: 124104 -> 120400 (-2.98%)
helped: 904
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Wed, 11 Feb 2015 00:25:47 +0000 (16:25 -0800)]
i965/fs: Consider MOV.SAT to interfere if it has a source modifier.
The saturate propagation pass recognizes that the second instruction
below does not interfere with an attempt to propagate the saturate
modifier from instruction 3 to 1.
1: add(8) dst0 src0 src1
2: mov.sat(8) dst1 dst0
3: mov.sat(8) dst2 dst0
Unfortunately, we did not consider the case of instruction 2 having a
source modifier on dst0. Take for instance:
1: add(8) dst0 src0 src1
2: mov.sat(8) dst1 -dst0
3: mov.sat(8) dst2 dst0
Consider such an instruction to interfere. Increase instruction counts
in Anomaly 2, which could be a bug fix depending on the values the first
instruction produces.
instructions in affected programs: 53228 -> 53934 (1.33%)
HURT: 360
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Wed, 28 Jan 2015 06:43:28 +0000 (22:43 -0800)]
i965/fs: Use fs_inst::overwrites_reg() in saturate propagation.
This is safer and matches the conditional_mod propagation pass.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Tue, 10 Feb 2015 21:38:07 +0000 (13:38 -0800)]
i965/fs: Add unit tests for saturate propagation pass.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Thu, 19 Feb 2015 10:32:21 +0000 (21:32 +1100)]
glsl: Use the without_array predicate
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ilia Mirkin [Wed, 18 Feb 2015 08:35:23 +0000 (03:35 -0500)]
nv50: add PIPELINE_STATISTICS query support, based on nvc0
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Nick Tenney <nick.tenney@gmail.com>
Ilia Mirkin [Fri, 20 Feb 2015 01:15:28 +0000 (20:15 -0500)]
svga: add missing :
Fixes:
924ee3f408 ("gallium: add shader cap for dldexp/dfracexp support")
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Jason Ekstrand [Tue, 10 Feb 2015 04:18:44 +0000 (20:18 -0800)]
nir/GCM: Pull unpinned instructions out of blocks while pinning
This lets us be slightly more efficient by not walking the CFG extra times.
Also, it may make it easier to ensure that GVN happens on only unpinned
instructions.
Reviewed-by: Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Mon, 9 Feb 2015 22:58:12 +0000 (14:58 -0800)]
nir/GCM: Use pass_flags instead of bitsets for tracking visited/pinned
Reviewed-by: Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Tue, 3 Feb 2015 18:11:23 +0000 (10:11 -0800)]
nir: Add a global code motion (GCM) pass
v2 Jason Ekstrand <jason.ekstrand@intel.com>:
- Use nir_dominance_lca for computing least common anscestors
- Use the block index for comparing dominance tree depths
- Pin things that do partial derivatives
Reviewed-by: Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Mon, 9 Feb 2015 22:41:10 +0000 (14:41 -0800)]
nir/instr: Change "live" to a more generic "pass_flags" field
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Thu, 5 Feb 2015 05:22:45 +0000 (21:22 -0800)]
nir: Make nir_[cf_node/instr]_[prev/next] return null if at the end
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Thu, 5 Feb 2015 05:38:28 +0000 (21:38 -0800)]
nir/from_ssa: Don't try to read an invalid instruction
Right now, the nir_instr_prev function function blindly looks up the
previous element in the exec list and casts it to an instruction even if
it's the tail sentinel. The next commit will change this to return null if
it's the first instruction. Making this change first avoids getting a
segfault between commits. The only reason we never noticed is that, thanks
to the way things are laid out in nir_block, the casted instruction's type
was never parallal_copy.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Wed, 4 Feb 2015 22:01:51 +0000 (14:01 -0800)]
nir/validate: Validate SSA defs the same way we do for registers
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Wed, 4 Feb 2015 21:58:12 +0000 (13:58 -0800)]
nir/validate: Validate if_uses on registers
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Wed, 4 Feb 2015 05:39:56 +0000 (21:39 -0800)]
nir: Properly clean up CF nodes when we remove them
Previously, if you remved a CF node that still had instructions in it, none
of the use/def information from those instructions would get cleaned up.
Also, we weren't removing if statements from the if_uses of the
corresponding register or SSA def. This commit fixes both of these
problems
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Wed, 4 Feb 2015 05:04:57 +0000 (21:04 -0800)]
nir: use nir_foreach_ssa_def for indexing ssa defs
This is both simpler and more correct. The old code didn't properly index
load_const instructions.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Fri, 6 Feb 2015 20:49:08 +0000 (12:49 -0800)]
nir/from_ssa: Use the nir_block_dominance function instead of our own
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Fri, 6 Feb 2015 20:45:43 +0000 (12:45 -0800)]
nir/dominance: Add a constant-time mechanism for comparing blocks
This is mostly thanks to Connor. The idea is to do a depth-first search
that computes pre and post indices for all the blocks. We can then figure
out if one block dominates another in constant time by two simple
comparison operations.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Fri, 6 Feb 2015 20:06:04 +0000 (12:06 -0800)]
nir/dominance: Expose the dominance intersection function
Being able to find the least common anscestor in the dominance tree is a
useful thing that we may want to do in other passes. In particular, we
need it for GCM.
v2: Handle NULL inputs by returning the other block
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Ilia Mirkin [Fri, 18 Jul 2014 04:38:59 +0000 (00:38 -0400)]
st/mesa: lower DFRACEXP/DLDEXP when they are not supported
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Fri, 25 Jul 2014 21:19:57 +0000 (17:19 -0400)]
st/mesa: disable lowering of dops to dfrac when dround is available
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Fri, 25 Jul 2014 21:12:42 +0000 (17:12 -0400)]
st/mesa: add support for new double opcodes
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Fri, 25 Jul 2014 21:48:01 +0000 (17:48 -0400)]
gallium: add shader cap for dldexp/dfracexp support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Fri, 25 Jul 2014 21:03:33 +0000 (17:03 -0400)]
gallium: add a cap to enable double rounding opcodes
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Fri, 25 Jul 2014 20:46:42 +0000 (16:46 -0400)]
gallium: add some more double opcodes to avoid unnecessary lowering
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 19 Feb 2015 23:14:44 +0000 (09:14 +1000)]
docs/GL3.txt: softpipe now supports GL_ARB_gpu_shader_fp64
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 17 Feb 2015 00:48:04 +0000 (10:48 +1000)]
st/mesa: add st fp64 support (v7.1)
This adds support to the state tracker for
ARB_gpu_shader_fp64.
The details are explained in comments
within the code.
v2 : add double to int/unsigned conversion
v3: handle fp64 consts better
v4: use DRSQ
v4.1: add d2b
v4.2: drop DDIV
v5: split out some prep patches.
v5.1: add some comments.
v5.2: more comments
v6: simplify down the double instruction
generation loop.
v7: Merge Ilia's two cleanup patches.
v7.1: minor fixups for Ilia patch + cleanups
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 16 Feb 2015 23:44:50 +0000 (09:44 +1000)]
mesa/st_tgsi_to_glsl: prepare add_constant for fp64
This just moves stuff around a little to make the next patch
cleaner.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 16 Feb 2015 23:39:05 +0000 (09:39 +1000)]
st/glsl_to_tgsi: convert dst to an array
This is just prep work for fp64 support where we need
an array of 2 dst values.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 14 Aug 2014 08:49:20 +0000 (18:49 +1000)]
i965: just avoid warnings with fp64
This just fills in some blanks to avoid warnings in the i965 driver.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Thu, 19 Feb 2015 21:36:07 +0000 (13:36 -0800)]
glsl: Add compute to _mesa_shader_stage_to_string(); use unreachable.
This is basically Ian's review feedback for my patch that added
_mesa_shader_stage_to_abbrev() - it just makes both consistent again.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Thu, 19 Feb 2015 01:52:28 +0000 (17:52 -0800)]
i965/vec4: Print "VS" or "GS" when compiles fail, not "vec4".
This is now trivial to do right.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Kenneth Graunke [Thu, 19 Feb 2015 01:50:42 +0000 (17:50 -0800)]
i965/vec4: Replace debug_flag with debug_enabled.
backend_visitor now handles this, so we can delete the vec4_visitor
specific code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Kenneth Graunke [Thu, 19 Feb 2015 01:45:51 +0000 (17:45 -0800)]
i965: Make scheduler cycle estimates use the proper stage name.
Previously, the vec4 backend labeled shaders as "vec4" - now it uses the
specific names "VS" and "GS".
The FS backend now correctly prints "VS" for vertex shaders (rather than
"fs"). It also prints "FS" instead of "fs" for fragment shaders;
preserving that behavior didn't seem essential.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Kenneth Graunke [Thu, 19 Feb 2015 01:43:07 +0000 (17:43 -0800)]
i965/fs: Un-hardcode DEBUG_WM, "FS", and "fragment".
These code paths can (or will) be used for other shader stages.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Kenneth Graunke [Thu, 19 Feb 2015 01:38:45 +0000 (17:38 -0800)]
i965: Create backend_visitor fields for debugging messages.
We introduce three new fields in backend_visitor:
- debug_enabled: whether or not INTEL_DEBUG & DEBUG_<stage flag>
- stage_name: "vertex", "fragment", etc. for use in messages
- stage_abbrev: "VS", "FS", etc. for use in messages
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Kenneth Graunke [Thu, 19 Feb 2015 01:31:29 +0000 (17:31 -0800)]
i965: Add a function to translate MESA_SHADER_* into DEBUG_* enums.
When compiling, we have a gl_shader_stage (MESA_SHADER_*) enum, and want
to know whether debugging is enabled for that stage. This allows us to
easily translate it into the corresponding debug flag.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Kenneth Graunke [Thu, 19 Feb 2015 01:35:41 +0000 (17:35 -0800)]
glsl: Create a _mesa_shader_stage_to_abbrev() function.
This is similar to _mesa_shader_stage_to_string(), but returns "VS"
instead of "vertex".
v2: Use unreachable() and add MESA_SHADER_COMPUTE (requested by Ian).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Kenneth Graunke [Sat, 31 Jan 2015 12:31:16 +0000 (04:31 -0800)]
i965/fs: Use VARYING_SLOT checks rather than strcmp().
Comparing the location field is equivalent and more efficient.
We'll also need this when we start using NIR for ARB programs, as our
NIR converter will set the location field correctly, but probably won't
use the GLSL names for these concepts.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Kenneth Graunke [Wed, 4 Feb 2015 09:40:09 +0000 (01:40 -0800)]
i965/fs: Remove type parameter from emit_vs_system_value().
Every VS system value has type D. We can always add this back if that
changes, but for now, it's extra typing.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Dave Airlie [Mon, 9 Feb 2015 06:53:10 +0000 (16:53 +1000)]
glsl: add lowering for double divide to rcp/mul
It looks like no hw does div anyways, so we should just
lower at the GLSL level.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 14 Aug 2014 08:40:41 +0000 (18:40 +1000)]
softpipe/tgsi: expose doubles for softpipe.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 26 Aug 2014 23:56:14 +0000 (09:56 +1000)]
tgsi: add support for flt64 constants
These act like flt32 except they take up two slots, and you
can only add 2 x flt64 constants in one slot.
The main reason they are different is we don't want to match half a flt64
constants against a flt32 constant in the matching code, we need to make
sure we treat both parts of the flt64 as an single structure.
Cleaned up printing/parsing by Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 14 Aug 2014 08:38:51 +0000 (18:38 +1000)]
gallium: add double opcodes and TGSI execution (v4.2)
This patch adds support for a set of double opcodes
to TGSI. It is an update of work done originally
by Michal Krol on the gallium-double-opcodes branch.
The opcodes have a hint where they came from in the
header file.
v2: add unsigned/int <-> double
v2.1: update docs.
v3: add DRSQ (Glenn), fix review comments (Glenn).
v4: drop DDIV
v4.1: cleanups, fix some docs bugs, (Ilia)
rework store_dest and fetch_source fns. (Ilia)
4.2: fixup float comparisons (Ilia)
This is based on code by Michael Krol <michal@vmware.com>
Roland and Glenn also reviewed earlier versions.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Brian Paul [Thu, 19 Feb 2015 16:29:18 +0000 (09:29 -0700)]
gallium/util: indentation fix
Brian Paul [Thu, 19 Feb 2015 16:26:51 +0000 (09:26 -0700)]
st/mesa: add GSL_TYPE_DOUBLE, new ir_unop_* switch cases
To silence compiler warnings about unhandled switch cases.
v2: move GSL_TYPE_DOUBLE case to the "Invalid type in type_size" section,
per Ilia.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Brian Paul [Thu, 19 Feb 2015 16:25:42 +0000 (09:25 -0700)]
nir: add missing GLSL_TYPE_DOUBLE case in type_size()
To silence compiler warning about unhandled switch case.
v2: move GLSL_TYPE_DOUBLE to the "not reached" section, per Ilia.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Brian Paul [Wed, 18 Feb 2015 18:16:55 +0000 (11:16 -0700)]
st/mesa: fix sampler view reference counting bug in glDraw/CopyPixels
Use pipe_sampler_view_reference() instead of ordinary assignment.
Also add a new sanity check assertion.
Fixes piglit gl-1.0-drawpixels-color-index test crash. But note
that the test still fails.
Cc: "10.4, 10.5" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Brian Paul [Mon, 16 Feb 2015 18:23:06 +0000 (11:23 -0700)]
swrast: fix multiple color buffer writing
If a fragment program wrote to more than one color buffer, the
first fragment color got replicated to all dest buffers. This
fixes 5 piglit FBO tests, including fbo-drawbuffers-arbfp.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45348
Cc: "10.4, 10.5" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Brian Paul [Mon, 16 Feb 2015 18:12:40 +0000 (11:12 -0700)]
mesa: remove unused _math_trans_4chan()
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Lucas Stach [Thu, 19 Feb 2015 13:52:49 +0000 (14:52 +0100)]
install-lib-links: don't depend on .libs directory
This snippet can be included in Makefiles that may, depending on the
project configuration, not actually build any installable libraries.
In that case we don't have anything to depend on and this part of
the makefile may be executed before the .libs directory is created,
so do not depend on it being there.
Cc: "10.3 10.4 10.5" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Francisco Jerez [Wed, 11 Feb 2015 16:15:44 +0000 (18:15 +0200)]
i965/vec4: Calculate register allocation q values manually.
This fixes a regression in the running time of Piglit introduced by
commit
78e9043475d4bed8b50f7e413963c960fa0935bb, which increased the
number of register allocation classes set up by the VEC4 back-end
from 2 to 16. The algorithm used by ra_set_finalize() to calculate
them is unnecessarily expensive, do it manually like the FS back-end
does.
Reported-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Fri, 30 Jan 2015 15:50:35 +0000 (17:50 +0200)]
i965: Don't compact instructions with unmapped bits.
Some instruction bits don't have a mapping defined to any compacted
instruction field. If they're ever set and we end up compacting the
instruction they will be forced to zero. Avoid using compaction in such
cases.
v2: Align multiple lines of an expression to the same column. Change
conditional compaction of 3-source instructions to an
assertion. (Matt)
v3: The 3-source instruction bit 105 is part of SourceIndex on CHV.
Add assertion that reserved bit 7 is not set. (Matt)
Document overlap with UIP and 64-bit immediate fields.
v4: Make some more unmapped bit checks assertions. (Matt)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 4 Feb 2015 16:24:47 +0000 (18:24 +0200)]
i965: Handle F16TO32/F32TO16 with dword src/dst consistently on both back-ends.
Due to the way it's implemented in hardware, the F16TO32/F32TO16
instructions require the source/destination register to be of some
16-bit type in Align1 mode, while they require it to be some 32-bit
type in Align16 mode (and as an undocumented feature the high 16 bits
of the destination register are zeroed out in the case of the F32TO16
instruction on Gen7). Make their behaviour consistent so you can
specify a 32 bit register type as source or destination and get
predictable results in the most significant bits no matter what access
mode is being used.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 4 Feb 2015 16:08:47 +0000 (18:08 +0200)]
i965/gen8: Fix F32TO16 in vec4 mode if the source and destination registers alias.
We cannot zero out the destination register if it overlaps with the
source. Use an Align1 instruction instead to zero out the high 16
bits after the conversion to half float.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 4 Feb 2015 15:58:49 +0000 (17:58 +0200)]
i965/fs: Replace ud_reg_to_w() with a more general helper function.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Tue, 3 Feb 2015 18:34:17 +0000 (20:34 +0200)]
i965/vec4: Don't attempt to reduce swizzles of send from GRF instructions.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Tue, 3 Feb 2015 20:48:27 +0000 (22:48 +0200)]
i965/vec4: Fix constant propagation across different types.
If the source type differs from the original type of the constant we
need to bit-cast it before propagating, otherwise the original type
information will be lost. If the constant was a vector float there
isn't much we can do, because the result of bit-casting the component
values of a vector float cannot itself be represented as an immediate.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Samuel Iglesias Gonsalvez [Tue, 25 Nov 2014 15:36:53 +0000 (16:36 +0100)]
glsl: A shader cannot redefine or overload built-in functions in GLSL ES 3.00
Create a new search function to look for matching built-in functions by name
and use it for built-in function redefinition or overload in GLSL ES 3.00.
GLSL ES 3.0 spec, chapter 6.1 "Function Definitions", page 71
"A shader cannot redefine or overload built-in functions."
While in GLSL ES 1.0 specification, chapter 8 "Built-in Functions"
"User code can overload the built-in functions but cannot redefine them."
So this check is specific to GLSL ES 3.00.
This patch fixes the following dEQP tests:
dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function_vertex
dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function_fragment
dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function_vertex
dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function_fragment
No piglit regressions.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eduardo Lima Mitev [Mon, 15 Dec 2014 10:30:21 +0000 (11:30 +0100)]
mesa: Adds check for integer internal format and num samples in glRenderbufferStorageMultisample
Per GLES3 specification, section 4.4 Framebuffer objects page 198, "If
internalformat is a signed or unsigned integer format and samples is greater
than zero, then the error INVALID_OPERATION is generated.".
Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.buffer.renderbuffer_storage_multisample
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eduardo Lima Mitev [Tue, 16 Dec 2014 08:15:07 +0000 (09:15 +0100)]
mesa: Returns correct error values from gl(Get)SamplerParameter*() on GL-ES 3.0+
'3.8.2 Sampler Objects' section of the GL-ES 3.0 specification states:
"An INVALID_OPERATION error is generated if sampler is not the name
of a sampler object previously returned from a call to GenSamplers."
In desktop GL, an GL_INVALID_VALUE is returned instead.
Fixes 6 dEQP failing tests:
* dEQP-GLES3.functional.negative_api.shader.get_sampler_parameteriv
* dEQP-GLES3.functional.negative_api.shader.get_sampler_parameterfv
* dEQP-GLES3.functional.negative_api.shader.sampler_parameteri
* dEQP-GLES3.functional.negative_api.shader.sampler_parameteriv
* dEQP-GLES3.functional.negative_api.shader.sampler_parameterf
* dEQP-GLES3.functional.negative_api.shader.sampler_parameterfv
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ilia Mirkin [Thu, 19 Feb 2015 06:44:44 +0000 (01:44 -0500)]
glsl: remove bogus 'd' constant qualifiers
0.0 is a double anyways. Apparently my version of gcc was happy with
0.0d as well, but this is not true of all compilers.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89218
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Thu, 19 Feb 2015 06:38:58 +0000 (01:38 -0500)]
st/mesa: don't die for ETC2 formats when no driver support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Eric Anholt [Mon, 10 Nov 2014 19:16:30 +0000 (11:16 -0800)]
nir: Add an ALU op builder kind of like ir_builder.h
v2: Rebase on the nir_opcodes.h python code generation support.
v3: Use SSA values, and set an appropriate writemask on dot products.
v4: Make the arguments be SSA references as well. This lets you stack up
expressions in the arguments of other expressions, at the cost of
having to insert a fmov/imov if you want to swizzle. Also, add
the generated file to NIR_GENERATED_FILES.
v5: Use more pythonish style for iterating the list.
v6: Infer the size of the dest from the size of the srcs, and auto-swizzle
a single small src out to the appropriate size.
v7: Add little helpers for initializing the struct, add a typedef for the
struct like other nir types have.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v6)
Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (v7)
Ilia Mirkin [Wed, 18 Feb 2015 19:53:26 +0000 (14:53 -0500)]
docs: mark ARB_gpu_shader_fp64 as done in core
No driver support... yet. But core is ready.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sun, 8 Feb 2015 08:42:51 +0000 (03:42 -0500)]
glsl/tests: add DOUBLE types
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Thu, 17 Jul 2014 21:59:32 +0000 (17:59 -0400)]
glsl: add a lowering pass for frexp/ldexp with double arguments
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 14 Aug 2014 10:21:46 +0000 (20:21 +1000)]
glsl: lower double optional passes (v2)
These lowering passes are optional for the backend to request, currently
the TGSI softpipe backend most likely the r600g backend would want to use
these passes as is. They aim to hit the gallium opcodes from the standard
rounding/truncation functions.
v2: also lower floor in mod_to_floor
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 14 Aug 2014 08:48:57 +0000 (18:48 +1000)]
glsl: implement double builtin functions
This implements the bulk of the builtin functions for fp64 support.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 14 Aug 2014 08:44:35 +0000 (18:44 +1000)]
glsl/lower_instructions: add double lowering passes
This lowers double dot product and lrp to fma.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 14 Aug 2014 08:44:50 +0000 (18:44 +1000)]
glsl: enable/disable certain lowering passes for doubles
We want to restrict some lowering passes to floats only,
and enable other for doubles.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tapani Pälli [Mon, 11 Aug 2014 09:03:54 +0000 (12:03 +0300)]
glsl: validate output types for shader stages
Patch fixes Piglit test:
arb_gpu_shader_fp64/preprocessor/fs-output-double.frag
and adds additional validation for shader outputs.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 14 Aug 2014 08:48:09 +0000 (18:48 +1000)]
glsl: add double support to lower_mat_op_to_vec
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 10:11:58 +0000 (12:11 +0200)]
glsl: Linking support for doubles
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 10:10:26 +0000 (12:10 +0200)]
glsl: Support double loop control
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 10:09:04 +0000 (12:09 +0200)]
glsl: Support double inouts
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 10:07:34 +0000 (12:07 +0200)]
glsl/lexer: Support double floats
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 10:06:20 +0000 (12:06 +0200)]
glsl/parser: Support double floats
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 10:04:58 +0000 (12:04 +0200)]
glsl/ast: Support double floats
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 10:00:11 +0000 (12:00 +0200)]
glsl: Add ubo lowering support for doubles
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 09:58:05 +0000 (11:58 +0200)]
glsl: Add support doubles in optimization passes
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 09:54:39 +0000 (11:54 +0200)]
glsl/ir: Add builder support for functions with double floats
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 09:53:10 +0000 (11:53 +0200)]
glsl/ir: Add builtin constant function support for doubles
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 10:53:26 +0000 (12:53 +0200)]
glsl/ir: Add cloning support for doubles
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 10:52:19 +0000 (12:52 +0200)]
glsl/ir: Add printing support for doubles
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 09:50:43 +0000 (11:50 +0200)]
glsl/ir: Add builtin function support for doubles
v2: add d2b, more ir_constant stuff (Ilia)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Tue, 10 Feb 2015 08:02:09 +0000 (03:02 -0500)]
glsl: fix uniform linking logic in the presence of structs
Add a enter/leave record callback so that the offset may be aligned to
the proper value. Otherwise only leaf fields are called, and the first
field needs to be aligned to the outer struct's base alignment while the
last field needs to be aligned to the inner struct's base alignment.
This removes most usage of the last field/record type values passed into
visit_field.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Sat, 14 Feb 2015 03:03:47 +0000 (22:03 -0500)]
glsl: teach std140_base_alignment about samplers
These functions are about to be used more aggressively for determining
uniform layout. Samplers may be inside of structs, and it's easier to
reuse the existing base alignment logic.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 5 Feb 2015 09:44:02 +0000 (11:44 +0200)]
glsl: Uniform linking support for doubles
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 09:38:44 +0000 (11:38 +0200)]
glsl: Add double builtin type generation
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Wed, 11 Jun 2014 03:36:12 +0000 (13:36 +1000)]
glsl: add ARB_gpu_shader_fp64 to the glsl extensions. (v2)
v2: add define bit (Tapani Pälli)
Patch makes following Piglit tests pass:
arb_gpu_shader_fp64/preprocessor/define.vert
arb_gpu_shader_fp64/preprocessor/define.frag
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>