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Hal Finkel [Sun, 11 May 2014 16:23:29 +0000 (16:23 +0000)]
[PowerPC] On PPC32, 128-bit shifts might be runtime calls
The counter-loops formation pass needs to know what operations might be
function calls (because they can't appear in counter-based loops). On PPC32,
128-bit shifts might be runtime calls (even though you can't use __int128 on
PPC32, it seems that SROA might form them).
Fixes PR19709.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208501
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David Blaikie [Sun, 11 May 2014 16:08:41 +0000 (16:08 +0000)]
DwarfUnit: Pick a winner between isTypeSigned and isUnsignedDIType.
And the winner by a nose is isUnsignedDIType, for no particular reason.
These two functions were just complements of each other and used in very
related code, so refactor callers to just use one of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208500
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David Blaikie [Sun, 11 May 2014 15:56:59 +0000 (15:56 +0000)]
DwarfUnit: Factor out calling isUnsignedDIType into a utility function so each caller of emitConstantValue doesn't have to call it separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208496
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David Blaikie [Sun, 11 May 2014 15:47:39 +0000 (15:47 +0000)]
DwarfUnit: Share common constant value emission between APInts of small (<= 64 bit) and MCOperand immediates.
Doesn't seem a good reason to duplicate this code (it was more literally
duplicated prior to r208494, and while the dataN code /does/ actually
fire in this case, it doesn't seem necessary (and the DWARF standard
recommends using udata/sdata pervasively instead of dataN, so as to
indicate signedness of the values))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208495
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David Blaikie [Sun, 11 May 2014 15:06:20 +0000 (15:06 +0000)]
DebugInfo: Simplify constant value emission.
This code looks to have become dead at some time in the past. I tried to
reproduce cases where LLVM would emit constants with dataN, but could
not. Upon inspection it seems the code doesn't do that anymore - the
only time a size is provided by isTypeSigned is when the type is signed,
and in those cases we use sdata. dataN is only used for unsigned types
and isTypeSigned doesn't provide a value for sizeInBits in that case.
Remove the dead cases/size plumbing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208494
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Benjamin Kramer [Sun, 11 May 2014 10:28:58 +0000 (10:28 +0000)]
SLPVectorizer: Instead of just performing CSE on dead blocks ignore them completely.
Turns out that there is a very cheap way of testing whether a block is dead,
just look it up in the DomTree. We have to do this anyways so just ignore
unreachable blocks before sorting by domination. This restores a proper
ordering for std::stable_sort when dead code is present.
Covered by existing tests & buildbots running in STL debug mode (MSVC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208492
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Simon Atanasyan [Sun, 11 May 2014 08:48:09 +0000 (08:48 +0000)]
[llvm-readobj] Print values of FLAGS and MIPS_FLAGS dynamic table tags
in a human readable form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208489
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Serge Pavlov [Sun, 11 May 2014 08:46:12 +0000 (08:46 +0000)]
Reorder shuffle and binary operation.
This patch enables transformations:
BinOp(shuffle(v1), shuffle(v2)) -> shuffle(BinOp(v1, v2))
BinOp(shuffle(v1), const1) -> shuffle(BinOp, const2)
They allow to eliminate extra shuffles in some cases.
Differential Revision: http://reviews.llvm.org/D3525
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208488
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Filipe Cabecinhas [Sun, 11 May 2014 08:12:56 +0000 (08:12 +0000)]
Fixed a bug when lowering build_vector (PR19694)
When lowering build_vector to an insertps, we would still lower it, even
if the source vectors weren't v4x32. This would break on avx if the source
was a v8x32. We now check the type of the source vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208487
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Vincent Lejeune [Sat, 10 May 2014 19:18:39 +0000 (19:18 +0000)]
R600/SI: Fold fabs/fneg into src input modifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208480
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Vincent Lejeune [Sat, 10 May 2014 19:18:33 +0000 (19:18 +0000)]
R600/SI: Prettier display of input modifiers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208479
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Vincent Lejeune [Sat, 10 May 2014 19:18:25 +0000 (19:18 +0000)]
R600/SI: Use pseudo instruction for fabs/clamp/fneg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208478
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Benjamin Kramer [Sat, 10 May 2014 17:47:18 +0000 (17:47 +0000)]
SCEV: Use range-based for loop and fold variable into assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208476
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Tim Northover [Sat, 10 May 2014 07:37:50 +0000 (07:37 +0000)]
ARM64: fix SELECT_CC lowering in absence of NaNs.
We were swapping the true & false results while testing for FMAX/FMIN,
but not putting them back to the original state if the later checks
failed.
Should fix PR19700.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208469
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Kevin Enderby [Fri, 9 May 2014 23:57:49 +0000 (23:57 +0000)]
Fix llvm-nm to print the full 64-bit address for symbols in 64-bit object files.
The implementation might be better to have a method is64Bit() in the class
SymbolicFile instead of having the static routine isSymbolList64Bit() in
llvm-nm.cpp . But this is very much in the sprit of isObject() and
getNMTypeChar() in llvm-nm.cpp that has a series of if else statements
based on the specific class of the SymbolicFile. I can update this if
folks would like.
Also the tests were updated to be explicit about checking the address for
64-bits or 32-bits from object files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208463
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Benjamin Kramer [Fri, 9 May 2014 23:28:49 +0000 (23:28 +0000)]
SLPVectorizer: When sorting by domination for CSE don't assert on unreachable code.
There is no total ordering if the CFG is disconnected. We don't care if we
catch all CSE opportunities in dead code either so just exclude ignore them in
the assert.
PR19646
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208461
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Reid Kleckner [Fri, 9 May 2014 22:56:42 +0000 (22:56 +0000)]
Revert "[ms-cxxabi] Add a new calling convention that swaps 'this' and 'sret'"
This reverts commit r200561.
This calling convention was an attempt to match the MSVC C++ ABI for
methods that return structures by value. This solution didn't scale,
because it would have required splitting every CC available on Windows
into two: one for methods and one for free functions.
Now that we can put sret on the second arg (r208453), and Clang does
that (r208458), revert this hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208459
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Sebastian Pop [Fri, 9 May 2014 22:45:07 +0000 (22:45 +0000)]
move findArrayDimensions to ScalarEvolution
we do not use the information from SCEVAddRecExpr to compute the shape of the array,
so a better place for this function is in ScalarEvolution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208456
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Sebastian Pop [Fri, 9 May 2014 22:45:02 +0000 (22:45 +0000)]
fix typo in debug message
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208455
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Reid Kleckner [Fri, 9 May 2014 22:32:13 +0000 (22:32 +0000)]
Allow sret on the second parameter as well as the first
MSVC always places the implicit sret parameter after the implicit this
parameter of instance methods. We used to handle this for
x86_thiscallcc by allocating the sret parameter on the stack and leaving
the this pointer in ecx, but that doesn't handle alternative calling
conventions like cdecl, stdcall, fastcall, or the win64 convention.
Instead, change the verifier to allow sret on the second parameter.
This also requires changing the Mips and X86 backends to return the
argument with the sret parameter, instead of assuming that the sret
parameter comes first.
The Sparc backend also returns sret parameters in a register, but I
wasn't able to update it to handle secondary sret parameters. It
currently calls report_fatal_error if you feed it an sret in the second
parameter.
Reviewers: rafael.espindola, majnemer
Differential Revision: http://reviews.llvm.org/D3617
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208453
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Reid Kleckner [Fri, 9 May 2014 21:52:48 +0000 (21:52 +0000)]
Fix ARM intrinsics-overflow.ll test on Windows
Windows on ARM only supports thumb mode execution, so we have to
explicitly pick some non-Windows OS to test ARM mode codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208448
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Rafael Espindola [Fri, 9 May 2014 21:49:17 +0000 (21:49 +0000)]
Don't crash on redefinitions.
One error we were not deleting the alias or putting it in the Module. The
end result is that there was an use left of the aliasee when the module was
deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208447
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Jonathan Roelofs [Fri, 9 May 2014 18:06:22 +0000 (18:06 +0000)]
Fix broken build
ARM64 backend was missing a required_library entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208437
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Louis Gerbarg [Fri, 9 May 2014 17:02:49 +0000 (17:02 +0000)]
Add custom lowering for add/sub with overflow intrinsics to ARM
This patch adds support to ARM for custom lowering of the
llvm.{u|s}add.with.overflow.i32 intrinsics for i32/i64. This is particularly useful
for handling idiomatic saturating math functions as generated by
InstCombineCompare.
Test cases included.
rdar://
14853450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208435
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Louis Gerbarg [Fri, 9 May 2014 17:02:46 +0000 (17:02 +0000)]
Add ExtractValue instruction to SimplifyCFG's ComputeSpeculationCost
Since ExtractValue is not included in ComputeSpeculationCost CFGs containing
ExtractValueInsts cannot be simplified. In particular this interacts with
InstCombineCompare's tendency to insert add.with.overflow intrinsics for
certain idiomatic math operations, preventing optimization.
This patch adds ExtractValue to the ComputeSpeculationCost. Test case included
rdar://
14853450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208434
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Tom Stellard [Fri, 9 May 2014 16:42:22 +0000 (16:42 +0000)]
R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208432
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Tom Stellard [Fri, 9 May 2014 16:42:21 +0000 (16:42 +0000)]
R600/SI: Fix SMRD pattern for offsets > 32 bits
We were dropping the high bits of 64-bit immediate offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208431
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Tom Stellard [Fri, 9 May 2014 16:42:19 +0000 (16:42 +0000)]
R600: Expand i64 SELECT_CC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208430
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Tom Stellard [Fri, 9 May 2014 16:42:16 +0000 (16:42 +0000)]
R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208429
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James Molloy [Fri, 9 May 2014 16:20:53 +0000 (16:20 +0000)]
Attempt to pacify the bots - this commit requires asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208424
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Rafael Espindola [Fri, 9 May 2014 16:01:06 +0000 (16:01 +0000)]
Use auto and clang-format this snippet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208421
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Rafael Espindola [Fri, 9 May 2014 15:49:02 +0000 (15:49 +0000)]
Run clang-format in small sections of code to make a patch easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208419
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Rafael Espindola [Fri, 9 May 2014 14:39:25 +0000 (14:39 +0000)]
Delete trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208416
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Rafael Espindola [Fri, 9 May 2014 14:31:07 +0000 (14:31 +0000)]
Delete trailing white space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208415
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Daniel Sanders [Fri, 9 May 2014 14:06:17 +0000 (14:06 +0000)]
[mips] Marked up instructions added in MIPS-IV and tested that IAS for -mcpu=mips[123] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-IV that was available in MIPS32
A small number of instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now.
Depends on D3676
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208414
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Oliver Stannard [Fri, 9 May 2014 14:01:47 +0000 (14:01 +0000)]
ARM: HFAs must be passed in consecutive registers
When using the ARM AAPCS, HFAs (Homogeneous Floating-point Aggregates) must
be passed in a block of consecutive floating-point registers, or on the stack.
This means that unused floating-point registers cannot be back-filled with
part of an HFA, however this can currently happen. This patch, along with the
corresponding clang patch (http://reviews.llvm.org/D3083) prevents this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208413
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Simon Atanasyan [Fri, 9 May 2014 13:57:33 +0000 (13:57 +0000)]
[yaml2obj] Follow-up to the r208228 and r208406. Remove duplicated YAML
map keys.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208412
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Rafael Espindola [Fri, 9 May 2014 13:54:40 +0000 (13:54 +0000)]
Remove trailing white space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208411
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Daniel Sanders [Fri, 9 May 2014 13:15:07 +0000 (13:15 +0000)]
[mips] Remove unused CondMov feature bit
Summary:
No functional change
Depends on D3675
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208410
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Daniel Sanders [Fri, 9 May 2014 13:02:27 +0000 (13:02 +0000)]
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-III that was available in MIPS32
A small number of instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now.
There's some obvious InstAlias's that ought to be marked MIPS-III but arent.
This is because they are not currently tested. I intend to catch these with
a final pass through the tablegen records to find tablegen records without
ISA annotations.
Depends on D3674
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208408
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NAKAMURA Takumi [Fri, 9 May 2014 11:24:18 +0000 (11:24 +0000)]
Mark yaml2obj-elf-x86-rel.yaml as XFAIL:vg_leak for now. This has two pairs of duplicate hashes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208406
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Andrea Di Biagio [Fri, 9 May 2014 11:08:23 +0000 (11:08 +0000)]
Fix 80 col violation.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208405
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Benjamin Kramer [Fri, 9 May 2014 09:48:03 +0000 (09:48 +0000)]
[asan] Stop leaking X86Operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208400
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Daniel Sanders [Fri, 9 May 2014 09:46:21 +0000 (09:46 +0000)]
[mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6
Summary:
Adds MIPS32r6/MIPS64r6 and checks the compatibility requirements for these
processors.
I've also included comments to describe removed and re-encoded instructions,
along with placeholder def's for the new instructions but there are no
functional changes to codegen at this point.
Reviewers: jkolek, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3622
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208399
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Daniel Sanders [Fri, 9 May 2014 09:32:01 +0000 (09:32 +0000)]
[mips] Added missing daddu test to the valid instruction tests.
Summary: Depends on D3673
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208398
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Daniel Sanders [Fri, 9 May 2014 09:24:49 +0000 (09:24 +0000)]
[mips] Added missing dsra -> dsrav and sra -> srav aliases.
Summary: dsll, dsrl, sll, and srl already exist.
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3673
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208397
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Alp Toker [Fri, 9 May 2014 08:57:32 +0000 (08:57 +0000)]
MemoryBuffer: don't force mmap when stat fails
Fix error handling introduced in r127426 that could result in MemoryBuffers not
having null termination.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208396
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Alp Toker [Fri, 9 May 2014 08:57:06 +0000 (08:57 +0000)]
MemoryBuffer: remove unusued definitions
These were made redundant back in r186560.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208395
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NAKAMURA Takumi [Fri, 9 May 2014 08:18:33 +0000 (08:18 +0000)]
test/TableGen: Remove XFAIL:vg_leak out of 3 tests corresponding to r208293.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208393
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Rafael Espindola [Fri, 9 May 2014 02:56:16 +0000 (02:56 +0000)]
Don't indent inside a namespace. Don't duplicate a function name in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208389
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David Blaikie [Fri, 9 May 2014 02:26:36 +0000 (02:26 +0000)]
Remove use of = default/= delete as they're unsupported on MSVC2012
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208388
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Saleem Abdulrasool [Fri, 9 May 2014 00:58:32 +0000 (00:58 +0000)]
ARM: support PIC on Windows on ARM
Handle lowering of global addresses for PIC mode compilation on Windows. Always
use the movw/movt load to load the address as Windows on ARM requires ARMv7+ and
is a pure Thumb environment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208385
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Nick Lewycky [Fri, 9 May 2014 00:49:03 +0000 (00:49 +0000)]
printCustom is only used in PseudoSourceValue, remove it from Value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208383
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Rafael Espindola [Fri, 9 May 2014 00:36:18 +0000 (00:36 +0000)]
Add missing linkage predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208379
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Lang Hames [Fri, 9 May 2014 00:11:18 +0000 (00:11 +0000)]
[RuntimeDyld] Unify the RuntimeDyldMachO resolve.*Relocation method signatures
around RelocationEntries, rather than passing the same information via loose
arguments.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208375
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Filipe Cabecinhas [Thu, 8 May 2014 23:16:08 +0000 (23:16 +0000)]
Optimize shufflevector that copies an i64/f64 and zeros the rest.
Summary:
Also ran clang-format on the function. The code added is the last else
if block.
Reviewers: nadav, craig.topper, delena
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D3518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208372
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Quentin Colombet [Thu, 8 May 2014 23:12:27 +0000 (23:12 +0000)]
[TargetInstrInfo] Fix the implementation of commuteInstruction to match the
comment of the API.
Relaxes the behavior of TargetInstrInfo::commuteInstruction when
TargetInstrInfo::findCommutedOpIndices returns false.
Previously TargetInstrInfo triggered a fatal error in such situation whereas based
on the comment in the API it should just return nullptr. Indeed the only
precondition that should be ensured is that the instruction must be commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208371
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Nick Lewycky [Thu, 8 May 2014 23:04:46 +0000 (23:04 +0000)]
Improve wording to make it sounds more like a change than an analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208370
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Justin Bogner [Thu, 8 May 2014 22:45:07 +0000 (22:45 +0000)]
test/CodeGen: Check that the correct register is used in a store
This tightens up r208351 to ensure that a store is fed with the
correct value.
Thanks to Quentin Colombet for spotting this!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208368
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David Blaikie [Thu, 8 May 2014 22:24:51 +0000 (22:24 +0000)]
Reapply r207876 (Try simplifying LexicalScopes ownership again) including a workaround for an MSVC2012 bug regarding forward_as_tuple
(r207876 was reverted in r208131 after seeing some consistent buildbot
failure for MSVC 2012. The original commits were in r207724-r207726)
Takumi was nice enough to dig into this and locate this Microsoft
Connect issue:
http://connect.microsoft.com/VisualStudio/feedback/details/814899/forward-as-tuple-debug-implementation-error
describing a bug in MSVC2012's forward_as_tuple implementation.
Since the parameters in this instance are trivial/small, pass them by
value (using make_tuple) instead of perfectly-forwarded tuple of rvalue
references (involving the broken forward_as_tuple). Hopefully this will
satisfy MSVC2012.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208364
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David Blaikie [Thu, 8 May 2014 21:53:33 +0000 (21:53 +0000)]
Missed formatting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208362
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David Blaikie [Thu, 8 May 2014 21:52:29 +0000 (21:52 +0000)]
StringMap: Move assignment and move construction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208361
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David Blaikie [Thu, 8 May 2014 21:52:26 +0000 (21:52 +0000)]
StringMap: Replace faux-copyability with faux-movability, which is sufficient.
This behavior was added to support StringMaps of StringMaps, default +
move construction are sufficient for this.
Real move construction support coming soon (& probably copy construction
too).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208360
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David Blaikie [Thu, 8 May 2014 21:52:23 +0000 (21:52 +0000)]
StringMap support for move-only values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208359
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Tobias Grosser [Thu, 8 May 2014 21:43:19 +0000 (21:43 +0000)]
Correct formatting.
Sorry for the commit spam. My clang-format crashed on me and the vim
plugin did not print an error, but instead just left the formatting
untouched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208358
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Tobias Grosser [Thu, 8 May 2014 21:32:59 +0000 (21:32 +0000)]
Use std::remove_if to remove elements from a vector
Suggested-by: Benjamin Kramer <benny.kra@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208357
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Michael Zolotukhin [Thu, 8 May 2014 19:50:24 +0000 (19:50 +0000)]
[InstCombine] Some cleanup in optimization of redundant insertvalue instructions.
And one more test added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208355
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Rafael Espindola [Thu, 8 May 2014 19:30:17 +0000 (19:30 +0000)]
Use range loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208353
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Justin Bogner [Thu, 8 May 2014 18:53:56 +0000 (18:53 +0000)]
Make a CodeGen test more robust against vector register selection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208351
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Jyotsna Verma [Thu, 8 May 2014 18:47:08 +0000 (18:47 +0000)]
[Hexagon] Add new InstrItinClass to support timing classes.
This patch doesn't introduce any functionality change. Test cases will be
added later when v5 support is added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208349
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Rafael Espindola [Thu, 8 May 2014 18:40:06 +0000 (18:40 +0000)]
Use for range loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208348
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Sebastian Pop [Thu, 8 May 2014 18:38:58 +0000 (18:38 +0000)]
add testcase for r208237: do not collect undef terms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208347
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Rafael Espindola [Thu, 8 May 2014 18:17:44 +0000 (18:17 +0000)]
Use range loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208346
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Matt Arsenault [Thu, 8 May 2014 18:01:56 +0000 (18:01 +0000)]
R600: Promote f64 vector load/stores to i64 for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208344
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Rafael Espindola [Thu, 8 May 2014 17:57:50 +0000 (17:57 +0000)]
Use a range loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208343
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Andrea Di Biagio [Thu, 8 May 2014 17:44:04 +0000 (17:44 +0000)]
[X86] Add target specific combine rules to fold SSE2/AVX2 packed arithmetic shift intrinsics.
This patch teaches the backend how to combine packed SSE2/AVX2 arithmetic shift
intrinsics.
The rules are:
- Always fold a packed arithmetic shift by zero to its first operand;
- Convert a packed arithmetic shift intrinsic dag node into a ISD::SRA only if
the shift count is known to be smaller than the vector element size.
This patch also teaches to function 'getTargetVShiftByConstNode' how fold
target specific vector shifts by zero.
Added two new tests to verify that the DAGCombiner is able to fold
sequences of SSE2/AVX2 packed arithmetic shift calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208342
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Saleem Abdulrasool [Thu, 8 May 2014 17:11:29 +0000 (17:11 +0000)]
test: fix test on Windows
When building on Windows, the default target is Windows. Windows on ARM does
not support ARM mode compilation, resulting in test failures. Simply specify a
triple to ensure that we are testing the correct behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208340
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NAKAMURA Takumi [Thu, 8 May 2014 17:06:10 +0000 (17:06 +0000)]
Mark test/TableGen/listconcat.td as XFAIL:vg_leak. llvm-tblgen is ignorant of vg_leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208337
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Daniel Sanders [Thu, 8 May 2014 16:12:31 +0000 (16:12 +0000)]
[mips] Add PredicateControl to InstAlias's
Summary:
No functional change
Depends on D3649
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3672
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208334
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Bradley Smith [Thu, 8 May 2014 15:40:39 +0000 (15:40 +0000)]
[ARM64] Add diagnostics for expected arithmetic shifts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208330
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Bradley Smith [Thu, 8 May 2014 15:39:58 +0000 (15:39 +0000)]
[ARM64] Re-work parsing of ADD/SUB shifted immediate operands
The parsing of ADD/SUB shifted immediates needs to be done explicitly so
that better diagnostics can be emitted, as a side effect this also
removes some of the hacks in the current method of handling this operand
type.
Additionally remove manual CMP aliasing to ADD/SUB and use InstAlias
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208329
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Daniel Sanders [Thu, 8 May 2014 15:17:29 +0000 (15:17 +0000)]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS.
Summary:
I've noticed a bug in my test generator script that caused 64-bit objects
to be disassembled as if it were using the O32 ABI, giving the wrong register
names. As a result, it generated assembly files that are rejected by GAS when
assembling for the correct ABI. This was caused by the generator setting the
ELF e_flags incorrectly before disassembling the object.
This patch corrects the invalid tests that have already been committed by
replacing the ABI-dependent register names with numeric registers. In addition
to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed
to produce the invalid-*.s tests which test that instructions defined in later ISA's
are not accepted.
Depends on D3648
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208327
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Bradley Smith [Thu, 8 May 2014 14:12:12 +0000 (14:12 +0000)]
[ARM64] Ensure immediates in extend operands are in a valid range
Also emit a more useful diagnostic when they are not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208318
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Bradley Smith [Thu, 8 May 2014 14:11:16 +0000 (14:11 +0000)]
[ARM64] Check for proper immediate in shift/extend operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208317
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Christian Pirker [Thu, 8 May 2014 14:06:24 +0000 (14:06 +0000)]
ARM big endian function argument passing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208316
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Hal Finkel [Thu, 8 May 2014 13:42:57 +0000 (13:42 +0000)]
Fix a spelling error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208314
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Daniel Sanders [Thu, 8 May 2014 13:02:11 +0000 (13:02 +0000)]
[mips] Implement l[wd]c3, and s[wd]c3.
Summary:
These instructions were added in MIPS-I, and MIPS-II but were removed in
MIPS-III. Interestingly, GAS continues to accept them when assembling for
MIPS-III.
For the moment, these instructions will follow GAS and accept them for
MIPS-III and newer but this will be tightened up when the invalid-*.s
tests are added.
Depends on D3647
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3648
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208311
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Ed Maste [Thu, 8 May 2014 13:00:15 +0000 (13:00 +0000)]
Add isOSFreeBSD triple test
For http://reviews.llvm.org/D3448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208309
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Dario Domizioli [Thu, 8 May 2014 12:54:43 +0000 (12:54 +0000)]
Revert test commit. Removed blank line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208308
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James Molloy [Thu, 8 May 2014 12:53:50 +0000 (12:53 +0000)]
[ARM64-BE] Teach fast-isel about how to set up sub-word stack arguments for big endian calls.
SelectionDAG already knows about this, but fast-isel was ignorant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208307
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Daniel Sanders [Thu, 8 May 2014 12:40:48 +0000 (12:40 +0000)]
[mips] Marked up instructions added in MIPS-II and tested that IAS for -mcpu=mips1 does not accept them
Summary:
A small number of instructions are rejected with the wrong error message.
These have been placed in a separate test for now. There seems to be some
parsing quirk that triggers when these instructions are disabled.
Depends on D3571
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3647
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208305
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Daniel Sanders [Thu, 8 May 2014 11:51:18 +0000 (11:51 +0000)]
[mips] Implement tlbp, tlbr, tlbwi, and tlbwr
Reviewers: vmedic, dsanders
Reviewed By: dsanders
Differential Revision: http://reviews.llvm.org/D3571
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208301
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Dario Domizioli [Thu, 8 May 2014 11:28:14 +0000 (11:28 +0000)]
Test commit. Added blank line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208298
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Tim Northover [Thu, 8 May 2014 10:30:56 +0000 (10:30 +0000)]
ARM64: make sure FastISel emits SSA MachineInstrs
We need to use a temporary register for a 2-step operation like REM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208297
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Evgeniy Stepanov [Thu, 8 May 2014 09:55:24 +0000 (09:55 +0000)]
[asan] Preserve flags in asm instrumentation.
Patch by Yuri Gorshenin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208296
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Daniel Sanders [Thu, 8 May 2014 09:29:28 +0000 (09:29 +0000)]
Use a vector of unique_ptrs to fix a memory leak introduced in r208179.
Also removed an inaccurate comment that stated that a DenseMap was used as
storage for the ListInit*'s. It's currently using a FoldingSet.
I expect there's a better way to fix this but I haven't found it yet. FoldingSet
is incompatible with the Pool template and I'm not sure if FoldingSet can be
safely replaced with a DenseMap of computed FoldingSetID's to ListInit*'s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208293
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Hal Finkel [Thu, 8 May 2014 09:14:44 +0000 (09:14 +0000)]
Move late partial-unrolling thresholds into the processor definitions
The old method used by X86TTI to determine partial-unrolling thresholds was
messy (because it worked by testing target features), and also would not
correctly identify the target CPU if certain target features were disabled.
After some discussions on IRC with Chandler et al., it was decided that the
processor scheduling models were the right containers for this information
(because it is often tied to special uop dispatch-buffer sizes).
This does represent a small functionality change:
- For generic x86-64 (which uses the SB model and, thus, will get some
unrolling).
- For AMD cores (because they still currently use the SB scheduling model)
- For Haswell (based on benchmarking by Louis Gerbarg, it was decided to bump
the default threshold to 50; we're working on a test case for this).
Otherwise, nothing has changed for any other targets. The logic, however, has
been moved into BasicTTI, so other targets may now also opt-in to this
functionality simply by setting LoopMicroOpBufferSize in their processor
model definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208289
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Tobias Grosser [Thu, 8 May 2014 07:55:34 +0000 (07:55 +0000)]
Revert "SCEV: Use I = vector<>.erase(I) to iterate and delete at the same time"
as committed in r208282. The original commit was incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208286
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Hao Liu [Thu, 8 May 2014 07:38:13 +0000 (07:38 +0000)]
AArch64/ARM64: Port NEON post-increment load/store with 2/3/4 vectors to ARM64 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208284
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Tobias Grosser [Thu, 8 May 2014 07:12:44 +0000 (07:12 +0000)]
SCEV: Use I = vector<>.erase(I) to iterate and delete at the same time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208282
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