OSDN Git Service
Simon Pilgrim [Sun, 2 Apr 2017 16:20:34 +0000 (16:20 +0000)]
[X86][MMX] Simplify tablegen patterns by always combining MOVDQ2Q from v2i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299336
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 2 Apr 2017 15:52:28 +0000 (15:52 +0000)]
[X86][MMX] Added support for subvector extraction to MMX register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299335
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Sun, 2 Apr 2017 15:05:18 +0000 (15:05 +0000)]
APInt.h: Prune \param(s) in \returns. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299334
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 2 Apr 2017 14:21:14 +0000 (14:21 +0000)]
Regenerate test with codegen. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299333
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 2 Apr 2017 13:59:37 +0000 (13:59 +0000)]
Regenerate test with codegen. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299332
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 2 Apr 2017 13:50:44 +0000 (13:50 +0000)]
Regenerate test. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299331
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Berlin [Sun, 2 Apr 2017 13:23:44 +0000 (13:23 +0000)]
NewGVN: Handle coercion of constant stores, loads, memory insts.
Summary:
Depends on D30928.
This adds support for coercion of stores and memory instructions that do not require insertion to process.
Another few tests down.
I added the relevant tests from rle.ll
Reviewers: davide
Subscribers: llvm-commits, Prazek
Differential Revision: https://reviews.llvm.org/D30929
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299330
91177308-0d34-0410-b5e6-
96231b3b80d8
Nikolai Bozhenov [Sun, 2 Apr 2017 13:14:30 +0000 (13:14 +0000)]
[BypassSlowDivision] Do not bypass division of hash-like values
Disable bypassing if one of the operands looks like a hash value. Slow
division often occurs in hashtable implementations and fast division is
never taken there because a hash value is extremely unlikely to have
enough upper bits set to zero.
A value is considered to be hash-like if it is produced by
1) XOR operation
2) Multiplication by a constant wider than the shorter type
3) PHI node with all incoming values being hash-like
Differential Revision: https://reviews.llvm.org/D28200
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299329
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 2 Apr 2017 13:10:20 +0000 (13:10 +0000)]
[X86][MMX] Add generic fptosi 4f32-4i32 test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299328
91177308-0d34-0410-b5e6-
96231b3b80d8
Zvi Rackover [Sun, 2 Apr 2017 10:42:21 +0000 (10:42 +0000)]
Add another interesting shufflevector test case for InstSimplify. NFC.
Test case shows opportunity to constant fold a shuffle with one variable
input vector operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299327
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 2 Apr 2017 06:59:43 +0000 (06:59 +0000)]
[X86] Use tcAdd/tcSubtract to implement the slow case of operator+=/operator-=.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299326
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 2 Apr 2017 06:59:41 +0000 (06:59 +0000)]
[APInt] Combine declaration and initialization. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299325
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 2 Apr 2017 06:59:38 +0000 (06:59 +0000)]
[APInt] Simplify some code by using operator+=(uint64_t) instead of doing a more complex assignment into a temporary APInt just to use the APInt operator+=.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299324
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 2 Apr 2017 06:59:36 +0000 (06:59 +0000)]
[APInt] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299323
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Berlin [Sun, 2 Apr 2017 05:09:15 +0000 (05:09 +0000)]
MemorySSA: Add support for caching clobbering access in stores
Summary:
This enables us to cache the clobbering access for stores, despite the
fact that we can't rewrite the use-def chains themselves.
Early testing shows that, after this change, for larger testcases, it will be a significant net positive (memory and time) to remove the walker caching.
Reviewers: george.burgess.iv, davide
Subscribers: Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D31567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299322
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 1 Apr 2017 21:50:10 +0000 (21:50 +0000)]
[APInt] Use conditional operator to simplify some code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299320
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 1 Apr 2017 21:50:08 +0000 (21:50 +0000)]
[APInt] Implement flipAllBitsSlowCase with tcComplement. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299319
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 1 Apr 2017 21:50:06 +0000 (21:50 +0000)]
[APInt] Fix indentation. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299318
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 1 Apr 2017 21:50:03 +0000 (21:50 +0000)]
[APInt] Implement AndAssignSlowCase using tcAnd. Do the same for Or and Xor. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299317
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 1 Apr 2017 20:30:57 +0000 (20:30 +0000)]
[APInt] Allow GreatestCommonDivisor to take rvalue inputs efficiently. Use moves instead of copies in the loop.
Summary:
GreatestComonDivisor currently makes a copy of both its inputs. Then in the loop we do one move and two copies, plus any allocation the urem call does.
This patch changes it to take its inputs by value so that we can do a move of any rvalue inputs instead of copying. Then in the loop we do 3 move assignments and no copies. This way the only possible allocations we have in the loop is from the urem call.
Reviewers: dblaikie, RKSimon, hans
Reviewed By: dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31572
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299314
91177308-0d34-0410-b5e6-
96231b3b80d8
Davide Italiano [Sat, 1 Apr 2017 19:47:52 +0000 (19:47 +0000)]
[WASM] Remove other comparison of unsigned expression >= 0.
This should finally fix the GCC 7 build with -Werror.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299313
91177308-0d34-0410-b5e6-
96231b3b80d8
Davide Italiano [Sat, 1 Apr 2017 19:40:51 +0000 (19:40 +0000)]
[WASM] Remove a set but never used variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299312
91177308-0d34-0410-b5e6-
96231b3b80d8
Davide Italiano [Sat, 1 Apr 2017 19:37:15 +0000 (19:37 +0000)]
[WASM] Remove an assertion that can never fire.
uint* is by definition always >=0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299311
91177308-0d34-0410-b5e6-
96231b3b80d8
Davide Italiano [Sat, 1 Apr 2017 19:30:17 +0000 (19:30 +0000)]
[AMDGPU] Garbage collect now unused dead code. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299310
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sat, 1 Apr 2017 19:05:11 +0000 (19:05 +0000)]
[InstSimplify] add constant folding for fdiv/frem
Also, add a helper function so we don't have to repeat this code for each binop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299309
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sat, 1 Apr 2017 18:44:03 +0000 (18:44 +0000)]
[InstSimplify] add tests for missed constant folding; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299308
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sat, 1 Apr 2017 18:40:30 +0000 (18:40 +0000)]
fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299307
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sat, 1 Apr 2017 15:53:12 +0000 (15:53 +0000)]
fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299305
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sat, 1 Apr 2017 15:05:54 +0000 (15:05 +0000)]
[DAGCombiner] enable vector transforms for any/all {sign} bits set/clear
The code already allowed vector types in via "isInteger" (which might want
a more specific name), so use splat-friendly constant predicates to match
those types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299304
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sat, 1 Apr 2017 14:32:18 +0000 (14:32 +0000)]
[PowerPC, x86] add vector tests for any/all {sign} bits set/clear; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299303
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Berlin [Sat, 1 Apr 2017 10:04:28 +0000 (10:04 +0000)]
MemorySSA: Update expensive checking version of def_chain_iterator for templating changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299301
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Berlin [Sat, 1 Apr 2017 09:44:33 +0000 (09:44 +0000)]
NewGVN: Don't try to kill off the stored value of stores when
processing the congruence class of the store.
Because we use the stored value of a store as the def, it isn't dead
just because it appears as a def when it comes from a store.
Note: I have not hit any cases with the memory code as it is where
this breaks anything, just because of what memory congruences we
actually allow. In a followup that improves memory congruence,
this bug actually breaks real stuff (but the verifier catches it).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299300
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Berlin [Sat, 1 Apr 2017 09:44:29 +0000 (09:44 +0000)]
NewGVN: Clean up GVNExpression memory hierarchy, restructure hash computation a bit so we don't have to redefine it for loads, stores, and calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299299
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Berlin [Sat, 1 Apr 2017 09:44:24 +0000 (09:44 +0000)]
NewGVN: Use def_chain iterator in singleReachablePhiPath instead of recursion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299298
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Berlin [Sat, 1 Apr 2017 09:44:19 +0000 (09:44 +0000)]
Move def_chain iterator to MemorySSA.h so it can be reused
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299297
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Berlin [Sat, 1 Apr 2017 09:44:14 +0000 (09:44 +0000)]
MemorySSA.h - make clang-format happy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299296
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Berlin [Sat, 1 Apr 2017 09:01:12 +0000 (09:01 +0000)]
MemorySSA: Push const correctness further.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299295
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Berlin [Sat, 1 Apr 2017 08:59:45 +0000 (08:59 +0000)]
MemorySSA: Kill the WalkTargetCache now that we have getBlockDefs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299294
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 1 Apr 2017 06:50:00 +0000 (06:50 +0000)]
[APInt] Implement operator! using operator==(uint64_t). NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299293
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 1 Apr 2017 05:08:57 +0000 (05:08 +0000)]
[APInt] Remove the mul/urem/srem/udiv/sdiv functions from the APIntOps namespace. Replace the few usages with calls to the class methods. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299292
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 1 Apr 2017 04:26:20 +0000 (04:26 +0000)]
[DAGCombiner] Fix fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask) to explicitly ensure that only one of the inputs of each shuffle is a zero vector.
This can only happen when we have a mix of zero and undef elements and the two vectors have a different arrangement of zeros/undefs. The shuffle should eventually be constant folded to all zeros.
Fixes PR32484.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299291
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Sat, 1 Apr 2017 01:26:24 +0000 (01:26 +0000)]
Revert "Feature generic option to setup start/stop-after/before"
This reverts commit r299282.
Didn't intend to commit this :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299288
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Sat, 1 Apr 2017 01:26:21 +0000 (01:26 +0000)]
Revert "Localizer fun"
This reverts commit r299283.
Didn't intend to commit this :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299287
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Sat, 1 Apr 2017 01:26:17 +0000 (01:26 +0000)]
Revert "Instrument SDISel C++ patterns"
This reverts commit r299284.
Didn't intend to commit this :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299286
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Sat, 1 Apr 2017 01:26:14 +0000 (01:26 +0000)]
[RegBankSelect] Support REG_SEQUENCE for generic mapping
REG_SEQUENCE falls into the same category as COPY for operands mapping:
- They don't have MCInstrDesc with register constraints
- The input variable could use whatever register classes
- It is possible to have register class already assigned to the operands
In particular, given REG_SEQUENCE are always target specific because of
the subreg indices. Those indices must apply to the register class of
the definition of the REG_SEQUENCE and therefore, the target must set a
register class to that definition. As a result, the generic code can
always use that register class to derive a valid mapping for a
REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299285
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Sat, 1 Apr 2017 01:21:32 +0000 (01:21 +0000)]
Instrument SDISel C++ patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299284
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Sat, 1 Apr 2017 01:21:28 +0000 (01:21 +0000)]
Localizer fun
WIP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299283
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Sat, 1 Apr 2017 01:21:24 +0000 (01:21 +0000)]
Feature generic option to setup start/stop-after/before
This patch refactors the code used in llc such that all the users of the
addPassesToEmitFile API have access to a homogeneous way of handling
start/stop-after/before options right out of the box.
Previously each user would have needed to duplicate this logic and set
up its own options.
NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299282
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Fri, 31 Mar 2017 23:22:19 +0000 (23:22 +0000)]
Fix a test to check assembly output instead of bitcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299279
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Fri, 31 Mar 2017 23:12:27 +0000 (23:12 +0000)]
Reduce the number of times we query the subtarget for the same information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299278
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Fri, 31 Mar 2017 23:12:24 +0000 (23:12 +0000)]
Small cleanup to remove extraneous cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299277
91177308-0d34-0410-b5e6-
96231b3b80d8
Konstantin Zhuravlyov [Fri, 31 Mar 2017 22:36:39 +0000 (22:36 +0000)]
AMDGPU/llvm-readobj: Rename RuntimeMDNoteType -> CodeObjectMetadataNoteType to
match the new metadata. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299275
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 31 Mar 2017 22:23:42 +0000 (22:23 +0000)]
[APInt] Fix bugs in isShiftedMask to match behavior of the similar function in MathExtras.h
This removes a parameter from the routine that was responsible for a lot of the issue. It was a bit count that had to be set to the BitWidth of the APInt and would get passed to getLowBitsSet. This guaranteed the call to getLowBitsSet would create an all ones value. This was then compared to (V | (V-1)). So the only shifted masks we detected had to have the MSB set.
The one in tree user is a transform in InstCombine that never fires due to earlier transforms covering the case better. I've submitted a patch to remove it completely, but for now I've just adapted it to the new interface for isShiftedMask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299273
91177308-0d34-0410-b5e6-
96231b3b80d8
Konstantin Zhuravlyov [Fri, 31 Mar 2017 22:14:54 +0000 (22:14 +0000)]
[AMDGPU] Fix typo in test filename. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299271
91177308-0d34-0410-b5e6-
96231b3b80d8
Derek Schuff [Fri, 31 Mar 2017 22:14:14 +0000 (22:14 +0000)]
Add virtual destructor to WasmYAML::Section or avoid memory leak
Tested locally with -DLLVM_USE_SANITIZER=Address
Differential Revision: https://reviews.llvm.org/D31551
Patch by Sam Clegg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299270
91177308-0d34-0410-b5e6-
96231b3b80d8
Bob Haarman [Fri, 31 Mar 2017 21:56:30 +0000 (21:56 +0000)]
LTO: call getRealLinkageName on IRNames before feeding to getGUID
Summary: GlobalValue has two getGUID methods: an instance method and a static method. The static method takes a string, which is expected to be what GlobalValue::getRealLinkageName() would return. In LTO.cpp, we were not doing this consistently, sometimes passing an IR name instead. This change makes it so that we call getRealLinkageName() first, making the static getGUID return value consistent with the instance method. Without this change, compiling FileCheck with ThinLTO on Windows fails with numerous undefined symbol errors. With the change, it builds successfully.
Reviewers: pcc, rnk
Reviewed By: pcc
Subscribers: tejohnson, mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D31444
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299268
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 31 Mar 2017 21:35:30 +0000 (21:35 +0000)]
[InstCombine] When adding an Instruction and its Users to the worklist at the same time, make sure we put the Users in first. Then put in the instruction.
This way we ensure we immediately revisit the instruction and do any additional optimizations before visiting the users. Otherwise we might visit the users, then the instruction, then users again, then instruction again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299267
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 31 Mar 2017 21:30:50 +0000 (21:30 +0000)]
[DAGCombiner] refactor and/or-of-setcc to get rid of duplicated code; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299266
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Fri, 31 Mar 2017 21:16:22 +0000 (21:16 +0000)]
Fix binary static archive that got mangled by patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299265
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Fri, 31 Mar 2017 21:10:53 +0000 (21:10 +0000)]
[llvm-ar] Extract objects to their basename in the CWD
This is helpful when extracting objects from archives produced by MSVC's
lib.exe, which users absolute paths to describe the archive members.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299264
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 31 Mar 2017 21:08:37 +0000 (21:08 +0000)]
[InstCombine] Add test case demonstrating missed opportunities for removing add/sub when the LSBs of one input are known to be 0 and MSBs of the output aren't consumed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299263
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Fri, 31 Mar 2017 21:03:59 +0000 (21:03 +0000)]
[Hexagon] Remove unused variables
Found by PVS-Studio. Fixes llvm.org/PR31676.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299262
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Fri, 31 Mar 2017 20:36:00 +0000 (20:36 +0000)]
[Hexagon] Fix typo in HexagonEarlyIfCConv.cpp
Found by PVS-Studio. Fixes llvm.org/PR32480.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299258
91177308-0d34-0410-b5e6-
96231b3b80d8
Stephen Canon [Fri, 31 Mar 2017 20:35:02 +0000 (20:35 +0000)]
Fix 80-column violation in previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299257
91177308-0d34-0410-b5e6-
96231b3b80d8
Stephen Canon [Fri, 31 Mar 2017 20:31:33 +0000 (20:31 +0000)]
Fix APFloat mod (committing for simonbyrne)
The previous version was prone to intermediate rounding or overflow.
Differential Revision: https://reviews.llvm.org/D29346
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299256
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 31 Mar 2017 20:28:06 +0000 (20:28 +0000)]
[DAGCombiner] add fold for 'All sign bits set?'
(and (setlt X, 0), (setlt Y, 0)) --> (setlt (and X, Y), 0)
We have 7 similar folds, but this one got away. The fact that the
x86 test with a branch didn't change is probably a separate bug. We
may also be missing this and the related folds in instcombine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299252
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Fri, 31 Mar 2017 20:16:54 +0000 (20:16 +0000)]
[AMDGPU] Remove assumption that vector and scalar types do not alias
Differential Revision: https://reviews.llvm.org/D31547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299250
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 31 Mar 2017 20:01:16 +0000 (20:01 +0000)]
[APInt] Remove shift functions from APIntOps namespace. Replace the few users with the APInt class methods. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299248
91177308-0d34-0410-b5e6-
96231b3b80d8
Joerg Sonnenberger [Fri, 31 Mar 2017 19:58:07 +0000 (19:58 +0000)]
Do not translate rint into nearbyint, but truncate it like nearbyint.
A common way to implement nearbyint is by fiddling with the floating
point environment and calling rint. This is used at least by the BSD
libm and musl. As such, canonicalizing the latter to the former will
create infinite loops for libm and generally pessimize performance, at
least when the generic C versions are used.
This change preserves the rint in the libcall translation and also
handles the domain truncation logic, so that rint with float argument
will be reduced to rintf etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299247
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Fri, 31 Mar 2017 19:53:03 +0000 (19:53 +0000)]
AMDGPU: Remove unnecessary ands when f16 is legal
Add a new node to act as a fancy bitcast from f16 operations to
i32 that implicitly zero the high 16-bits of the result.
Alternatively could try making v2f16 legal and canonicalizing
on build_vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299246
91177308-0d34-0410-b5e6-
96231b3b80d8
Jan Vesely [Fri, 31 Mar 2017 19:26:23 +0000 (19:26 +0000)]
AMDGPU/R600: Fix amdgpu alias analysis pass.
R600 uses higher AS number to access kernel parameters
Fixes: r298846
Differential Revision: https://reviews.llvm.org/D31520
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299245
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 31 Mar 2017 18:51:03 +0000 (18:51 +0000)]
[PowerPC] add tests for setcc+setcc+logic; NFC
These are the same tests added for x86 with r299238,
but PPC doesn't specify all branches as cheap, so we
see different patterns in tests with branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299244
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 31 Mar 2017 18:48:14 +0000 (18:48 +0000)]
[APInt] Rewrite getLoBits in a way that will do one less memory allocation in the multiword case. Rewrite getHiBits to use the class method version of lshr instead of the one in APIntOps. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299243
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 31 Mar 2017 18:30:01 +0000 (18:30 +0000)]
[APInt] Remove unused functions from the APIntOps namespace. The corresponding methods on the APInt object should be used instead. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299242
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 31 Mar 2017 18:18:58 +0000 (18:18 +0000)]
[DAGCombiner] remove redundant code and add comments; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299241
91177308-0d34-0410-b5e6-
96231b3b80d8
Balaram Makam [Fri, 31 Mar 2017 18:16:53 +0000 (18:16 +0000)]
[AArch64] Add new subtarget feature to fold LSL into address mode.
Summary:
This feature enables folding of logical shift operations of up to 3 places into addressing mode on Kryo and Falkor that have a fastpath LSL.
Reviewers: mcrosier, rengolin, t.p.northover
Subscribers: junbuml, gberry, llvm-commits, aemerson
Differential Revision: https://reviews.llvm.org/D31113
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299240
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 31 Mar 2017 17:55:07 +0000 (17:55 +0000)]
[x86] add/consolidate tests for setcc+setcc+and/or; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299238
91177308-0d34-0410-b5e6-
96231b3b80d8
Adam Nemet [Fri, 31 Mar 2017 17:51:12 +0000 (17:51 +0000)]
Improve DebugInfo/strip-loop-metadata.ll test
This wasn't covering for the case where you have multiple latches and hence
the use of the same loop-id which needs to be mapped to the same loop-id.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299237
91177308-0d34-0410-b5e6-
96231b3b80d8
Piotr Padlewski [Fri, 31 Mar 2017 17:39:07 +0000 (17:39 +0000)]
[MSSA] Small test fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299235
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 31 Mar 2017 17:24:29 +0000 (17:24 +0000)]
[AVX-512] Update lowering for gather/scatter prefetch intrinsics to match the immediate encodings the frontend uses based on the _MM_HINT_T0/T1 constant values in clang's headers.
Our _MM_HINT_T0/T1 constant values are 3/2 which matches gcc, but not icc or Intel documentation. Interestingly gcc had this same bug on their implementation of the gather/scatter builtins at one point too.
Fixes PR32411.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299234
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Fri, 31 Mar 2017 17:11:51 +0000 (17:11 +0000)]
Rename variable.
Requested on post commit code review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299232
91177308-0d34-0410-b5e6-
96231b3b80d8
Dehao Chen [Fri, 31 Mar 2017 15:59:52 +0000 (15:59 +0000)]
Fix the InstCombine to reserve the VP metadata and sets correct call count.
Summary: Currently the VP metadata was dropped when InstCombine converts a call to direct call. This patch converts the VP metadata to branch_weights so that its hotness is recorded.
Reviewers: eraman, davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31344
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299228
91177308-0d34-0410-b5e6-
96231b3b80d8
Jan Sjodin [Fri, 31 Mar 2017 15:55:37 +0000 (15:55 +0000)]
Refactor code to create getFallThrough method in MachineBasicBlock.
Differential Revision: https://reviews.llvm.org/D27264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299227
91177308-0d34-0410-b5e6-
96231b3b80d8
Kristof Beyls [Fri, 31 Mar 2017 14:58:52 +0000 (14:58 +0000)]
Remove name space pollution from Signals.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299224
91177308-0d34-0410-b5e6-
96231b3b80d8
Petar Jovanovic [Fri, 31 Mar 2017 14:31:55 +0000 (14:31 +0000)]
[mips][msa] Prevent output operand from commuting for dpadd_[su].df ins
Implementation of TargetInstrInfo::findCommutedOpIndices for MIPS target,
restricting commutativity to second and third operand only for
dpaadd_[su].df instructions therein.
Prior to this change, there were cases where the vector that is to be added
to the dot product of the other two could take a position other than the
first one in the instruction, generating false output in the destination
vector.
Such behavior has been noticed in the two functions generating v2i64 output
values so far. Other ones may exhibit such behavior as well, just not for
the vector operands which are present in the test at the moment.
Tests altered so that the function's first operand is a constant splat so
that it can be loaded with a ldi instruction, since that is the case in
which the erroneous instruction operand placement has occurred. We check
that the register which is present in the ldi instruction is placed as the
first operand in the corresponding dpadd instruction.
Patch by Stefan Maksimovic.
Differential Revision: https://reviews.llvm.org/D30827
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299223
91177308-0d34-0410-b5e6-
96231b3b80d8
Kristof Beyls [Fri, 31 Mar 2017 14:26:44 +0000 (14:26 +0000)]
Remove more name space pollution from .inc files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299222
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 31 Mar 2017 14:21:50 +0000 (14:21 +0000)]
[DAGCombiner] Add ComputeNumSignBits vector demanded elements support to ASHR and INSERT_VECTOR_ELT
Followup to D31311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299221
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Paulsson [Fri, 31 Mar 2017 14:06:59 +0000 (14:06 +0000)]
[SystemZ] Make sure of correct regclasses in insertSelect()
Since LOCR only accepts GR32 virtual registers, its operands must be copied
into this regclass in insertSelect(), when an LOCR is built. Otherwise, the
case where the source operand was GRX32 will produce invalid IR.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299220
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 31 Mar 2017 13:54:09 +0000 (13:54 +0000)]
[DAGCombiner] Add vector demanded elements support to ComputeNumSignBits
Currently ComputeNumSignBits returns the minimum number of sign bits for all elements of vector data, when we may only be interested in one/some of the elements.
This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original ComputeNumSignBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1.
I've only added support for BUILD_VECTOR and EXTRACT_VECTOR_ELT so far, all others will default to demanding all elements but can be updated in due course.
Followup to D25691.
Differential Revision: https://reviews.llvm.org/D31311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299219
91177308-0d34-0410-b5e6-
96231b3b80d8
Kristof Beyls [Fri, 31 Mar 2017 13:48:21 +0000 (13:48 +0000)]
Do not pollute the namespace in a header file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299218
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Fri, 31 Mar 2017 13:41:10 +0000 (13:41 +0000)]
Add a %basename substitution.
This will be used to avoid various call to basename in the asan tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299216
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Paulsson [Fri, 31 Mar 2017 13:22:59 +0000 (13:22 +0000)]
[SystemZ] Skip DAGCombining of vector node for older subtargets.
Even on older subtargets that lack vector support, there may be vector values
with just one element in the input program. These are converted during DAG
legalization to scalar values.
The pre-legalize SystemZ DAGCombiner methods should in this circumstance not
touch these nodes. This patch adds a check for this in
SystemZTargetLowering::combineEXTRACT_VECTOR_ELT().
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299213
91177308-0d34-0410-b5e6-
96231b3b80d8
Kristof Beyls [Fri, 31 Mar 2017 13:06:40 +0000 (13:06 +0000)]
Make naming in Host.h in line with coding standards.
Based on post-commit review comments by Chandler Carruth on
https://reviews.llvm.org/D31236. Thanks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299211
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Fri, 31 Mar 2017 12:46:39 +0000 (12:46 +0000)]
Use the current working directory in the glob expansion
This fixes tests that do things like
mkdir <dir>
cd <dir>
..
<cmd> *.foo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299209
91177308-0d34-0410-b5e6-
96231b3b80d8
Yaron Keren [Fri, 31 Mar 2017 12:08:45 +0000 (12:08 +0000)]
Update comment for r299098 per feedback from James Henderson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299207
91177308-0d34-0410-b5e6-
96231b3b80d8
Max Kazantsev [Fri, 31 Mar 2017 12:05:30 +0000 (12:05 +0000)]
[ScalarEvolution] Re-enable Predicate implication from operations
The patch rL298481 was reverted due to crash on clang-with-lto-ubuntu build.
The reason of the crash was type mismatch between either a or b and RHS in the following situation:
LHS = sext(a +nsw b) > RHS.
This is quite rare, but still possible situation. Normally we need to cast all {a, b, RHS} to their widest type.
But we try to avoid creation of new SCEV that are not constants to avoid initiating recursive analysis that
can take a lot of time and/or cache a bad value for iterations number. To deal with this, in this patch we
reject this case and will not try to analyze it if the type of sum doesn't match with the type of RHS. In this
situation we don't need to create any non-constant SCEVs.
This patch also adds an assertion to the method IsProvedViaContext so that we could fail on it and not
go further into range analysis etc (because in some situations these analyzes succeed even when the passed
arguments have wrong types, what should not normally happen).
The patch also contains a fix for a problem with too narrow scope of the analysis caused by wrong
usage of predicates in recursive invocations.
The regression test on the said failure: test/Analysis/ScalarEvolution/implied-via-addition.ll
Reviewers: reames, apilipenko, anna, sanjoy
Reviewed By: sanjoy
Subscribers: mzolotukhin, mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D31238
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299205
91177308-0d34-0410-b5e6-
96231b3b80d8
Kristof Beyls [Fri, 31 Mar 2017 12:00:24 +0000 (12:00 +0000)]
Do not pollute the namespace in a header file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299203
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Kolton [Fri, 31 Mar 2017 11:42:43 +0000 (11:42 +0000)]
[AMDGPU] SDWA Peephole: improve search for immediates in SDWA patterns
Previously compiler often extracted common immediates into specific register, e.g.:
```
%vreg0 = S_MOV_B32 0xff;
%vreg2 = V_AND_B32_e32 %vreg0, %vreg1
%vreg4 = V_AND_B32_e32 %vreg0, %vreg3
```
Because of this SDWA peephole failed to find SDWA convertible pattern. E.g. in previous example this could be converted into 2 SDWA src operands:
```
SDWA src: %vreg2 src_sel:BYTE_0
SDWA src: %vreg4 src_sel:BYTE_0
```
With this change peephole check if operand is either immediate or register that is copy of immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299202
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 31 Mar 2017 11:24:16 +0000 (11:24 +0000)]
[DAGCombiner] Add vector demanded elements support to computeKnownBitsForTargetNode
Follow up to D25691, this sets up the plumbing necessary to support vector demanded elements support in known bits calculations in target nodes.
Differential Revision: https://reviews.llvm.org/D31249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299201
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 31 Mar 2017 10:59:37 +0000 (10:59 +0000)]
Spelling mistakes in comments. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299197
91177308-0d34-0410-b5e6-
96231b3b80d8