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Fangrui Song [Tue, 18 Jun 2019 14:01:03 +0000 (14:01 +0000)]
[llvm-readobj] Allow --hex-dump/--string-dump to dump multiple sections
1) `-x foo` currently dumps one `foo`. This change makes it dump all `foo`.
2) `-x foo -x foo` currently dumps `foo` twice. This change makes it dump `foo` once.
In addition, if foo has section index 9, `-x foo -x 9` dumps `foo` once.
3) Give a warning instead of an error if `foo` does not exist.
The new behaviors match GNU readelf.
Also, print a new line as a separator between two section dumps.
GNU readelf uses two lines, but one seems good enough.
Reviewed By: grimar, jhenderson
Differential Revision: https://reviews.llvm.org/D63475
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363683
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Matt Arsenault [Tue, 18 Jun 2019 13:19:57 +0000 (13:19 +0000)]
AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics
There may or may not be additional work to handle this correctly on
SI/CI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363678
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Andrea Di Biagio [Tue, 18 Jun 2019 12:59:46 +0000 (12:59 +0000)]
[MCA] Slightly refactor the bottleneck analysis view. NFCI
This patch slightly refactors data structures internally used by the bottleneck
analysis to track data and resource dependencies.
This patch also updates methods used to print out information about dependency
edges when in debug mode.
This is the last of a sequence of commits done in preparation for an upcoming
patch that fixes PR37494. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363677
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Matt Arsenault [Tue, 18 Jun 2019 12:48:36 +0000 (12:48 +0000)]
AMDGPU: Change API for checking for exec modification
Invert the name and return value to better reflect the imprecise
nature.
Force passing in the DefMI, since it's known in the 2 users and could
possibly fail for an arbitrary vreg.
Allow specifying a specific user instruction. Scan through use
instructions, instead of use operands. Add scan thresholds instead of
searching infinitely.
Stop using a set to track seen uses. I didn't understand this usage,
or why it would not check the last use. I don't think the use list has
any particular order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363675
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Fangrui Song [Tue, 18 Jun 2019 12:30:06 +0000 (12:30 +0000)]
MCContext: Delete unused functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363674
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Nico Weber [Tue, 18 Jun 2019 12:29:04 +0000 (12:29 +0000)]
gn build: Merge r363658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363673
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Nico Weber [Tue, 18 Jun 2019 12:26:31 +0000 (12:26 +0000)]
gn build: Merge r363649
This reverts commit "gn build: Merge r363626" because r363626
was reverted in r363649.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363672
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Simon Pilgrim [Tue, 18 Jun 2019 12:24:02 +0000 (12:24 +0000)]
[SelectionDAG] Legalize vaargs that require vector splitting
This adds vector splitting for vaarg instructions during type legalization
Committed on behalf of @luke (Luke Lau)
Differential Revision: https://reviews.llvm.org/D60762
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363671
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Matt Arsenault [Tue, 18 Jun 2019 12:23:46 +0000 (12:23 +0000)]
AMDGPU: Fold readlane from copy of SGPR or imm
These may be inserted to assert uniformity somewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363670
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Matt Arsenault [Tue, 18 Jun 2019 12:23:45 +0000 (12:23 +0000)]
AMDGPU: Remove unnecessary check for virtual register
The copy was found by searching the uses of a virtual register, so
it's already known to be virtual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363669
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Matt Arsenault [Tue, 18 Jun 2019 12:23:44 +0000 (12:23 +0000)]
AMDGPU: Fix iterator crash in AMDGPUPromoteAlloca
The lifetime intrinsic was erased, which was the next iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363668
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Matt Arsenault [Tue, 18 Jun 2019 12:23:42 +0000 (12:23 +0000)]
AMDGPU/GlobalISel: RegBankSelect for amdgcn.div.scale
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363667
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Sjoerd Meijer [Tue, 18 Jun 2019 12:13:11 +0000 (12:13 +0000)]
[ARM] Some Thumb2ITBlock clean ups. NFC
Some more refactoring, like registering the IT Block pass, less cryptic
variable names, and some simplification of loops.
Differential Revision: https://reviews.llvm.org/D63419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363666
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Jonas Paulsson [Tue, 18 Jun 2019 12:10:02 +0000 (12:10 +0000)]
[SystemZ] Fix AHIMuxK pseudo expansion.
Do not emit a copy if the source and destination registers are the same.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363665
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Valery Pykhtin [Tue, 18 Jun 2019 11:43:17 +0000 (11:43 +0000)]
[AMDGPU] Speed up live-in virtual register set computaion in GCNScheduleDAGMILive.
Differential revision: https://reviews.llvm.org/D62401
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363661
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Graham Hunter [Tue, 18 Jun 2019 10:11:56 +0000 (10:11 +0000)]
[SVE][IR] Scalable Vector IR Type with pr42210 fix
Recommit of D32530 with a few small changes:
- Stopped recursively walking through aggregates in
the verifier, so that we don't impose too much
overhead on large modules under LTO (see PR42210).
- Changed tests to match; the errors are slightly
different since they only report the array or
struct that actually contains a scalable vector,
rather than all aggregates which contain one in
a nested member.
- Corrected an older comment
Reviewers: thakis, rengolin, sdesmalen
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D63321
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363658
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Simon Pilgrim [Tue, 18 Jun 2019 10:10:53 +0000 (10:10 +0000)]
[X86] Regenerate promote.ll. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363657
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Diogo N. Sampaio [Tue, 18 Jun 2019 10:04:36 +0000 (10:04 +0000)]
[NFC] Improve triple match of scripts that update tests
Summary:
The prior behavior of the triple matcher would stop
in the first matched triple. It was not possible to
create specific matches for sub-sets of a triple
(e.g aarch64-apple-darwin would never be used after
aarch64 was matched).
This patch:
1) Allows that specialized triples take priority,
considering that the string lenght of the triple
indentifies how specialized a triple is. If two
triples of same lenght match, the one matched first
prevails, preserving the old behavior.
2) Remove 20 duplicated triples of arm, thumb,
aarch64 options with same arguments, matching
the common prefix (aarch64, arm, thumb) of them.
3) Creates three new function matching regexes and
five triple options for arm64-apple-ios,
(arm|thumb)-apple-ios and thumb(v5)?-macho
Reviewers: lebedev.ri, RKSimon, MaskRay, gbedwell
Reviewed By: MaskRay
Subscribers: javed.absar, kristof.beyls, llvm-commits, carwil
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63145
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363656
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Simon Pilgrim [Tue, 18 Jun 2019 09:50:13 +0000 (09:50 +0000)]
[X86] Replace any_extend* vector extensions with zero_extend* equivalents
First step toward addressing the vector-reduce-mul-widen.ll regression in D63281 - we should replace ANY_EXTEND/ANY_EXTEND_VECTOR_INREG in X86ISelDAGToDAG to avoid having to add duplicate patterns when treating any extensions as legal.
In future patches this will also allow us to keep any extension nodes around a lot longer in the DAG, which should mean that we can keep better track of undef elements that otherwise become zeros that we think we have to keep......
Differential Revision: https://reviews.llvm.org/D63326
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363655
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Jeremy Morse [Tue, 18 Jun 2019 08:52:38 +0000 (08:52 +0000)]
[DebugInfo][Docs] Document that prologue/epilogue variable location changes are ignored
This patch documents that LLVM does not describe all changes in variable
locations during the prologue and the epilogue. The debugger doesn't /
shouldn't step through that portion of the function anyway, and describing
every location through such stages would bloat location lists.
Perform some minor cleanup at the same time,
* Fix an enumerated list
* Document that dbg.declare intrinsics have their variable location recorded
in a MachineFunction table, not with DBG_VALUE meta-insts
* Adds frame-indexes to the list of things that can be operands to
DBG_VALUEs.
Differential Revision: https://reviews.llvm.org/D63083
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363654
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Yevgeny Rouban [Tue, 18 Jun 2019 06:50:52 +0000 (06:50 +0000)]
[SimplifyCFG] NFC, prof branch_weighs handling is simplified
Using the new SwitchInstProfUpdateWrapper this patch
simplifies 3 places of prof branch_weights handling.
Differential Revision: https://reviews.llvm.org/D62123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363652
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Fangrui Song [Tue, 18 Jun 2019 06:35:18 +0000 (06:35 +0000)]
[llvm-objdump] Tidy up AMDGCNPrettyPrinter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363650
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Craig Topper [Tue, 18 Jun 2019 04:52:49 +0000 (04:52 +0000)]
[X86] Add i128 ctpop and i32/i64/i128 optsize test cases to popcnt.ll
Test cases for PR41151 and D59909.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363647
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Craig Topper [Tue, 18 Jun 2019 04:23:58 +0000 (04:23 +0000)]
[X86] Move code that shrinks immediates for ((x << C1) op C2) into a helper function. NFCI
Preliminary step for D59909
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363645
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Craig Topper [Tue, 18 Jun 2019 03:23:15 +0000 (03:23 +0000)]
[X86] Remove MOVDI2SSrm/MOV64toSDrm/MOVSS2DImr/MOVSDto64mr CodeGenOnly instructions.
The isel patterns for these use a bitcast and load/store, but
DAG combine should have canonicalized those away.
For the purposes of the memory folding table these opcodes can be
replaced by the MOVSSrm_alt/MOVSDrm_alt and MOVSSmr/MOVSDmr opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363644
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Craig Topper [Tue, 18 Jun 2019 03:23:11 +0000 (03:23 +0000)]
[X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.
Rename the old versions that use FR32/FR64 to MOVSSrm_alt/MOVSDrm_alt.
Use the new versions in patterns that previously used a COPY_TO_REGCLASS
to VR128. These patterns expect the upper bits to be zero. The
current set up appears to work, but I'm not sure we should be
enforcing upper bits being zero through a COPY_TO_REGCLASS.
I wanted to flip the arrangement and use a COPY_TO_REGCLASS to
FR32/FR64 for the patterns that need an f32/f64 result, but that
complicated fastisel and globalisel.
I've been doing some experiments with reducing some isel patterns
and ended up in a situation where I had a
(SUBREG_TO_REG (COPY_TO_RECLASS (VMOVSSrm), VR128)) and our
post-isel peephole was unable to avoid using an instruction for
the SUBREG_TO_REG due to the COPY_TO_REGCLASS. Having a VR128
instruction removes the COPY_TO_REGCLASS that was breaking this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363643
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Tom Stellard [Tue, 18 Jun 2019 02:05:06 +0000 (02:05 +0000)]
GlobalISel: Remove redundant pass initialization
Summary:
All the GlobalISel passes are initialized when the target calls
initializeGlobalISel(), so we don't need to call the initializers
from the pass constructors.
Reviewers: qcolombet, t.p.northover, paquette, dsanders, aemerson, aditya_nandakumar
Reviewed By: aemerson
Subscribers: rovka, kristof.beyls, hiraditya, volkan, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363642
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Alex Brachet [Tue, 18 Jun 2019 00:39:10 +0000 (00:39 +0000)]
[llvm-strip] Error when using stdin twice
Summary: Implements bug [[ https://bugs.llvm.org/show_bug.cgi?id=42204 | 42204 ]]. llvm-strip now warns when the same input file is used more than once, and errors when stdin is used more than once.
Reviewers: jhenderson, rupprecht, espindola, alexshap
Reviewed By: jhenderson, rupprecht
Subscribers: emaste, arichardson, jakehehrlich, MaskRay, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63122
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363638
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Matt Arsenault [Mon, 17 Jun 2019 23:48:43 +0000 (23:48 +0000)]
GlobalISel: Use the original flags when lowering fneg to fsub
This was ignoring the flag on fneg, and using the source instruction's
flags. Also fixes tests missing from r358702.
Note the expansion itself isn't correct without nnan, but that should
be fixed separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363637
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Peter Collingbourne [Mon, 17 Jun 2019 23:39:51 +0000 (23:39 +0000)]
hwasan: Use bits [3..11) of the ring buffer entry address as the base stack tag.
This saves roughly 32 bytes of instructions per function with stack objects
and causes us to preserve enough information that we can recover the original
tags of all stack variables.
Now that stack tags are deterministic, we no longer need to pass
-hwasan-generate-tags-with-calls during check-hwasan. This also means that
the new stack tag generation mechanism is exercised by check-hwasan.
Differential Revision: https://reviews.llvm.org/D63360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363636
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Peter Collingbourne [Mon, 17 Jun 2019 23:39:41 +0000 (23:39 +0000)]
hwasan: Add a tag_offset DWARF attribute to instrumented stack variables.
The goal is to improve hwasan's error reporting for stack use-after-return by
recording enough information to allow the specific variable that was accessed
to be identified based on the pointer's tag. Currently we record the PC and
lower bits of SP for each stack frame we create (which will eventually be
enough to derive the base tag used by the stack frame) but that's not enough
to determine the specific tag for each variable, which is the stack frame's
base tag XOR a value (the "tag offset") that is unique for each variable in
a function.
In IR, the tag offset is most naturally represented as part of a location
expression on the llvm.dbg.declare instruction. However, the presence of the
tag offset in the variable's actual location expression is likely to confuse
debuggers which won't know about tag offsets, and moreover the tag offset
is not required for a debugger to determine the location of the variable on
the stack, so at the DWARF level it is represented as an attribute so that
it will be ignored by debuggers that don't know about it.
Differential Revision: https://reviews.llvm.org/D63119
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363635
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Peter Collingbourne [Mon, 17 Jun 2019 23:39:31 +0000 (23:39 +0000)]
gn build: Merge r363626.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363634
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Amara Emerson [Mon, 17 Jun 2019 23:20:29 +0000 (23:20 +0000)]
[GlobalISel][Localizer] Rewrite localizer to run in 2 phases, inter & intra block.
Inter-block localization is the same as what currently happens, except now it
only runs on the entry block because that's where the problematic constants with
long live ranges come from.
The second phase is a new intra-block localization phase which attempts to
re-sink the already localized instructions further right before one of the
multiple uses.
One additional change is to also localize G_GLOBAL_VALUE as they're constants
too. However, on some targets like arm64 it takes multiple instructions to
materialize the value, so some additional heuristics with a TTI hook have been
introduced attempt to prevent code size regressions when localizing these.
Overall, these changes improve CTMark code size on arm64 by 1.2%.
Full code size results:
Program baseline new diff
------------------------------------------------------------------------------
test-suite...-typeset/consumer-typeset.test
1249984 1217216 -2.6%
test-suite...:: CTMark/ClamAV/clamscan.test
1264928 1232152 -2.6%
test-suite :: CTMark/SPASS/SPASS.test
1394092 1361316 -2.4%
test-suite...Mark/mafft/pairlocalalign.test 731320 714928 -2.2%
test-suite :: CTMark/lencod/lencod.test
1340592 1324200 -1.2%
test-suite :: CTMark/kimwitu++/kc.test
3853512 3820420 -0.9%
test-suite :: CTMark/Bullet/bullet.test
3406036 3389652 -0.5%
test-suite...ark/tramp3d-v4/tramp3d-v4.test
8017000 8016992 -0.0%
test-suite...TMark/7zip/7zip-benchmark.test
2856588 2856588 0.0%
test-suite...:: CTMark/sqlite3/sqlite3.test 765704 765704 0.0%
Geomean difference -1.2%
Differential Revision: https://reviews.llvm.org/D63303
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363632
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Michael Berg [Mon, 17 Jun 2019 23:19:40 +0000 (23:19 +0000)]
Propagate fmf in IRTranslate for fneg
Summary: This case is related to D63405 in that we need to be propagating FMF on negates.
Reviewers: volkan, spatel, arsenm
Reviewed By: arsenm
Subscribers: wdng, javed.absar
Differential Revision: https://reviews.llvm.org/D63458
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363631
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Craig Topper [Mon, 17 Jun 2019 23:08:29 +0000 (23:08 +0000)]
Use VR128X instead of FR32X/FR64X for the register class in VMOVSSZmrk/VMOVSDZmrk.
Removes COPY_TO_REGCLASS from some patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363630
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Craig Topper [Mon, 17 Jun 2019 23:08:09 +0000 (23:08 +0000)]
[X86] Make an assert in LowerSCALAR_TO_VECTOR stricter to make it clear what types are allowed here. NFC
Make it clear that only integer type with i32 or smaller elements shoudl get to this part of the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363629
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Stanislav Mekhanoshin [Mon, 17 Jun 2019 22:37:37 +0000 (22:37 +0000)]
[AMDGPU] Use custom inserter for gfx10 VOP2b
This is part of the approved D63204 pending parent revision.
This small change is in fact a part of the VOP2b legalization which
does not technically belong to wave32 support, so extracted
separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363625
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Stanislav Mekhanoshin [Mon, 17 Jun 2019 21:55:06 +0000 (21:55 +0000)]
[AMDGPU] gfx1010 subvector test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363623
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Volkan Keles [Mon, 17 Jun 2019 21:25:25 +0000 (21:25 +0000)]
[test][AArch64] Relax the check line for G_BRJT in legalizer-info-validation.mir
Replace the specific number with a pattern to relax the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363621
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Philip Reames [Mon, 17 Jun 2019 21:06:17 +0000 (21:06 +0000)]
Teach getSCEVAtScope how to handle loop phis w/invariant operands in loops w/taken backedges
This patch really contains two pieces:
Teach SCEV how to fold a phi in the header of a loop to the value on the backedge when a) the backedge is known to execute at least once, and b) the value is safe to use globally within the scope dominated by the original phi.
Teach IndVarSimplify's rewriteLoopExitValues to allow loop invariant expressions which already exist (and thus don't need new computation inserted) even in loops where we can't optimize away other uses.
Differential Revision: https://reviews.llvm.org/D63224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363619
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Richard Smith [Mon, 17 Jun 2019 21:01:09 +0000 (21:01 +0000)]
Add convenience utility for replacing a range within a container with a
different range, in preparation for use in Clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363617
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Daniel Sanders [Mon, 17 Jun 2019 20:56:31 +0000 (20:56 +0000)]
[globalisel] Fix iterator invalidation in the extload combines
Summary:
Change the way we deal with iterator invalidation in the extload combines as it
was still possible to neglect to visit a use. Even worse, it happened in the
in-tree test cases and the checks weren't good enough to detect it.
We now take a cheap copy of the use list before iterating over it. This
prevents iterator invalidation from occurring and has the nice side effect
of making the existing schedule-for-erase/schedule-for-insert mechanism
moot.
Reviewers: aditya_nandakumar
Reviewed By: aditya_nandakumar
Subscribers: rovka, kristof.beyls, javed.absar, volkan, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61813
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363616
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Stanislav Mekhanoshin [Mon, 17 Jun 2019 20:42:48 +0000 (20:42 +0000)]
[AMDGPU] Propagate function attributes thru bitcasts
AMDGPUPropagateAttributes will not work on function bitcatsts,
so move AMDGPUFixFunctionBitcasts before it.
Differential Revision: https://reviews.llvm.org/D63455
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363614
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Philip Reames [Mon, 17 Jun 2019 20:32:22 +0000 (20:32 +0000)]
Fix a bug w/inbounds invalidation in LFTR (recommit)
Recommit r363289 with a bug fix for crash identified in pr42279. Issue was that a loop exit test does not have to be an icmp, leading to a null dereference crash when new logic was exercised for that case. Test case previously committed in r363601.
Original commit comment follows:
This contains fixes for two cases where we might invalidate inbounds and leave it stale in the IR (a miscompile). Case 1 is when switching to an IV with no dynamically live uses, and case 2 is when doing pre-to-post conversion on the same pointer type IV.
The basic scheme used is to prove that using the given IV (pre or post increment forms) would have to already trigger UB on the path to the test we're modifying. As such, our potential UB triggering use does not change the semantics of the original program.
As was pointed out in the review thread by Nikita, this is defending against a separate issue from the hasConcreteDef case. This is about poison, that's about undef. Unfortunately, the two are different, see Nikita's comment for a fuller explanation, he explains it well.
(Note: I'm going to address Nikita's last style comment in a separate commit just to minimize chance of subtle bugs being introduced due to typos.)
Differential Revision: https://reviews.llvm.org/D62939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363613
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Peter Collingbourne [Mon, 17 Jun 2019 20:03:11 +0000 (20:03 +0000)]
gn build: Merge r363483.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363610
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Peter Collingbourne [Mon, 17 Jun 2019 19:59:16 +0000 (19:59 +0000)]
gn build: Merge r363584.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363609
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Nicolai Haehnle [Mon, 17 Jun 2019 19:28:43 +0000 (19:28 +0000)]
AMDGPU/GFX10: Don't generate s_code_end padding in the asm-printer
Summary:
The purpose of the padding is to guard against stale code being
fetched into the instruction cache by the lowest level prefetching.
We're generating relocatable ELF here, and so the padding should
arguably be added by the linker. This is in fact what Mesa does.
This also fixes multi-part shaders for Mesa.
Change-Id: I6bfede58f20e9f337762ccf39ef9e0e263e69e82
Reviewers: arsenm, rampitec, t-tye
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363602
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Philip Reames [Mon, 17 Jun 2019 19:27:45 +0000 (19:27 +0000)]
Reduced test case for pr42279 in advance of the relevant re-commit + fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363601
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Nicolai Haehnle [Mon, 17 Jun 2019 19:25:57 +0000 (19:25 +0000)]
AMDGPU: Explicitly define a triple for some tests
Summary:
This is related to the changes to the groupstaticsize intrinsic in
D61494 which would otherwise make the related tests in these files
fail or much less useful.
Note that for some reason, SOPK generation is less effective in the
amdhsa OS, which is why I chose PAL. I haven't investigated this
deeper.
Change-Id: I6bb99569338f7a433c28b4c9eb1e3e036b00d166
Reviewers: arsenm
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363600
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Joseph Tremoulet [Mon, 17 Jun 2019 19:11:28 +0000 (19:11 +0000)]
[EarlyCSE] Fix hashing of self-compares
Summary:
Update compare normalization in SimpleValue hashing to break ties (when
the same value is being compared to itself) by switching to the swapped
predicate if it has a lower numerical value. This brings the hashing in
line with isEqual, which already recognizes the self-compares with
swapped predicates as equal.
Fixes PR 42280.
Reviewers: spatel, efriedma, nikic, fhahn, uabelho
Reviewed By: nikic
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63349
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363598
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Alina Sbirlea [Mon, 17 Jun 2019 18:58:40 +0000 (18:58 +0000)]
[MemorySSA] Don't use template when the clone is a simplified instruction.
Summary:
LoopRotate doesn't create a faithful clone of an instruction, it may
simplify it beforehand. Hence the clone of an instruction that has a
MemoryDef associated may not be a definition, but a use or not a memory
alternig instruction.
Don't rely on the template when the clone may be simplified.
Reviewers: george.burgess.iv
Subscribers: jlebar, Prazek, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363597
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Jessica Paquette [Mon, 17 Jun 2019 18:40:06 +0000 (18:40 +0000)]
[GlobalISel][AArch64] Fold G_SUB into G_ICMP when it's safe to do so
Basically porting over the behaviour in AArch64ISelLowering to GISel. See
emitComparison for reference.
When we have something like this:
```
lhs = G_SUB 0, y
...
G_ICMP lhs, rhs
```
We can fold away the G_SUB and produce a cmn instead, given that we produce
the same value in NZCV.
Add a test showing that the transformation works, and also showing that we
don't perform the transformation when it's unsafe.
Also factor out the CSet emission into emitCSetForICMP.
Differential Revision: https://reviews.llvm.org/D63163
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363596
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Craig Topper [Mon, 17 Jun 2019 18:38:07 +0000 (18:38 +0000)]
[X86] Add TB_NO_REVERSE to some memory folding table entries where the register form requires 64-bit mode, but the memory form does not.
We don't know if its safe to unfold if we're in 32-bit mode.
This is simlar to what was done to some load opcodes in r363523.
I think its pretty unlikely we will try to unfold these anyway so
I don't think this is testable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363595
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Valery Pykhtin [Mon, 17 Jun 2019 18:23:39 +0000 (18:23 +0000)]
LiveInterval.h: add LiveRange::findIndexesLiveAt function - return a list of SlotIndexes the LiveRange live at.
Differential revision: https://reviews.llvm.org/D62411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363593
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Simon Pilgrim [Mon, 17 Jun 2019 18:20:04 +0000 (18:20 +0000)]
[X86][SSE] Scalarize under-aligned XMM vector nt-stores (PR42026)
If a XMM non-temporal store has less than natural alignment, scalarize the vector - with SSE4A we can stay on the vector and use MOVNTSD(f64), else we must move to GPRs and use MOVNTI(i32/i64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363592
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Matt Arsenault [Mon, 17 Jun 2019 18:17:25 +0000 (18:17 +0000)]
AMDGPU: Make getreg intrinsic inaccessiblememonly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363591
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Alina Sbirlea [Mon, 17 Jun 2019 18:16:53 +0000 (18:16 +0000)]
[MemorySSA] Add all MemoryPhis before filling their values.
Summary:
Add all MemoryPhis in IDF before filling in their incomign values.
Otherwise, a new Phi can be added that needs to become the incoming
value of another Phi.
Test fails the verification in verifyPrevDefInPhis.
Reviewers: george.burgess.iv
Subscribers: jlebar, Prazek, zzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63353
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363590
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Stanislav Mekhanoshin [Mon, 17 Jun 2019 17:57:50 +0000 (17:57 +0000)]
[AMDGPU] gfx1010 wavefrontsize intrinsic folding
Differential Revision: https://reviews.llvm.org/D63206
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363588
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Matt Arsenault [Mon, 17 Jun 2019 17:52:35 +0000 (17:52 +0000)]
AMDGPU: Fold readlane/readfirstlane calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363587
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Stanislav Mekhanoshin [Mon, 17 Jun 2019 17:47:28 +0000 (17:47 +0000)]
[AMDGPU] Pass to propagate ABI attributes from kernels to the functions
The pass works in two modes:
Mode 1: Just set attributes starting from kernels. This can work at
the very beginning of opt and llc pipeline, but cannot clone functions
because it must be a function pass.
Mode 2: Actually clone functions for new attributes. This can only work
after all function passes in the opt pipeline because it has to be a
module pass.
Differential Revision: https://reviews.llvm.org/D63208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363586
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Nico Weber [Mon, 17 Jun 2019 17:45:12 +0000 (17:45 +0000)]
gn build: Merge r363541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363583
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Simon Pilgrim [Mon, 17 Jun 2019 17:22:38 +0000 (17:22 +0000)]
[X86][AVX] Split under-aligned vector nt-stores.
If a YMM/ZMM non-temporal store has less than natural alignment, split the vector - either they will be satisfactorily aligned or will continue to be split until they are XMMs - at which point the legalizer will scalarize it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363582
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Warren Ristow [Mon, 17 Jun 2019 17:20:08 +0000 (17:20 +0000)]
[LV] Suppress vectorization in some nontemporal cases
When considering a loop containing nontemporal stores or loads for
vectorization, suppress the vectorization if the corresponding
vectorized store or load with the aligment of the original scaler
memory op is not supported with the nontemporal hint on the target.
This adds two new functions:
bool isLegalNTStore(Type *DataType, unsigned Alignment) const;
bool isLegalNTLoad(Type *DataType, unsigned Alignment) const;
to TTI, leaving the target independent default implementation as
returning true, but with overriding implementations for X86 that
check the legality based on available Subtarget features.
This fixes https://llvm.org/PR40759
Differential Revision: https://reviews.llvm.org/D61764
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363581
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Matt Arsenault [Mon, 17 Jun 2019 17:01:35 +0000 (17:01 +0000)]
GlobalISel: Ignore callsite attributes when picking intrinsic type
A target intrinsic may be defined as possibly reading memory, but the
call site may have additional knowledge that it doesn't read
memory. The intrinsic lowering will expect the pessimistic assumption
of the intrinsic definition, so the chain should still be used.
I fixed the same bug in SelectionDAG in r287593.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363580
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Matt Arsenault [Mon, 17 Jun 2019 17:01:32 +0000 (17:01 +0000)]
GlobalISel: Verify intrinsics
I keep using the wrong instruction when manually writing tests. This
really needs to check the number of operands, but I don't see an easy
way to do that right now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363579
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Matt Arsenault [Mon, 17 Jun 2019 17:01:27 +0000 (17:01 +0000)]
AMDGPU/GlobalISel: Account for multiple defs when finding intrinsic ID
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363578
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Stanislav Mekhanoshin [Mon, 17 Jun 2019 16:48:56 +0000 (16:48 +0000)]
[AMDGPU] gfx1010 wave32 metadata
Differential Revision: https://reviews.llvm.org/D63207
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363577
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Tom Stellard [Mon, 17 Jun 2019 16:27:43 +0000 (16:27 +0000)]
AMDGPU/GlobalISel: Implement select for G_ICMP and G_SELECT
Reviewers: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363576
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Francis Visoiu Mistrih [Mon, 17 Jun 2019 16:06:00 +0000 (16:06 +0000)]
[Remarks] Extend -fsave-optimization-record to specify the format
Use -fsave-optimization-record=<format> to specify a different format
than the default, which is YAML.
For now, only YAML is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363573
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Simon Pilgrim [Mon, 17 Jun 2019 15:54:36 +0000 (15:54 +0000)]
[X86] combineLoad - begun making the load split code more generic. NFCI.
This is currently only used for ymm->xmm splitting but we shouldn't hardcode the offsets/alignment.
This is necessary for an upcoming patch to split under-aligned non-temporal vector loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363570
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Whitney Tsang [Mon, 17 Jun 2019 14:38:56 +0000 (14:38 +0000)]
PHINode: introduce setIncomingValueForBlock() function, and use it.
Summary:
There is PHINode::getBasicBlockIndex() and PHINode::setIncomingValue()
but no function to replace incoming value for a specified BasicBlock*
predecessor.
Clearly, there are a lot of places that could use that functionality.
Reviewer: craig.topper, lebedev.ri, Meinersbur, kbarton, fhahn
Reviewed By: Meinersbur, fhahn
Subscribers: fhahn, hiraditya, zzheng, jsji, llvm-commits
Tag: LLVM
Differential Revision: https://reviews.llvm.org/D63338
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363566
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Simon Pilgrim [Mon, 17 Jun 2019 14:38:17 +0000 (14:38 +0000)]
[X86][SSE] Add tests for underaligned nt loads
Test both 'unaligned' (which we should just use regular unaligned loads) and 'subvector aligned' (which we should split)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363565
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Simon Pilgrim [Mon, 17 Jun 2019 14:26:10 +0000 (14:26 +0000)]
[X86][SSE] Prevent misaligned non-temporal vector load/store combines
For loads, pre-SSE41 we can't perform NT loads at all, and after that we can only perform vector aligned loads, so if the alignment is less than for a xmm we'll just end up using the regular unaligned vector loads anyway.
First step towards fixing PR42026 - the next step for stores will be to use SSE4A movntsd where possible and to avoid the stack spill on SSE2 targets.
Differential Revision: https://reviews.llvm.org/D63246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363564
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Matt Arsenault [Mon, 17 Jun 2019 14:13:29 +0000 (14:13 +0000)]
InferAddressSpaces: Fix cloning original addrspacecast
If an addrspacecast needed to be inserted again, this was creating a
clone of the original cast for each user. Just use the original, which
also saves losing the value name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363562
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Matt Arsenault [Mon, 17 Jun 2019 14:13:24 +0000 (14:13 +0000)]
AMDGPU: Ignore subtarget for InferAddressSpaces
Even if the target doesn't have flat instructions, addrspace(0) is
still flat. It just happens to not work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363561
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Matt Arsenault [Mon, 17 Jun 2019 13:52:24 +0000 (13:52 +0000)]
AMDGPU: Mark exp/exp.compr as inaccessiblememonly
Should also be marked writeonly, but I think that would require
splitting the version with done set to a separate intrinsic
Test change is only from renumbering the attribute group numbers,
which for some reason the generated check lines consider.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363560
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Matt Arsenault [Mon, 17 Jun 2019 13:52:19 +0000 (13:52 +0000)]
AMDGPU/GlobalISel: Fix default mapping for non-register operands
Tests will be in future commits when new intrinsics are handled here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363559
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Matt Arsenault [Mon, 17 Jun 2019 13:52:15 +0000 (13:52 +0000)]
AMDGPU: Cleanup custom PseudoSourceValue definitions
Use separate enums for each kind, avoid repeating overloads, and add
missing classof implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363558
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Sam Parker [Mon, 17 Jun 2019 13:39:28 +0000 (13:39 +0000)]
[CodeGen] Check for HardwareLoop Latch ExitBlock
The HardwareLoops pass finds exit blocks with a scevable exit count.
If the target specifies to update the loop counter in a register,
through a phi, we need to ensure that the exit block is a latch so
that we can insert the phi with the correct value for the incoming
edge.
Differential Revision: https://reviews.llvm.org/D63336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363556
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Simon Pilgrim [Mon, 17 Jun 2019 12:35:26 +0000 (12:35 +0000)]
[X86][SSE] Avoid unnecessary stack codegen in NT store codegen tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363552
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Nicolai Haehnle [Mon, 17 Jun 2019 12:24:04 +0000 (12:24 +0000)]
AsmPrinter: add doc-string for EmitLinkage
Change-Id: I376fcbd58f84a2aac6aaf744bc1665c92d312b25
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363550
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Nico Weber [Mon, 17 Jun 2019 12:18:27 +0000 (12:18 +0000)]
gn build: Merge r363530
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363549
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Bjorn Pettersson [Mon, 17 Jun 2019 12:02:24 +0000 (12:02 +0000)]
[LV] Deny irregular types in interleavedAccessCanBeWidened
Summary:
Avoid that loop vectorizer creates loads/stores of vectors
with "irregular" types when interleaving. An example of
an irregular type is x86_fp80 that is 80 bits, but that
may have an allocation size that is 96 bits. So an array
of x86_fp80 is not bitcast compatible with a vector
of the same type.
Not sure if interleavedAccessCanBeWidened is the best
place for this check, but it solves the problem seen
in the added test case. And it is the same kind of check
that already exists in memoryInstructionCanBeWidened.
Reviewers: fhahn, Ayal, craig.topper
Reviewed By: fhahn
Subscribers: hiraditya, rkruppe, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363547
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Sander de Smalen [Mon, 17 Jun 2019 12:01:53 +0000 (12:01 +0000)]
Test forward references in IntrinsicEmitter on Neon LD(2|3|4)
This patch tests the forward-referencing added in D62995 by changing
some existing intrinsics to use forward referencing of overloadable
parameters, rather than backward referencing.
This patch changes the TableGen definition/implementation of
llvm.aarch64.neon.ld2lane and llvm.aarch64.neon.ld2lane intrinsics
(and similar for ld3 and ld4). This change is intended to be
non-functional, since the behaviour of the intrinsics is
expected to be the same.
Reviewers: arsenm, dmgreen, RKSimon, greened, rnk
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D63189
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363546
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Luis Marques [Mon, 17 Jun 2019 10:54:12 +0000 (10:54 +0000)]
[DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting
Some GEPs were not being split, presumably because that split would just be
undone by the DAGCombiner. Not performing those splits can prevent important
optimizations, such as preventing the element indices / member offsets from
being (partially) folded into load/store instruction immediates. This patch:
- Makes the splits also occur in the cases where the base address and the GEP
are in the same BB.
- Ensures that the DAGCombiner doesn't reassociate them back again.
Differential Revision: https://reviews.llvm.org/D60294
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363544
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Fangrui Song [Mon, 17 Jun 2019 10:20:20 +0000 (10:20 +0000)]
Fix clang -Wcovered-switch-default after stack-id change by D60137
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363543
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Simon Pilgrim [Mon, 17 Jun 2019 10:14:52 +0000 (10:14 +0000)]
[SelectionDAG] Fold insert_subvector(undef, extract_subvector(v, c), c) -> v in getNode
This is already done in DAGCombiner::visitINSERT_SUBVECTOR, but this helps a number of shuffles across different vector widths recognise when they come from the same source.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363542
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Sam Parker [Mon, 17 Jun 2019 10:05:18 +0000 (10:05 +0000)]
[SCEV] Use NoWrapFlags when expanding a simple mul
Second functional change following on from rL362687. Pass the
NoWrapFlags from the MulExpr to InsertBinop when we're generating a
shl or mul.
Differential Revision: https://reviews.llvm.org/D61934
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363540
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Fangrui Song [Mon, 17 Jun 2019 09:59:55 +0000 (09:59 +0000)]
[llvm-objdump] Use %08 instead of %016 to print leading addresses for 32-bit binaries
Reviewed By: grimar
Differential Revision: https://reviews.llvm.org/D63398
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363539
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Fangrui Song [Mon, 17 Jun 2019 09:51:07 +0000 (09:51 +0000)]
[lit] Delete empty lines at the end of lit.local.cfg NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363538
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Roman Lebedev [Mon, 17 Jun 2019 09:50:50 +0000 (09:50 +0000)]
[NFC][Codegen] Standalone tests for icmp eq/ne (urem %x, C), 0 -> icmp eq/ne %x, 0 fold (D63390)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363537
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Fangrui Song [Mon, 17 Jun 2019 09:29:50 +0000 (09:29 +0000)]
[ARM] Fix another -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after D63265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363535
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Fangrui Song [Mon, 17 Jun 2019 09:26:50 +0000 (09:26 +0000)]
[ARM] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after D63265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363534
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Sander de Smalen [Mon, 17 Jun 2019 09:13:29 +0000 (09:13 +0000)]
Describe stack-id as an enum
This patch changes MIR stack-id from an integer to an enum,
and adds printing/parsing support for this in MIR files. The default
stack-id '0' is now renamed to 'default'.
This should make MIR tests that have stack objects with different stack-ids
more descriptive. It also clarifies code operating on StackID.
Reviewers: arsenm, thegameg, qcolombet
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D60137
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363533
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Sam Parker [Mon, 17 Jun 2019 09:13:10 +0000 (09:13 +0000)]
[ARM] Remove ARMComputeBlockSize
Forgot to remove file!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363532
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Sam Parker [Mon, 17 Jun 2019 09:05:43 +0000 (09:05 +0000)]
[ARM] Add ARMBasicBlockInfo.cpp
Forgot to add file!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363531
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Sam Parker [Mon, 17 Jun 2019 08:49:09 +0000 (08:49 +0000)]
[ARM] Extract some code from ARMConstantIslandPass
Create the ARMBasicBlockUtils class for tracking and querying basic
blocks sizes so we can use them when generating low-overhead loops.
Differential Revision: https://reviews.llvm.org/D63265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363530
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Hans Wennborg [Mon, 17 Jun 2019 07:47:28 +0000 (07:47 +0000)]
Re-commit r357452 (take 3): "SimplifyCFG SinkCommonCodeFromPredecessors: Also sink function calls without used results (PR41259)"
Third time's the charm.
This was reverted in r363220 due to being suspected of an internal benchmark
regression and a test failure, none of which turned out to be caused by this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363529
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Yevgeny Rouban [Mon, 17 Jun 2019 05:55:12 +0000 (05:55 +0000)]
[SimplifyCFG] Fix prof branch_weights MD while removing unreachable switch cases
SimplifyCFG has a bug that results in inconsistent prof branch_weights metadata
if unreachable switch cases are removed. This patch fixes this bug by making use
of the newly introduced SwitchInstProfUpdateWrapper class (see patch D62122).
A new test is created.
Differential Revision: https://reviews.llvm.org/D62186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363527
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Justin Hibbits [Mon, 17 Jun 2019 03:15:23 +0000 (03:15 +0000)]
PowerPC: Optimize SPE double parameter calling setup
Summary:
SPE passes doubles the same as soft-float, in register pairs as i32
types. This is all handled by the target-independent layer. However,
this is not optimal when splitting or reforming the doubles, as it
pushes to the stack and loads from, on either side.
For instance, to pass a double argument to a function, assuming the
double value is in r5, the sequence currently looks like this:
evstdd 5, X(1)
lwz 3, X(1)
lwz 4, X+4(1)
Likewise, to form a double into r5 from args in r3 and r4:
stw 3, X(1)
stw 4, X+4(1)
evldd 5, X(1)
This optimizes the fence to use SPE instructions. Now, to pass a double
to a function:
mr 4, 5
evmergehi 3, 5, 5
And to form a double into r5 from args in r3 and r4:
evmergelo 5, 3, 4
This is comparable to the way that gcc generates the double splits.
This also fixes a bug with expanding builtins to libcalls, where the
LowerCallTo() code path was generating intermediate illegal type nodes.
Reviewers: nemanjai, hfinkel, joerg
Subscribers: kbarton, jfb, jsji, llvm-commits
Differential Revision: https://reviews.llvm.org/D54583
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363526
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