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Rob Clark [Wed, 30 Nov 2016 18:52:11 +0000 (13:52 -0500)]
freedreno/a5xx: fix discard
Signed-off-by: Rob Clark <robdclark@gmail.com>
Ville Syrjälä [Mon, 28 Nov 2016 16:44:28 +0000 (18:44 +0200)]
anv: Prefer in-tree headers to out-of-tree headers
Set the include paths to consider in-tree headers before out-of-tree
headers.
Avoids the build failing due to stale headers being present in
$prefix. Previosuly 'make -ki install' or something similar was required
to update the out-of-tree headers to allow the build to succeed.
Also avoids having to rebuild the entire thing after every 'make
install'.
Cc: Rob Clark <robdclark@gmail.com>
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Rob Clark [Tue, 8 Nov 2016 15:50:03 +0000 (10:50 -0500)]
freedreno/a5xx: initial support
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 8 Nov 2016 15:49:16 +0000 (10:49 -0500)]
freedreno: update generated headers
Pull in a5xx
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 23 Nov 2016 14:53:44 +0000 (09:53 -0500)]
freedreno: make gmem tile size alignment configurable
a5xx seems to prefer 64 pixel alignment, in at least some cases. Make
this configurable per generation.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 23 Nov 2016 17:21:38 +0000 (12:21 -0500)]
freedreno/ir3: don't offset inloc by 8
On a3xx/a4xx, the SP_VS_VPC_DST_REG.OUTLOCn is offset by 8, so we used
to add this offset into fs->inputs[n].inloc. But a5xx drops this extra
offset-by-8. So instead make inloc zero based and add the offset when
we emit OUTLOCn values (for the gen's that need the offset).
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 23 Nov 2016 17:10:23 +0000 (12:10 -0500)]
freedreno/a3xx: use new shader linkage helper
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 23 Nov 2016 17:08:16 +0000 (12:08 -0500)]
freedreno/a4xx: use new shader linkage helper
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 23 Nov 2016 14:46:15 +0000 (09:46 -0500)]
freedreno/ir3: add new helper for shader linkage
Helps simplify things on a5xx, where pos/psize get added to the vs-out
map. And anyways, simplifies a3xx and a4xx.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Nicolai Hähnle [Fri, 18 Nov 2016 19:51:56 +0000 (20:51 +0100)]
st/mesa: skip lower_output_reads when possible
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 21 Nov 2016 09:36:50 +0000 (10:36 +0100)]
st/glsl_to_tgsi: swizzle PROGRAM_OUTPUTs correctly in src_register translation
This is required for reading directly from fragment shader stencil and depth
outputs.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 18 Nov 2016 19:49:54 +0000 (20:49 +0100)]
gallium: add PIPE_CAP_TGSI_CAN_READ_OUTPUTS
Drivers that support this benefit by saving one lowering pass in the
GLSL-to-TGSI conversion.
radeonsi already supports this because all outputs are stored in temporary
variables before the export (except for TCS outputs, which have always
been readable in TGSI anyway due to their special semantics).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bas Nieuwenhuizen [Tue, 29 Nov 2016 23:41:16 +0000 (00:41 +0100)]
ac/nir: Fix out of bounds array access.
With nir_intrinsic_ssbo_atomic_comp_swap we run out of params.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Kristian H. Kristensen [Tue, 29 Nov 2016 06:40:23 +0000 (22:40 -0800)]
aubinator: Add support for enum types
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 05:00:34 +0000 (21:00 -0800)]
intel/genxml: Fix ksp for INTERFACE_DESCRIPTOR_DATA
This one was split across two dwords as "Kernel Start Pointer" and
"Kernel Start Pointer High", which looks like it works when the driver
only accesses "Kernel Start Pointer". This breaks, of course, with BO
offsets > 4G.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 01:46:05 +0000 (17:46 -0800)]
intel/genxml: Use enum 3D_Logic_Op_Function where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 01:42:46 +0000 (17:42 -0800)]
intel/genxml: Use blend function and factor enums where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 01:20:23 +0000 (17:20 -0800)]
intel/genxml: Use enum 3D_Vertex_Component_Control where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 01:10:57 +0000 (17:10 -0800)]
intel/genxml: Use enum 3D_Stencil_Operation where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:59:46 +0000 (16:59 -0800)]
intel/genxml: Use enum SURFACE_FORMAT where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:44:22 +0000 (16:44 -0800)]
intel/genxml: Use enum 3D_Prim_Topo_Type where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:38:04 +0000 (16:38 -0800)]
intel/genxml: Use 3D_Compare_Function for gen8+ test functions
When the state fields where shuffled around for gen8, the compare
function enums were downgraded to just uints. Change them to enum
3D_Compare_Function.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:34:08 +0000 (16:34 -0800)]
intel/genxml: Emit genxml enums as C enums
The previous commits got rid of any clashes between #defines and enum
values and we can now emit the genxml enums as debugger friendly C
enums.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:32:20 +0000 (16:32 -0800)]
intel/genxml: Remove duplicate COMPAREFUNCTION values
These values were defined both as an enum and as inline values. Remove
the inline values and reference the 3D_Compare_Function enum instead.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:24:13 +0000 (16:24 -0800)]
intel/genxml: Allow referencing enums in type attributes
This lets us reference enums in the type attribute of a field.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 01:15:14 +0000 (17:15 -0800)]
anv: Emit cherryview SF state without including gen9_pack.h
Cleaner this way and we avoid including gen9_pack.h when we compile with
gen8_pack.h. We also avoid the if (cherryview) condition for non-gen8
gens that don't need it.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:16:48 +0000 (16:16 -0800)]
anv: Don't include two different pack headers
The batch chain logic only needs the pre-gen8 size of
MI_BATCH_BUFFER_START, which seems like something we can make a special
case for. The other two gen7 references, MI_BATCH_BUFFER_END and
MI_NOOP, are the same on all gens.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:14:12 +0000 (16:14 -0800)]
intel/genxml: Move enums above structs
We'll need to define them before we can reference them in structs and
instructions. Enums have no dependencies, so move them first in the
file.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 15 Nov 2016 05:10:11 +0000 (21:10 -0800)]
genxml: Add values for Barycentric Interpolation Mode
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Mon, 28 Nov 2016 01:45:34 +0000 (20:45 -0500)]
anv: remove per-sample shading from TODO
This was done some time ago.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Ilia Mirkin [Sun, 27 Nov 2016 22:39:52 +0000 (17:39 -0500)]
anv: clean up VkPhysicalDeviceFeatures list
Remove duplicate .alphaToOne, add missing .shaderResourceMinLod, and
reorder a few entries to match their vulkan.h order. All the sparse
features are still left out entirely.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Michel Dänzer [Thu, 28 Jul 2016 08:54:49 +0000 (17:54 +0900)]
vulkan/wsi/x11: Destroy Present event context when destroying swapchain
Without this, the X server may accumulate stale Present event contexts
if a client creates and destroys multiple swapchains using the same
window.
v2: Based on Chris Wilson's review:
* Use xcb_present_select_input_checked so that protocol errors
generated by old X servers can be handled gracefully
* Use xcb_discard_reply() instead of free(xcb_request_check())
v3: Rebased on top of this code having been refactored out of anv
Reviewed-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Wed, 2 Nov 2016 03:28:12 +0000 (14:28 +1100)]
glsl: use linked_shaders bitmask to iterate stages for subroutine fields
This should be faster than looping over every stage and null checking, but
will also make the code a bit cleaner when we switch to getting more fields
from gl_program rather than from gl_linked_shader as we can just copy the
pointer and not need to worry about null checking then copying.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Wed, 9 Nov 2016 21:33:50 +0000 (08:33 +1100)]
mesa: optimise interleaved sso validation
Now that we have a linked_stages bitfield we can use this
to check if the program is used at a later stage.
This change is also required to be able to use gl_program
rather than gl_shader_program in the CurrentProgram array.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Mon, 31 Oct 2016 10:16:50 +0000 (21:16 +1100)]
mesa/glsl: add bitmask to track stages a program was linked against
This will be used to enable us to store the current gl_program
rather than gl_shader_program in the gl_pipline_object allowing
us to simplify handing of validation.
Also we should not be depending on _LinkedShader for this information
as it may contain shaders from a failed linking attempt rather than
the current program still in use.
We could also use this mask to iterate over the stages during linking
with _mesa_bit_scan() rather then the current method of NULL checking
each stage.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Ilia Mirkin [Thu, 24 Nov 2016 23:02:31 +0000 (18:02 -0500)]
swr: [rasterizer jit] use signed integer representation for logic op
Instead of (incorrectly) biasing the snorm value to make it look like a
unorm, just use signed integer math.
This fixes arb_color_buffer_float-render GL_RGBA8_SNORM
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sun, 20 Nov 2016 22:51:24 +0000 (17:51 -0500)]
swr: add missing rgbx8_srgb variant
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sun, 20 Nov 2016 22:42:26 +0000 (17:42 -0500)]
swr: reorder renderable formats, add grouping comments
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sun, 20 Nov 2016 19:04:51 +0000 (14:04 -0500)]
swr: use util_copy_framebuffer_state helper
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sun, 20 Nov 2016 18:33:04 +0000 (13:33 -0500)]
swr: enable cubemap arrays
Everything is in place for these.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sun, 20 Nov 2016 18:31:43 +0000 (13:31 -0500)]
swr: rearrange caps into limits/supported/unsupported groups
I find this a lot more readable and compact - much easier to scan
through the list and see what's on and what's off.
No functional change intended.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Fri, 18 Nov 2016 23:53:05 +0000 (18:53 -0500)]
swr: only store up to the LOD size
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Wed, 23 Nov 2016 01:50:00 +0000 (19:50 -0600)]
swr: [rasterizer common] add SwrTrace() and macros
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Marek Olšák [Mon, 28 Nov 2016 00:37:42 +0000 (01:37 +0100)]
radeonsi: don't fetch 8 dwords for samplerBuffer and imageBuffer
The compiler doesn't shrink s_load_dwordx8, so we always wasted 4 SGPRs.
Also, the extraction of the descriptor created some really ugly asm code
with lots of VALU bitwise ops and v_readfirstlane.
Totals from *affected* shaders:
SGPRS: 13880 -> 13253 (-4.52 %)
VGPRS: 15200 -> 15088 (-0.74 %)
Code Size: 499864 -> 459816 (-8.01 %) bytes
Max Waves: 1554 -> 1564 (0.64 %)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 27 Nov 2016 17:13:15 +0000 (18:13 +0100)]
radeonsi: disable XNACK to free 2 SGPRs on APUs
My LLVM commit disables it for dGPUs, but not APUs.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 26 Nov 2016 21:52:12 +0000 (22:52 +0100)]
radeonsi: count and report temp arrays in scratch separately
v2: only do this if debug output of shader dumping is enabled
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Marek Olšák [Sat, 26 Nov 2016 21:44:10 +0000 (22:44 +0100)]
radeonsi: don't try to eliminate trivial VS outputs for PS and CS
PS and CS don't have any param exports, so it's a no-op.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 26 Nov 2016 14:52:05 +0000 (15:52 +0100)]
radeonsi: disable RB+ blend optimizations for dual source blending
This fixes dual source blending on Stoney. The fix was copied from Vulkan.
The problem was discovered during internal testing.
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 26 Nov 2016 14:43:39 +0000 (15:43 +0100)]
radeonsi: set CB_BLEND1_CONTROL.ENABLE for dual source blending
copied from Vulkan
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 26 Nov 2016 14:39:06 +0000 (15:39 +0100)]
radeonsi: always set all blend registers
better safe than sorry
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 23 Nov 2016 22:11:45 +0000 (23:11 +0100)]
radeonsi: set the smallest possible CB_TARGET_MASK
better safe than sorry; set_framebuffer_state always makes this dirty
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 23 Nov 2016 22:28:53 +0000 (23:28 +0100)]
radeonsi: don't print bodies of header-only packets
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 23 Nov 2016 21:55:20 +0000 (22:55 +0100)]
radeonsi: print unknown registers with correct formatting
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 23 Nov 2016 20:19:17 +0000 (21:19 +0100)]
ddebug: fix hang detection with deferred flushes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dave Airlie [Thu, 24 Nov 2016 00:35:30 +0000 (00:35 +0000)]
radv: set spi_baryc_cntl.pos_float_location to 0
This fixes:
dEQP-VK.pipeline.multisample_interpolation.offset_interpolate_at_sample_position.*
This should probably be 2 when sample shading is enabled, but I'm
not sure.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 24 Nov 2016 00:18:21 +0000 (00:18 +0000)]
radv: force persample shading when required.
We need to force persample shading when
a) shader uses sample_id
b) shader uses sample_position
c) shader uses sample qualifier.
Also since ps_iter_samples can now change independently of the
rasterizer samples we need to move setting the regs more often.
This fixes:
dEQP-VK.pipeline.multisample_interpolation.centroid_interpolate_at_consistency.*
dEQP-VK.pipeline.multisample_interpolation.centroid_qualifier_inside_primitive.137_191_1.*
dEQP-VK.pipeline.multisample_interpolation.sample_interpolate_at_distinct_values.*
dEQP-VK.pipeline.multisample_interpolation.sample_qualifier_distinct_values.128_128_1.*
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 23 Nov 2016 22:25:50 +0000 (22:25 +0000)]
nir: print var binding in dumps.
This only useful for spir-v shaders, but I keep finding myself
having to add it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Eric Engestrom [Tue, 29 Nov 2016 11:40:55 +0000 (11:40 +0000)]
docs: fix small typo
Fixes:
ba28f2136febca32fe56 ("docs: add note about r-b/other tags when resending")
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Matt Turner [Mon, 28 Nov 2016 21:34:55 +0000 (13:34 -0800)]
i965/sched: Schedule trivial blocks.
In commit
45cd76e342d1e8e schedule_instructions(bblock_t *) began
setting bblock_t::cycle_count, but that function was not called on
trivial blocks.
Remove the code to skip trivial blocks so that cycle_count is set.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Matt Turner [Mon, 28 Nov 2016 21:29:45 +0000 (13:29 -0800)]
i965/sched: Make 'time' a local variable.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Matt Turner [Mon, 28 Nov 2016 21:25:01 +0000 (13:25 -0800)]
i965/cfg: Initialize bblock_t::cycle_count.
schedule_instructions(bblock_t *) isn't called on blocks with a single
instruction, and since it is the only thing that set cycle_count,
cycle_count would be uninitialized.
A non-empty block with bblock_t::cycle_count == 0 is arguably a bug.
That'll be fixed in the next commit.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Matt Turner [Mon, 28 Nov 2016 21:24:04 +0000 (13:24 -0800)]
i965/cfg: Initialize cfg_t::cycle_count.
This reverts commit
b4001af1744a02f472bd1204458662088307981b.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Bas Nieuwenhuizen [Tue, 29 Nov 2016 07:54:05 +0000 (08:54 +0100)]
ac/nir: Fix accessing an unitialized value.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Tue, 29 Nov 2016 07:51:00 +0000 (08:51 +0100)]
radv: Initialize the shader_stats_dump flag.
Meta was using it before it was set. I suspect we typically don't
want to dump meta shaders, so just set it to false in the beginning.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Eric Anholt [Tue, 15 Nov 2016 23:47:49 +0000 (15:47 -0800)]
vc4: Add a note for the future about texture latency calculation.
Debugging a shader-db reported cycle count regression from the tex
coalescing, I eventually figured out that the texture latencies were
totally bogus. Really fixing it will probably involve mirroring
vc4_qir_schedule.c's texture fifo management here.
Eric Anholt [Tue, 15 Nov 2016 22:48:43 +0000 (14:48 -0800)]
vc4: Add support for coalescing ALU ops into tex_[srtb] MOVs.
This isn't as complete as I would like (can't merge interpolation because
of the implicit r5 dependency, doesn't work with control flow), but this
was cheap and easy.
Improves 3DMMES Taiji performance by 1.15353% +/- 0.299896% (n=29, 16)
total instructions in shared programs: 99810 -> 99059 (-0.75%)
instructions in affected programs: 10705 -> 9954 (-7.02%)
Eric Anholt [Tue, 15 Nov 2016 22:35:12 +0000 (14:35 -0800)]
vc4: Restructure VPM write optimization into two passes.
For texturing, there won't be a fixed limit on how many writes there are,
so we need to compute uses up front.
Eric Anholt [Wed, 23 Nov 2016 20:23:55 +0000 (12:23 -0800)]
vc4: Make qir_for_each_inst_inorder() safe against removal.
The dead code elimination wants it to be safe, and I actually got
segfaults due to it being unsafe with the new coalescing pass.
Eric Anholt [Tue, 15 Nov 2016 22:24:25 +0000 (14:24 -0800)]
vc4: Split optimizing VPM writes from VPM reads.
The VPM write logic will be basically the same as the texture coordinate
write logic we need, and it's not really related to the VPM read logic
other than the reuse of the use_count array.
Eric Anholt [Tue, 15 Nov 2016 20:54:26 +0000 (12:54 -0800)]
vc4: Restructure texture insts as ALU ops with tex_[strb] as the dst.
For now we're still just generating MOVs, but this will let us fold into
other ops in the future. No difference on shader-db.
Eric Anholt [Tue, 15 Nov 2016 20:40:36 +0000 (12:40 -0800)]
vc4: Refactor qir_get_op_nsrc(enum qop) to qir_get_nsrc(struct qinst *).
Every caller was dereffing the qinst, and this will let us make the number
of sources vary depending on the destination of the qinst so that we can
have general ALU ops that store to tex_[strb] and get an implicit uniform.
Eric Anholt [Tue, 15 Nov 2016 20:36:20 +0000 (12:36 -0800)]
vc4: Replace the qinst src[] with a fixed-size array.
This may have made a tiny bit of sense when we had one 4-arg inst per
shader, but if we only ever put 2 things in, having a pointer to 2 things
almost every instruction is pointless indirection.
Eric Anholt [Tue, 15 Nov 2016 20:34:35 +0000 (12:34 -0800)]
vc4: Remove qir_inst4().
This was used originally for unorm4x8 packs, but we now represent those as
a series of packed movs.
Ilia Mirkin [Mon, 28 Nov 2016 02:05:36 +0000 (21:05 -0500)]
anv: bump the texture gather offset limits
This matches what NVIDIA and AMD hardware expose, as well as what Intel
hardware supports.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Mon, 28 Nov 2016 02:05:35 +0000 (21:05 -0500)]
i965/gen7: expose larger gather offsets
This matches the capabilities of the hardware.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Mon, 28 Nov 2016 02:05:34 +0000 (21:05 -0500)]
i965: support constant gather offsets larger than 4 bits
Offsets that don't fit into 4 bits need to force gather_po to be
selected. Adjust the logic so that this happens.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Tue, 29 Nov 2016 02:13:02 +0000 (18:13 -0800)]
i965/fs: Refactor handling of constant tg4 offsets
Previously, we had an OFFSET_VALUE source for logical texture instructions
that was intended to mean exactly what it says, "offset". In reality, we
only fully used it for tg4 offsets. We used offset_value.file == IMM to
mean, "you have a constant offset, go look in instr->offset" and didn't
actually use the contents of the register at all in that case except for
in nir_emit_texture where we used it as a temporary before we copy it into
instr->offset.
This commit renames OFFSET_VALUE to TG4_OFFSET and restricts its usage to
indirect tg4 offsets only. The nir_emit_texture code is refactored so that
we explicitly build a header_bits value which is placed in instr->offset
and the constant offset values (both for tg4 and regular texture
operations) are used to construct header_bits and don't go through the
offset source at all. Finally, we stop passing offset_value in to
lower_sampler_logical_send_gen5 because we can't do indirect offsets until
gen7 anyway.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bas Nieuwenhuizen [Mon, 28 Nov 2016 23:18:43 +0000 (00:18 +0100)]
radv: Use different intrinsic for ubo loads.
Not sure about the deprecation path, but this intrinsic
can be lowered to SMEM loads. This results in a significant
Talos performance improvement.
v2: Fix for LLVM attribute changes.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Sat, 26 Nov 2016 23:31:01 +0000 (10:31 +1100)]
mesa: fix active subroutine uniforms properly
07fe2d565b introduced a big hack in order to return
NumSubroutineUniforms when querying ACTIVE_RESOURCES for
<shader>_SUBROUTINE_UNIFORM interfaces. However this is the
wrong fix we are meant to be returning the number of active
resources i.e. the count of subroutine uniforms in the
resource list which is what the code was previously doing,
anything else will cause trouble when trying to retrieve
the resource properties based on the ACTIVE_RESOURCES count.
The real problem is that NumSubroutineUniforms was counting
array elements as separate uniforms but the innermost array
is always considered a single uniform so we fix that count
instead which was counted incorrectly in
7fa0250f9.
Idealy we could probably completely remove
NumSubroutineUniforms and just compute its value when needed
from the resource list but this works for now.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Sat, 26 Nov 2016 06:09:30 +0000 (22:09 -0800)]
anv/cmd_buffer: Remove the 1-D case from the HiZ QPitch calculation
The 1-D special case doesn't actually apply to depth or HiZ. I discovered
this while converting BLORP over to genxml and ISL. The reason is that the
1-D special case only applies to the new Sky Lake 1-D layout which is only
used for LINEAR 1-D images. For tiled 1-D images, such as depth buffers,
the old gen4 2-D layout is used and the QPitch should be in rows.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Mon, 28 Nov 2016 23:44:13 +0000 (15:44 -0800)]
anv/cmd_buffer: Set the correct surface type for depth/stencil
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Ilia Mirkin [Wed, 23 Nov 2016 04:20:11 +0000 (23:20 -0500)]
anv: enable drawIndirectFirstInstance
This was already piped through in the CmdDraw(Indexed)Indirect handling.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Wed, 23 Nov 2016 04:03:12 +0000 (23:03 -0500)]
anv: expose depthBiasClamp, it is already set
The gen7/8_cmd_buffer logic already sets the clamp, and it's piped
through via the dynamic state.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ilia Mirkin [Tue, 29 Nov 2016 00:49:51 +0000 (19:49 -0500)]
anv: bump maxFramebufferLayers to 2048
This matches maxImageArrayLayers, as well as the same setting in the GL
frontend.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ilia Mirkin [Sun, 27 Nov 2016 21:37:17 +0000 (16:37 -0500)]
anv: enable storage image extended formats
These are all regularly available in desktop GL, so the backend fully
supports them.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Sun, 27 Nov 2016 19:41:42 +0000 (14:41 -0500)]
anv: expose imageCubeArray functionality
This appears to be fully supported already.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Dave Airlie [Tue, 29 Nov 2016 01:16:56 +0000 (11:16 +1000)]
radv: set maxFragmentDualSrcAttachments to 1
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 29 Nov 2016 01:16:56 +0000 (11:16 +1000)]
anv: set maxFragmentDualSrcAttachments to 1
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Fri, 18 Nov 2016 20:36:40 +0000 (15:36 -0500)]
swr: [rasterizer memory] only clear up to the LOD size
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Fri, 18 Nov 2016 15:15:30 +0000 (10:15 -0500)]
swr: [rasterizer memory] hook up stencil clears for ClearTile
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Fri, 18 Nov 2016 14:52:41 +0000 (09:52 -0500)]
swr: [rasterizer memory] add support for clearing Z32F_X32 and Z16
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Jason Ekstrand [Thu, 24 Nov 2016 04:24:00 +0000 (20:24 -0800)]
intel/aubinator: Pull useful information from the AUB header
This commit does two things. One is to pull useful and/or interesting
information from the AUB file header and display it as a header above your
decoded batches. Second, it is now capable of pulling the PCI ID from the
AUB file comment left by intel_aubdump. This removes the need to use the
--gen flag all the time.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Thu, 24 Nov 2016 03:14:27 +0000 (19:14 -0800)]
intel/aubinator: Wait to setup decoders until we parse the aub header
This requires that a few more state bits become global.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Thu, 24 Nov 2016 03:38:00 +0000 (19:38 -0800)]
intel/aubinator: Rework handling of the --gen flag
This makes it just store the pci_id instead of a struct pointer
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Thu, 24 Nov 2016 03:26:13 +0000 (19:26 -0800)]
intel/aubinator: Trust the packet size in the header for SUBOPCODE_HEADER
We were reading from the "comment size" dword and incrementing by that
amount. This never caused a problem because that field was always zero.
However, experimenting with actual aub file comments indicates, the
simulator seems to include the comment size in the packet size provided in
the header. We should do the same.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Fri, 18 Nov 2016 19:30:50 +0000 (11:30 -0800)]
intel/aubinator: Add a get_offset helper
The helper automatically handles masking for us so we don't have to worry
about whether or not something is in the bottom bits.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Fri, 18 Nov 2016 19:33:20 +0000 (11:33 -0800)]
intel/aubinator: Fix the kernel start pointer for 3DSTATE_HS
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Fri, 18 Nov 2016 19:14:59 +0000 (11:14 -0800)]
intel/aubinator: Add a get_address helper
This new helper is automatically handles 32 vs. 48-bit GTT issues. It also
handles 48-bit canonical addresses on Broadwell and above.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Fri, 9 Sep 2016 04:12:11 +0000 (21:12 -0700)]
intel/aubinator: Properly handle batch buffer chaining
The original aubinator that Kristian wrote had a bug in the handling of
MI_BATCH_BUFFER_START that propagated into the version in upstream mesa.
In particular, it ignored the "2nd level" bit which tells you whether this
MI_BATCH_BUFFER_START is a subroutine call (2nd level) or a goto. Since
the Vulkan driver uses batch chaining, this can lead to a very confusing
interpretation of the batches. In some cases, depending on how things are
laid out in the virtual GTT, you can even end up with infinite loops in
batch processing.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Ilia Mirkin [Sat, 26 Nov 2016 02:08:16 +0000 (21:08 -0500)]
swr: don't clear all dirty bits when changing so targets
Among other things, blits would clear existing SO targets which would
cause a bunch of updates from u_blitter to be missed.
Fixes fbo-scissor-blit fbo, probably among many others.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>