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Blue Swirl [Sun, 28 Oct 2012 11:04:51 +0000 (11:04 +0000)]
exec: make some functions static
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Blue Swirl [Sun, 28 Oct 2012 11:04:50 +0000 (11:04 +0000)]
target-ppc: make some functions static
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Acked-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Blue Swirl [Sun, 28 Oct 2012 11:04:49 +0000 (11:04 +0000)]
ppc: add missing static
Add missing 'static' qualifiers.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Acked-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Blue Swirl [Sun, 28 Oct 2012 11:04:48 +0000 (11:04 +0000)]
vnc: add missing static
Add missing 'static' qualifiers.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Blue Swirl [Sun, 28 Oct 2012 11:04:47 +0000 (11:04 +0000)]
vl.c: add missing static
Add missing 'static' qualifiers.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Blue Swirl [Sun, 28 Oct 2012 11:04:46 +0000 (11:04 +0000)]
target-sparc: make do_unaligned_access static
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Meador Inge [Fri, 24 Feb 2012 22:18:41 +0000 (16:18 -0600)]
m68k: Return semihosting errno values correctly
Fixing a simple typo, s/errno/err/, that caused
the error status from GDB semihosted system calls
to be returned incorrectly.
Signed-off-by: Meador Inge <meadori@codesourcery.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Peter Crosthwaite [Fri, 19 Oct 2012 09:08:04 +0000 (19:08 +1000)]
cadence_uart: More debug information
Add more helpful debug information to the cadence UART.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Aurelien Jarno [Tue, 9 Oct 2012 19:53:21 +0000 (21:53 +0200)]
target-mips: don't flush extra TLB on permissions upgrade
If the guest uses a TLBWI instruction for upgrading permissions, we
don't need to flush the extra TLBs. This improve boot time performance
by about 10%.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Tue, 9 Oct 2012 19:53:21 +0000 (21:53 +0200)]
target-mips: fix TLBR wrt SEGMask
Like r4k_map_address(), r4k_helper_tlbp() should use SEGMask to mask the
address.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Tue, 9 Oct 2012 19:53:21 +0000 (21:53 +0200)]
target-mips: use deposit instead of hardcoded version
Use the deposit op instead of and hardcoded bit field insertion. It
allows the host to emit the corresponding instruction if available.
At the same time remove the (lsb > msb) test. The MIPS64R2 instruction
set manual says "Because of the instruction format, lsb can never be
greater than msb, so there is no UNPREDICATABLE case for this
instruction."
(Bug reported as LP:
1071149.)
Cc: Никита Канунников <n.kanunnikov@sbtcom.ru>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Tue, 9 Oct 2012 19:53:21 +0000 (21:53 +0200)]
target-mips: optimize ddiv/ddivu/div/divu with movcond
The result of a division by 0, or a division of INT_MIN by -1 in the
signed case, is unpredictable. Just replace 0 by 1 in that case so that
it doesn't trigger a floating point exception on the host.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Tue, 9 Oct 2012 19:53:21 +0000 (21:53 +0200)]
target-mips: implement movn/movz using movcond
Avoid the branches in movn/movz implementation and replace them with
movcond. Also update a wrong command.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Tue, 9 Oct 2012 19:53:21 +0000 (21:53 +0200)]
target-mips: don't use local temps for store conditional
Store conditional operations only need local temps in user mode. Fix
the code to use temp local only in user mode, this spares two memory
stores in system mode.
At the same time remove a wrong a wrong copied & pasted comment,
store operations don't have a register destination.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Tue, 9 Oct 2012 19:53:21 +0000 (21:53 +0200)]
target-mips: implement unaligned loads using TCG
Load/store from helpers should be avoided as they are quite
inefficient. Rewrite unaligned loads instructions using TCG and
aligned loads. The number of actual loads operations to implement
an unaligned load instruction is reduced from up to 8 to 1.
Note: As we can't rely on shift by 32 or 64 undefined behaviour,
the code loads already shift by one constants.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Tue, 9 Oct 2012 19:53:20 +0000 (21:53 +0200)]
target-mips: simplify load/store microMIPS helpers
load/store microMIPS helpers are reinventing the wheel. Call do_lw,
do_ll, do_sw and do_sl instead of using a macro calling the cpu_*
load/store functions.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Tue, 9 Oct 2012 19:53:20 +0000 (21:53 +0200)]
target-mips: optimize load operations
Only allocate t1 when needed.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Tue, 9 Oct 2012 19:53:20 +0000 (21:53 +0200)]
target-mips: cleanup load/store operations
Load/store operations use macros for historical reasons. Now that there
is no point in keeping them, replace them by direct calls to qemu_ld/st.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Sun, 28 Oct 2012 18:34:03 +0000 (19:34 +0100)]
target-mips: restore CPU state after an FPU exception
Rework *raise_exception*() functions so that they can be called from
other helpers, passing the return address as an argument.
Use do_raise_exception() function in update_fcr31() to correctly restore
the CPU state after an FPU exception.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Tue, 23 Oct 2012 08:12:00 +0000 (10:12 +0200)]
target-mips: use softfloat constants when possible
softfloat already has a few constants defined, use them instead of
redefining them in target-mips.
Rename FLOAT_SNAN32 and FLOAT_SNAN64 to FP_TO_INT32_OVERFLOW and
FP_TO_INT64_OVERFLOW as even if they have the same value, they are
technically different (and defined differently in the MIPS ISA).
Remove the unused constants.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Tue, 23 Oct 2012 07:53:50 +0000 (09:53 +0200)]
target-mips: cleanup float to int conversion helpers
Instead of accessing the flags from the floating point control
register after updating it, read the softfloat flags.
This is just code cleanup and should not change the behaviour.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Tue, 9 Oct 2012 19:53:20 +0000 (21:53 +0200)]
target-mips: fix FPU exceptions
For each FPU instruction that can trigger an FPU exception, to call
call update_fcr31() after.
Remove the manual NaN assignment in case of float to float operation, as
softfloat is already taking care of that. However for float to int
operation, the value has to be changed to the MIPS one. In the cvtpw_ps
case, the two registers have to be handled separately to guarantee
a correct final value in both registers.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Sun, 28 Oct 2012 17:08:27 +0000 (18:08 +0100)]
target-mips: keep softfloat exception set to 0 between instructions
Instead of clearing the softfloat exception flags before each floating
point instruction, reset them to 0 in update_fcr31() when an exception
is detected.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Tue, 9 Oct 2012 19:53:20 +0000 (21:53 +0200)]
target-mips: use the softfloat floatXX_muladd functions
Use the new softfloat floatXX_muladd() functions to implement the madd,
msub, nmadd and nmsub instructions. At the same time replace the name of
the helpers by the name of the instruction, as the only reason for the
previous names was to keep the macros simple.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Tue, 9 Oct 2012 19:53:20 +0000 (21:53 +0200)]
softfloat: implement fused multiply-add NaN propagation for MIPS
Add a pickNaNMulAdd function for MIPS, implementing NaN propagation
rules for MIPS fused multiply-add instructions.
Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Sun, 28 Oct 2012 14:55:47 +0000 (15:55 +0100)]
target-mips: do not save CPU state when using retranslation
When the CPU state after a possible retranslation is going to be handled
through code retranslation, we don't need to save the CPU state before.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Sun, 28 Oct 2012 14:42:55 +0000 (15:42 +0100)]
target-mips: correctly restore btarget upon exception
When the CPU state is restored through retranslation after an exception,
btarget should also be restored.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Aurelien Jarno [Tue, 30 Oct 2012 23:50:15 +0000 (00:50 +0100)]
tcg: don't remove op if output needs to be synced to memory
Commit
9c43b68de628a1e2cba556adfb71c17028eb802e do not correctly check
for dead outputs when they need to be synced to memory in case of
half-dead operations.
Fix that by applying the same pattern than for the default case.
Tested-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Richard Henderson [Tue, 30 Oct 2012 23:30:55 +0000 (10:30 +1100)]
target-alpha: Use TCG_CALL_NO_WG
Mark helper functions that raise exceptions, but otherwise do not
change TCG register state, with TCG_CALL_NO_WG.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Jan Kiszka [Fri, 12 Oct 2012 07:52:49 +0000 (09:52 +0200)]
chardev: Use timer instead of bottom-half to postpone open event
As the block layer may decide to flush bottom-halfs while the machine is
still initializing (e.g. to read geometry data from the disk), our
postponed open event may be processed before the last frontend
registered with a muxed chardev.
Until the semantics of BHs have been clarified, use an expired timer to
achieve the same effect (suggested by Paolo Bonzini). This requires to
perform the alarm timer initialization earlier as otherwise timer
subsystem can be used before being ready.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Aurelien Jarno [Wed, 31 Oct 2012 21:14:46 +0000 (22:14 +0100)]
target-mips: remove #if defined(TARGET_MIPS64) in opcode enums
All switch() decoding instruction have a default entry, so it is possible
to have unused enum entries. Remove conditional definitions of MIPS64
opcode enums, as it only makes the code less readable.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Jia Liu [Wed, 24 Oct 2012 14:17:14 +0000 (22:17 +0800)]
target-mips: Change TODO file
Change DSP r1 & DSP r2 into microMIPS DSP encodings in TODO file.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Jia Liu [Wed, 24 Oct 2012 14:17:13 +0000 (22:17 +0800)]
target-mips: Add ASE DSP testcases
Add MIPS ASE DSP testcases.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Jia Liu [Wed, 24 Oct 2012 14:17:12 +0000 (22:17 +0800)]
target-mips: Add ASE DSP processors
Add 74kf and mips64dspr2-generic-cpu model for test.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Jia Liu [Wed, 24 Oct 2012 14:17:11 +0000 (22:17 +0800)]
target-mips: Add ASE DSP accumulator instructions
Add MIPS ASE DSP Accumulator and DSPControl Access instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Jia Liu [Wed, 24 Oct 2012 14:17:10 +0000 (22:17 +0800)]
target-mips: Add ASE DSP compare-pick instructions
Add MIPS ASE DSP Compare-Pick instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Jia Liu [Wed, 24 Oct 2012 14:17:09 +0000 (22:17 +0800)]
target-mips: Add ASE DSP bit/manipulation instructions
Add MIPS ASE DSP Bit/Manipulation instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Jia Liu [Wed, 24 Oct 2012 14:17:08 +0000 (22:17 +0800)]
target-mips: Add ASE DSP multiply instructions
Add MIPS ASE DSP Multiply instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Jia Liu [Wed, 24 Oct 2012 14:17:07 +0000 (22:17 +0800)]
target-mips: Add ASE DSP GPR-based shift instructions
Add MIPS ASE DSP GPR-Based Shift instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Jia Liu [Wed, 24 Oct 2012 14:17:06 +0000 (22:17 +0800)]
target-mips: Add ASE DSP arithmetic instructions
Add MIPS ASE DSP Arithmetic instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Jia Liu [Wed, 24 Oct 2012 14:17:05 +0000 (22:17 +0800)]
target-mips: Add ASE DSP load instructions
Add MIPS ASE DSP Load instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Jia Liu [Wed, 24 Oct 2012 14:17:04 +0000 (22:17 +0800)]
target-mips: Add ASE DSP branch instructions
Add MIPS ASE DSP Branch instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Jia Liu [Wed, 24 Oct 2012 14:17:03 +0000 (22:17 +0800)]
Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Jia Liu [Wed, 24 Oct 2012 14:17:02 +0000 (22:17 +0800)]
target-mips: Add ASE DSP resources access check
Add MIPS ASE DSP resources access check.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Jia Liu [Wed, 24 Oct 2012 14:17:01 +0000 (22:17 +0800)]
target-mips: Add ASE DSP internal functions
Add internal functions using by MIPS ASE DSP instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Michael S. Tsirkin [Tue, 30 Oct 2012 14:04:50 +0000 (16:04 +0200)]
tap-win32: stubs to fix win32 build
Add missing stubs to win32 to fix link failure.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reported-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Catalin Patulea [Mon, 29 Oct 2012 18:01:07 +0000 (14:01 -0400)]
tests/tcg: fix unused result warnings
With i386-linux-user target on x86_64 host, this does not introduce any new test
failures.
Signed-off-by: Catalin Patulea <catalinp@google.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Peter Maydell [Sat, 27 Oct 2012 21:19:07 +0000 (22:19 +0100)]
configure: use -Wwombat to test whether gcc recognizes -Wno-wombat
gcc will silently accept unrecognized -Wno-wombat warning suppression
options (it only mentions them if it has to print a compiler warning
for some other reason). Since we already run a check for whether gcc
recognizes the warning options we use, we can easily make this use
the positive sense of the option when checking for support for the
suppression option. This doesn't have any effect except that it avoids
gcc emitting extra messages about unrecognized command line options
when it is printing other warning messages.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Richard Henderson [Mon, 29 Oct 2012 04:50:20 +0000 (15:50 +1100)]
target-sparc: Revert setting cpu_dst to gen_dest_gpr
There is some read-after-write error within the OP=2 insns which
prevents setting cpu_dst to the real output register. Until this
is found and fixed, always write to a temporary first.
Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Blue Swirl [Tue, 30 Oct 2012 18:35:18 +0000 (18:35 +0000)]
Merge branch 'qspi.2' of git://developer.petalogix.com/public/qemu
* 'qspi.2' of git://developer.petalogix.com/public/qemu:
xilinx_zynq: added QSPI controller
xilinx_spips: Generalised to model QSPI
m25p80: Support for Quad SPI
Aurelien Jarno [Mon, 29 Oct 2012 23:35:43 +0000 (00:35 +0100)]
Merge branch 's390-for-upstream' of git://repo.or.cz/qemu/agraf
* 's390-for-upstream' of git://repo.or.cz/qemu/agraf:
s390: sclp ascii console support
s390: sclp signal quiesce support
s390: sclp event support
s390: sclp base support
s390: use sync regs for register transfer
s390/kvm_stat: correct sys_perf_event_open syscall number
s390x: fix -initrd in virtio machine
Aurelien Jarno [Fri, 19 Oct 2012 21:48:13 +0000 (23:48 +0200)]
tcg/mips: use MUL instead of MULT on MIPS32 and above
MIPS32 and later instruction sets have a multiplication instruction
directly operating on GPRs. It only produces a 32-bit result but
it is exactly what is needed by QEMU.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Avi Kivity [Mon, 29 Oct 2012 16:22:36 +0000 (18:22 +0200)]
memory: fix rendering of a region obscured by another
The memory core drops regions that are hidden by another region (for example,
during BAR sizing), but it doesn't do so correctly if the lower address of the
existing range is below the lower address of the new range.
Example (qemu-system-mips -M malta -kernel vmlinux-2.6.32-5-4kc-malta
-append "console=ttyS0" -nographic -vga cirrus):
Existing range:
10000000-
107fffff
New range:
100a0000-
100bffff
Correct behaviour: drop new range
Incorrect behaviour: add new range
Fix by taking this case into account (previously we only considered
equal lower boundaries).
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Anthony Liguori [Mon, 29 Oct 2012 19:31:47 +0000 (14:31 -0500)]
Merge remote-tracking branch 'mst/tags/for_anthony' into staging
virtio,pci infrastructure
This includes infrastructure patches that don't do much by themselves
but should help vfio and q35 make progress.
Also included is rework of virtio-net to use iovec APIs
for vector access - helpful to make it more secure
and in preparation for a new feature that will allow
arbitrary s/g layout for guests.
Also included is a pci bridge bugfix by Avi.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* mst/tags/for_anthony: (25 commits)
pci: avoid destroying bridge address space windows in a transaction
virtio-net: enable mrg buf header in tap on linux
virtio-net: test peer header support at init time
virtio-net: minor code simplification
virtio-net: simplify rx code
virtio-net: switch tx to safe iov functions
virtio-net: first s/g is always at start of buf
virtio-net: refactor receive_hdr
virtio-net: use safe iov operations for rx
virtio-net: avoid sg copy
iov: add iov_cpy
virtio-net: track host/guest header length
pcie: Convert PCIExpressHost to use the QOM.
pcie: pass pcie window size to pcie_host_mmcfg_update()
pci: Add class 0xc05 as 'SMBus'
pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle
pci_ids: add intel
82801BA pci-to-pci bridge id
pci: pci capability must be in PCI space
pci: make each capability DWORD aligned
qemu: enable PV EOI for qemu 1.3
...
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Heinz Graalfs [Mon, 29 Oct 2012 02:13:25 +0000 (02:13 +0000)]
s390: sclp ascii console support
This code adds console support by implementing SCLP's ASCII Console
Data event. This is the same console as LPARs ASCII console or z/VMs
sysascii.
The console can be specified manually with something like
-chardev stdio,id=charconsole0 -device sclpconsole,chardev=charconsole0,id=console0
Newer kernels will autodetect that console and prefer that over virtio
console.
When data is received from the character layer it creates a service
interrupt to trigger a Read Event Data command from the guest that will
pick up the received character byte-stream.
When characters are echo'ed by the linux guest a Write Event Data occurs
which is forwarded by the Event Facility to the console that supports
a corresponding mask value.
Console resizing is not supported.
The character layer byte-stream is buffered using a fixed size iov
buffer.
Signed-off-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com>
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Heinz Graalfs [Mon, 29 Oct 2012 02:13:24 +0000 (02:13 +0000)]
s390: sclp signal quiesce support
This implements the sclp signal quiesce event via the SCLP Event
Facility.
This allows to gracefully shutdown a guest by using system_powerdown
notifiers. It creates a service interrupt that will trigger a
Read Event Data command from the guest. This code will then add an
event that is interpreted by linux guests as ctrl-alt-del.
Signed-off-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com>
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Heinz Graalfs [Mon, 29 Oct 2012 02:13:23 +0000 (02:13 +0000)]
s390: sclp event support
Several SCLP features are considered to be events. Those events don't
provide SCLP commands on their own, instead they are all based on
Read Event Data, Write Event Data, Write Event Mask and the service
interrupt. Follow-on patches will provide SCLP's Signal Quiesce (via
system_powerdown) and the ASCII console.
Further down the road the sclp line mode console and configuration
change events (e.g. cpu hotplug) can be implemented.
Signed-off-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com>
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Heinz Graalfs [Mon, 29 Oct 2012 02:13:22 +0000 (02:13 +0000)]
s390: sclp base support
This adds a more generic infrastructure for handling Service-Call
requests on s390. Currently we only support a small subset of Read
SCP Info directly in target-s390x. This patch provides the base
infrastructure for supporting more commands and moves Read SCP
Info.
In the future we could add additional commands for hotplug, call
home and event handling.
Signed-off-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com>
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Christian Borntraeger [Mon, 29 Oct 2012 02:13:21 +0000 (02:13 +0000)]
s390: use sync regs for register transfer
Newer kernels provide the guest registers in kvm_run. Lets use
those if available (i.e. the capability is set). This avoids
ioctls on cpu_synchronize_state making intercepts faster.
In addition, we have now the prefix register, the access registers
the control registers up to date. This helps in certain cases,
e.g. for resolving kernel module addresses with gdb on a guest.
On return, we update the registers according to the level statement,
i.e. we put all registers for KVM_PUT_FULL_STATE and _RESET_STATE.
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Heinz Graalfs [Mon, 29 Oct 2012 02:13:20 +0000 (02:13 +0000)]
s390/kvm_stat: correct sys_perf_event_open syscall number
Correct sys_perf_event_open syscall number for s390 architecture
- the hardcoded syscall number 298 is for x86 but should
be different for other architectures.
In case we figure out via /proc/cpuinfo that we are running
on s390 the appropriate syscall number is used from map
syscall_numbers; other architectures can extend this.
Signed-off-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com>
Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 19 Sep 2012 15:24:46 +0000 (17:24 +0200)]
s390x: fix -initrd in virtio machine
When using -initrd in the virtio machine, we need to indicate the initrd
start and size inside the kernel image. These parameters need to be stored
in native endianness.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Richard Henderson <rth@twiddle.net>
Acked-by: Christian Borntraeger <borntraeger@de.ibm.com>
Avi Kivity [Thu, 25 Oct 2012 10:37:57 +0000 (12:37 +0200)]
pci: avoid destroying bridge address space windows in a transaction
Calling memory_region_destroy() in a transaction is illegal (and aborts),
as until the transaction is committed, the region remains live.
Fix by moving destruction until after the transaction commits. This requires
having an extra set of regions, so the new and old regions can coexist.
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Michael S. Tsirkin [Mon, 24 Sep 2012 19:05:03 +0000 (21:05 +0200)]
virtio-net: enable mrg buf header in tap on linux
Modern linux supports arbitrary header size,
which makes it possible to pass mrg buf header
to tap directly without iovec mangling.
Use this capability when it is there.
This removes the need to deal with it in
vhost-net as we do now.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Michael S. Tsirkin [Mon, 24 Sep 2012 15:04:21 +0000 (17:04 +0200)]
virtio-net: test peer header support at init time
There's no reason to query header support at random
times: at load or feature query.
Driver also might not query functions.
Cleaner to do it at device init.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Michael S. Tsirkin [Mon, 24 Sep 2012 14:27:27 +0000 (16:27 +0200)]
virtio-net: minor code simplification
During packet filtering, we can now use host hdr len
to offset incoming buffer unconditionally.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Michael S. Tsirkin [Mon, 24 Sep 2012 12:54:44 +0000 (14:54 +0200)]
virtio-net: simplify rx code
Remove code duplication using guest header length that we track.
Drop specific layout requirement for rx buffers: things work
using generic iovec functions in any case.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Michael S. Tsirkin [Mon, 24 Sep 2012 12:52:28 +0000 (14:52 +0200)]
virtio-net: switch tx to safe iov functions
Avoid mangling iovec manually: use safe iov_*
functions.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Michael S. Tsirkin [Mon, 24 Sep 2012 11:26:55 +0000 (13:26 +0200)]
virtio-net: first s/g is always at start of buf
We know offset is 0, assert that.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Michael S. Tsirkin [Mon, 24 Sep 2012 11:24:17 +0000 (13:24 +0200)]
virtio-net: refactor receive_hdr
Now that we know host hdr length, we don't need to
duplicate the logic in receive_hdr: caller can
figure out the offset itself.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Michael S. Tsirkin [Mon, 24 Sep 2012 11:17:13 +0000 (13:17 +0200)]
virtio-net: use safe iov operations for rx
Avoid magling iov manually: use safe iov operations
for processing packets incoming to guest.
This also removes the requirement for virtio header to
fit the first s/g entry exactly.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Michael S. Tsirkin [Mon, 24 Sep 2012 11:14:16 +0000 (13:14 +0200)]
virtio-net: avoid sg copy
Avoid tweaking iovec during receive. This removes
the need to copy the vector.
Note: we currently have an evil cast in work_around_broken_dhclient
and unfortunately this patch does not fix it - just
pushes the evil cast to another place.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Michael S. Tsirkin [Mon, 24 Sep 2012 11:02:52 +0000 (13:02 +0200)]
iov: add iov_cpy
Add API to copy part of iovec safely.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Michael S. Tsirkin [Mon, 24 Sep 2012 10:12:25 +0000 (12:12 +0200)]
virtio-net: track host/guest header length
Tracking these in device state instead of
re-calculating on each packet. No functional
changes.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Avi Kivity [Thu, 25 Oct 2012 10:37:57 +0000 (12:37 +0200)]
pci: avoid destroying bridge address space windows in a transaction
Calling memory_region_destroy() in a transaction is illegal (and aborts),
as until the transaction is committed, the region remains live.
Fix by moving destruction until after the transaction commits. This requires
having an extra set of regions, so the new and old regions can coexist.
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Jason Baron [Fri, 19 Oct 2012 20:43:33 +0000 (16:43 -0400)]
pcie: Convert PCIExpressHost to use the QOM.
Let's use PCIExpressHost with QOM.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Acked-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Jason Baron <jbaron@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jason Baron [Fri, 19 Oct 2012 20:43:32 +0000 (16:43 -0400)]
pcie: pass pcie window size to pcie_host_mmcfg_update()
This allows q35 to pass/set the size of the pcie window in its update routine.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jan Kiszka [Fri, 19 Oct 2012 20:43:31 +0000 (16:43 -0400)]
pci: Add class 0xc05 as 'SMBus'
[jbaron@redhat.com: add PCI_CLASS_SERIAL_SMBUS definition]
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Isaku Yamahata [Fri, 19 Oct 2012 20:43:28 +0000 (16:43 -0400)]
pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle
Introduce pci_swizzle_map_irq_fn() for interrupt pin swizzle which is
standardized. PCI bridge swizzle is common logic, by introducing
this function duplicated swizzle logic will be avoided later.
[jbaron@redhat.com: drop opaque argument]
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Isaku Yamahata [Fri, 19 Oct 2012 20:43:31 +0000 (16:43 -0400)]
pci_ids: add intel
82801BA pci-to-pci bridge id
Adds pci id constants which will be used by q35.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Isaku Yamahata [Fri, 19 Oct 2012 20:43:28 +0000 (16:43 -0400)]
pci: pci capability must be in PCI space
pci capability must be in PCI space.
It can't lay in PCIe extended config space.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Michael S. Tsirkin [Mon, 22 Oct 2012 10:35:00 +0000 (12:35 +0200)]
pci: make each capability DWORD aligned
PCI spec (see e.g. 6.7 Capabilities List in spec rev 3.0)
requires that each capability is DWORD aligned.
Ensure this when allocating space by rounding size up to 4.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Michael S. Tsirkin [Wed, 17 Oct 2012 22:15:48 +0000 (00:15 +0200)]
qemu: enable PV EOI for qemu 1.3
Enable KVM PV EOI by default. You can still disable it with
-kvm_pv_eoi cpu flag. To avoid breaking cross-version migration,
enable only for qemu 1.3 (or in the future, newer) machine type.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Alex Williamson [Wed, 17 Oct 2012 22:13:12 +0000 (16:13 -0600)]
pci: Return PCI_INTX_DISABLED when no bus INTx routing support
Rather than assert, simply return PCI_INTX_DISABLED when we don't
have a pci_route_irq_fn. PIIX already returns DISABLED for an
invalid pin, so users already deal with this state. Users of this
interface should only be acting on an ENABLED or INVERTED return
value (though we really have no support for INVERTED). Also
complain loudly when we hit this so we don't forget it's missing.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Jan Kiszka <jan.kiszka@siemens.com>
Alex Williamson [Tue, 2 Oct 2012 19:22:14 +0000 (13:22 -0600)]
pci-assign: Use msi_get_message()
pci-assign only uses a subset of the flexibility msi_get_message()
provides, but it's still worthwhile to use it.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Alex Williamson [Tue, 2 Oct 2012 19:22:07 +0000 (13:22 -0600)]
msi: Add msi_get_message()
vfio-pci and pci-assign both do this on their own for setting up
direct MSI injection through KVM. Provide a helper function for
this in MSI code.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Alex Williamson [Tue, 2 Oct 2012 19:22:01 +0000 (13:22 -0600)]
pci-assign: Use pci_intx_route_changed()
Replace open coded version
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Alex Williamson [Tue, 2 Oct 2012 19:21:54 +0000 (13:21 -0600)]
pci: Helper function for testing if an INTx route changed
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Anthony Liguori [Mon, 29 Oct 2012 15:34:29 +0000 (10:34 -0500)]
Merge remote-tracking branch 'kraxel/usb.68' into staging
* kraxel/usb.68: (36 commits)
xhci: fix usb name in caps
xhci: make number of interrupters and slots configurable
xhci: allow disabling interrupters
xhci: flush endpoint context unconditinally
xhci: fix function name in error message
uhci: Use only one queue for ctrl endpoints
uhci: Retry to fill the queue while waiting for td completion
uhci: Always mark a queue valid when we encounter it
uhci: When the guest marks a pending td non-active, cancel the queue
uhci: Detect guest td re-use
uhci: Verify queue has not been changed by guest
uhci: Immediately free queues on device disconnect
uhci: Store ep in UHCIQueue
uhci: Make uhci_fill_queue() actually operate on an UHCIQueue
uhci: Add uhci_read_td() helper function
uhci: Rename UHCIAsync->td to UHCIAsync->td_addr
uhci: Move emptying of the queue's asyncs' queue to uhci_queue_free
uhci: Drop unnecessary forward declaration of some static functions
uhci: Don't retry on error
uhci: cleanup: Add an unlink call to uhci_async_cancel()
...
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Anthony Liguori [Mon, 29 Oct 2012 15:34:05 +0000 (10:34 -0500)]
Merge remote-tracking branch 'kwolf/for-anthony' into staging
* kwolf/for-anthony: (32 commits)
osdep: Less restrictive F_SEFL in qemu_dup_flags()
qemu-iotests: add testcases for mirroring on-source-error/on-target-error
qmp: add pull_event function
mirror: add support for on-source-error/on-target-error
iostatus: forward block_job_iostatus_reset to block job
qemu-iotests: add mirroring test case
mirror: implement completion
qmp: add drive-mirror command
mirror: introduce mirror job
block: introduce BLOCK_JOB_READY event
block: add block-job-complete
block: rename block_job_complete to block_job_completed
block: export dirty bitmap information in query-block
block: introduce new dirty bitmap functionality
block: add bdrv_open_backing_file
block: add bdrv_query_stats
block: add bdrv_query_info
qemu-config: Add new -add-fd command line option
monitor: Prevent removing fd from set during init
monitor: Enable adding an inherited fd to an fd set
...
Conflicts:
vl.c
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Aurelien Jarno [Mon, 29 Oct 2012 13:56:17 +0000 (14:56 +0100)]
Merge branch 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf
* 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf: (22 commits)
PPC: pseries: Remove hack for PIO window
PPC: e500: Map PIO space into core memory region
xen_platform: convert PIO to new memory api read/write
vmport: convert PIO to new memory api read/write
serial: convert PIO to new memory api read/write
rtl8139: convert PIO to new memory api read/write
pckbd: convert PIO to new memory api read/write
pc port92: convert PIO to new memory api read/write
mc146818rtc: convert PIO to new memory api read/write
m48t59: convert PIO to new memory api read/write
i8254: convert PIO to new memory api read/write
es1370: convert PIO to new memory api read/write
virtio-pci: convert PIO to new memory api read/write
ac97: convert PIO to new memory api read/write
pseries: Implement qemu initiated shutdowns using EPOW events
target-ppc: Rework storage of VPA registration state
pseries: Don't allow duplicate registration of hcalls or RTAS calls
Add USB option in machine options
e500: Fix serial initialization
PPC: 440: Emulate DCBR0
...
Aurelien Jarno [Mon, 29 Oct 2012 13:55:51 +0000 (14:55 +0100)]
Merge branch 'queue/qmp' of git://repo.or.cz/qemu/qmp-unstable
* 'queue/qmp' of git://repo.or.cz/qemu/qmp-unstable:
migration: go to paused state after finishing incoming migration with -S
qmp: handle stop/cont in INMIGRATE state
hmp: fix info cpus for sparc targets
Alexander Graf [Mon, 8 Oct 2012 11:54:18 +0000 (13:54 +0200)]
PPC: pseries: Remove hack for PIO window
Now that all users of old_portio are gone, we can remove the hack
that enabled us to support them.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Mon, 8 Oct 2012 10:21:30 +0000 (12:21 +0200)]
PPC: e500: Map PIO space into core memory region
On PPC, we don't have PIO. So usually PIO space behind a PCI bridge is
accessible via MMIO. Do this mapping explicitly by mapping the PIO space
of our PCI bus into a memory region that lives in memory space.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Mon, 8 Oct 2012 11:47:30 +0000 (13:47 +0200)]
xen_platform: convert PIO to new memory api read/write
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Mon, 8 Oct 2012 11:44:24 +0000 (13:44 +0200)]
vmport: convert PIO to new memory api read/write
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Mon, 8 Oct 2012 11:40:29 +0000 (13:40 +0200)]
serial: convert PIO to new memory api read/write
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Mon, 8 Oct 2012 11:35:24 +0000 (13:35 +0200)]
rtl8139: convert PIO to new memory api read/write
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Mon, 8 Oct 2012 11:30:08 +0000 (13:30 +0200)]
pckbd: convert PIO to new memory api read/write
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Mon, 8 Oct 2012 11:24:52 +0000 (13:24 +0200)]
pc port92: convert PIO to new memory api read/write
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Mon, 8 Oct 2012 11:22:28 +0000 (13:22 +0200)]
mc146818rtc: convert PIO to new memory api read/write
Signed-off-by: Alexander Graf <agraf@suse.de>