OSDN Git Service
Daniel Dunbar [Thu, 8 Mar 2012 04:17:15 +0000 (04:17 +0000)]
Revert r152288, "[ADT] Change the trivial FoldingSetNodeID::Add* methods to be
inline.", which is breaking the bots in a way I don't understand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152295
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Akira Hatanaka [Thu, 8 Mar 2012 03:32:42 +0000 (03:32 +0000)]
Test case for r152280, r152285 and r152290.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152292
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Akira Hatanaka [Thu, 8 Mar 2012 03:26:37 +0000 (03:26 +0000)]
Invoke setTargetDAGCombine for SELECT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152290
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Daniel Dunbar [Thu, 8 Mar 2012 02:52:00 +0000 (02:52 +0000)]
[ADT] Change the trivial FoldingSetNodeID::Add* methods to be inline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152288
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Akira Hatanaka [Thu, 8 Mar 2012 02:14:24 +0000 (02:14 +0000)]
Swap the operands of a select node if the false (the second) operand is 0.
For example, this pattern
(select (setcc lhs, rhs, cc), true, 0)
is transformed to this one:
(select (setcc lhs, rhs, inverse(cc)), 0, true)
This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to
replace 0 with $zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152285
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Chandler Carruth [Thu, 8 Mar 2012 02:04:19 +0000 (02:04 +0000)]
Rotate two of the functions used to count bonuses for the inline cost
analysis to be methods on the cost analysis's function info object
instead of the code metrics object. These really are just users of the
code metrics, they're building the information for the function's
analysis.
This is the first step of growing the amount of information we collect
about a function in order to cope with pair-wise simplifications due to
allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152283
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Akira Hatanaka [Thu, 8 Mar 2012 01:59:33 +0000 (01:59 +0000)]
Set minimum function alignment to 3 if target is Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152282
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Akira Hatanaka [Thu, 8 Mar 2012 01:51:59 +0000 (01:51 +0000)]
This patch eliminates redundant instructions that produce 0.
For example, the first instruction in the code below can be eliminated if the
use of $vr0 is replaced with $zero:
addiu $vr0, $zero, 0
add $vr2, $vr1, $vr0
add $vr2, $vr1, $zero
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152280
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Andrew Trick [Thu, 8 Mar 2012 01:41:12 +0000 (01:41 +0000)]
misched interface: Expose the MachineScheduler pass.
Allow targets to provide their own schedulers (subclass of
ScheduleDAGInstrs) to the misched pass. Select schedulers using
-misched=...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152278
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Jim Grosbach [Thu, 8 Mar 2012 00:07:52 +0000 (00:07 +0000)]
ARM don't use MCRelaxAll, as it's not safe on ARM.
The ARM code generator makes aggressive assumptions about the encodings
being selected for branches which MCRelaxAll invalidates.
rdar://
11006355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152268
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Sean Callanan [Wed, 7 Mar 2012 23:05:25 +0000 (23:05 +0000)]
Improved support in RuntimeDyldMachO for generating
code that will be relocated into another memory space.
Now when relocations are resolved, the address of
the relocation in the host memory (where the JIT is)
is passed separately from the address that the
relocation will be at in the target memory (where
the code will run).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152264
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Andrew Trick [Wed, 7 Mar 2012 23:01:09 +0000 (23:01 +0000)]
Cleanup VLIWPacketizer to use the updated ScheduleDAGInstrs interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152262
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Andrew Trick [Wed, 7 Mar 2012 23:01:06 +0000 (23:01 +0000)]
misched prep: Expose the ScheduleDAGInstrs interface so targets may
implement their own MachineScheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152261
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Andrew Trick [Wed, 7 Mar 2012 23:01:02 +0000 (23:01 +0000)]
misched prep: Remove LLVM_LIBRARY_VISIBILITY from ScheduleDAGInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152260
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Andrew Trick [Wed, 7 Mar 2012 23:00:59 +0000 (23:00 +0000)]
misched prep: Comment the ScheduleDAGInstrs interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152259
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Andrew Trick [Wed, 7 Mar 2012 23:00:57 +0000 (23:00 +0000)]
misched prep: Cleanup ScheduleDAGInstrs interface.
ScheduleDAGInstrs will be the main interface for MI-level
schedulers. Make sure it's readable: one page of protected fields, one
page of public methids.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152258
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Andrew Trick [Wed, 7 Mar 2012 23:00:54 +0000 (23:00 +0000)]
misched prep: remove extra "protected"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152257
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Andrew Trick [Wed, 7 Mar 2012 23:00:52 +0000 (23:00 +0000)]
misched prep: rename InsertPos to End.
ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152256
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Andrew Trick [Wed, 7 Mar 2012 23:00:49 +0000 (23:00 +0000)]
misched preparation: rename core scheduler methods for consistency.
We had half the API with one convention, half with another. Now was a
good time to clean it up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152255
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Benjamin Kramer [Wed, 7 Mar 2012 22:48:42 +0000 (22:48 +0000)]
Copy the right amount of elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152254
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Benjamin Kramer [Wed, 7 Mar 2012 22:33:21 +0000 (22:33 +0000)]
SmallPtrSet: Copy all the elements when swapping, not just numelements.
This fixes a build failure in webkit. Copying all elements shouldn't be
necessary, I'll look out for a better fix soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152252
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Chad Rosier [Wed, 7 Mar 2012 20:59:26 +0000 (20:59 +0000)]
[fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point
condition flags to CPSR. This allows us to simplify SelectCmp.
Patch by Zonr Chang <zonr.xchg@gmail.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152243
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Rafael Espindola [Wed, 7 Mar 2012 20:58:59 +0000 (20:58 +0000)]
Use llvm-mc instead of llc. Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152242
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Benjamin Kramer [Wed, 7 Mar 2012 17:07:20 +0000 (17:07 +0000)]
configure: Don't require a perl interpreter to be present, LLVM's buildsystem doesn't depend on perl anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152234
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Chad Rosier [Wed, 7 Mar 2012 17:06:40 +0000 (17:06 +0000)]
Revert r152202 as it's causing internal buildbot failures.
Original commit message:
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect
all 16-bit string table offsets. Also make sure the string to offset table
string is not larger than 65536 characters since larger string literals aren't
portable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152233
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Jakob Stoklund Olesen [Wed, 7 Mar 2012 16:39:35 +0000 (16:39 +0000)]
Fix infinite loop in nested multiclasses.
Patch by Michael Liao!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152232
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Chandler Carruth [Wed, 7 Mar 2012 12:27:35 +0000 (12:27 +0000)]
Try a completely different approach to this type trait to appease older
compilers. It seems that GCC 4.3 (and likely older) simply aren't going
to do SFINAE on non-type template parameters the way Clang and modern
GCCs do...
Now we detect the implicit conversion to an integer type, and then
blacklist classes, pointers, and floating point types. This seems to
work well enough, and I'm hopeful will return the bots to life.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152227
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Chandler Carruth [Wed, 7 Mar 2012 11:31:11 +0000 (11:31 +0000)]
Attempt #2 at appeasing GCC 4.3. This compiler really doesn't like these
traits.
With this change, the pattern used here is *extremely* close to the
pattern used elsewhere in the file, so I'm hoping it survives the
build-bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152225
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Chandler Carruth [Wed, 7 Mar 2012 10:13:40 +0000 (10:13 +0000)]
Try to clarify this comment some.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152221
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Chandler Carruth [Wed, 7 Mar 2012 10:05:35 +0000 (10:05 +0000)]
Switch the is_integral_or_enum trait machinery to use an explicit
template argument and an *implicit* conversion from '0' to a null
pointer. For some bizarre reason, GCC 4.3.2 thinks that the cast to
'(T*)' is invalid inside of an enumerator's value... which it isn't but
whatever. ;] This pattern is used elsewhere in the type_traits header
and so hopefully will survive the wrath of the build bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152220
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Chandler Carruth [Wed, 7 Mar 2012 09:54:06 +0000 (09:54 +0000)]
What's better than fixing and simplifying broken hash functions?
Deleting them because they aren't used. =D
Yell if you need these, I'm happy to instead replace them with nice uses
of the new infrastructure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152219
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Chandler Carruth [Wed, 7 Mar 2012 09:39:46 +0000 (09:39 +0000)]
Remove another outbreak of customized (and completely broken) hashing.
This one is particularly annoying because the hashing algorithm is
highly specialized, with a strange "equivalence" definition that subsets
the fields involved.
Still, this looks at the exact same set of data as the old code, but
without bitwise or-ing over parts of it and other mixing badness. No
functionality changed here. I've left a substantial fixme about the fact
that there is a cleaner and more principled way to do this, but it
requires making the equality definition actual stable for particular
types...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152218
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Chandler Carruth [Wed, 7 Mar 2012 09:32:32 +0000 (09:32 +0000)]
Add support to the hashing infrastructure for automatically hashing both
integral and enumeration types. This is accomplished with a bit of
template type trait magic. Thanks to Richard Smith for the core idea
here to detect viable types by detecting the set of types which can be
default constructed in a template parameter.
This is used (in conjunction with a system for detecting nullptr_t
should it exist) to provide an is_integral_or_enum type trait that
doesn't need a whitelist or direct compiler support.
With this, the hashing is extended to the more general facility. This
will be used in a subsequent commit to hashing more things, but I wanted
to make sure the type trait magic went through the build bots separately
in case other compilers don't like this formulation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152217
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Bill Wendling [Wed, 7 Mar 2012 08:49:42 +0000 (08:49 +0000)]
Where the BranchFolding pass removes a branch then adds another better branch,
the DebugLoc information can be maintained throughout by grabbing the DebugLoc
before the RemoveBranch and then passing the result to the InsertBranch.
Patch by Andrew Stanford-Jason!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152212
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Andrew Trick [Wed, 7 Mar 2012 05:46:04 +0000 (05:46 +0000)]
Fix cmake
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152210
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Andrew Trick [Wed, 7 Mar 2012 05:21:54 +0000 (05:21 +0000)]
comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152209
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Andrew Trick [Wed, 7 Mar 2012 05:21:52 +0000 (05:21 +0000)]
misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.
ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation.
ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class.
ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target.
Specific changes:
- Removed driver code from ScheduleDAG. clearDAG is the only interface needed.
- Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls.
- Added ScheduleDAGInstrs::begin()/end() public API.
- Moved Sequence into the driver layer, which is specific to the scheduling algorithm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208
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Andrew Trick [Wed, 7 Mar 2012 05:21:47 +0000 (05:21 +0000)]
ScheduleDAGInstrs comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152207
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Andrew Trick [Wed, 7 Mar 2012 05:21:44 +0000 (05:21 +0000)]
misched preparation: modularize schedule emission.
ScheduleDAG has nothing to do with how the instructions are scheduled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152206
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Andrew Trick [Wed, 7 Mar 2012 05:21:40 +0000 (05:21 +0000)]
misched preparation: modularize schedule printing.
ScheduleDAG will not refer to the scheduled instruction sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152205
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Andrew Trick [Wed, 7 Mar 2012 05:21:36 +0000 (05:21 +0000)]
misched preparation: modularize schedule verification.
ScheduleDAG will not refer to the scheduled instruction sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152204
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Andrew Trick [Wed, 7 Mar 2012 05:21:32 +0000 (05:21 +0000)]
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152203
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Craig Topper [Wed, 7 Mar 2012 05:17:23 +0000 (05:17 +0000)]
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152202
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Eli Friedman [Wed, 7 Mar 2012 03:37:32 +0000 (03:37 +0000)]
Missing change in r152106 for TinyPtrVector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152201
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Chandler Carruth [Wed, 7 Mar 2012 03:22:32 +0000 (03:22 +0000)]
Switch this code to use hash_combine_range rather than incremental calls
to hash_combine. One of the interfaces could already do this, and the
other can just use a small buffer. This is a much more efficient way to
use the hash_combine interface, although I don't have any particular
benchmark where this code was hot, so I can't measure much of an impact.
It at least doesn't slow anything down.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152200
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Chandler Carruth [Wed, 7 Mar 2012 02:33:09 +0000 (02:33 +0000)]
Cache the sized-ness of struct types, once we reach the steady state of
"is sized". This prevents every query to isSized() from recursing over
every sub-type of a struct type. This could get *very* slow for
extremely deep nesting of structs, as in 177.mesa.
This change is a 45% speedup for 'opt -O2' of 177.mesa.linked.bc, and
likely a significant speedup for other cases as well. It even impacts
-O0 cases because so many part of the code try to check whether a type
is sized.
Thanks for the review from Nick Lewycky and Benjamin Kramer on IRC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152197
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Chandler Carruth [Wed, 7 Mar 2012 02:33:06 +0000 (02:33 +0000)]
Remove an accidental cut/paste of a comment into the middle of
a function. Dunno how I missed this when going through code...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152196
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Nick Lewycky [Wed, 7 Mar 2012 02:27:53 +0000 (02:27 +0000)]
No functionality change. Type::isSized() can be expensive, so avoid calling it
until after other inexpensive tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152195
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Jim Grosbach [Wed, 7 Mar 2012 01:09:17 +0000 (01:09 +0000)]
ARM pre-v6 assembly parsing for umull/smull.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152188
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Jim Grosbach [Wed, 7 Mar 2012 00:52:41 +0000 (00:52 +0000)]
ARM pre-v6 alias for 'nop' to 'mov r0, r0'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152185
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Jim Grosbach [Wed, 7 Mar 2012 00:52:39 +0000 (00:52 +0000)]
Tidy up. Remove dead code that slipped into previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152184
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Andrew Trick [Wed, 7 Mar 2012 00:18:27 +0000 (00:18 +0000)]
Added -view-background to avoid waiting for each GraphViz invocation.
GV and XDOT paths are untested but should work the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152179
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Andrew Trick [Wed, 7 Mar 2012 00:18:25 +0000 (00:18 +0000)]
Added -view-misched=dags options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152178
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Andrew Trick [Wed, 7 Mar 2012 00:18:22 +0000 (00:18 +0000)]
Cleanup in preparation for misched: Move DAG visualization logic.
Soon, ScheduleDAG will not refer to the BB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152177
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Andrew Trick [Wed, 7 Mar 2012 00:18:18 +0000 (00:18 +0000)]
Added MachineBasicBlock::getFullName() to standardize/factor codegen diagnostics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152176
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Andrew Trick [Wed, 7 Mar 2012 00:18:15 +0000 (00:18 +0000)]
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152175
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Andrew Trick [Wed, 7 Mar 2012 00:18:12 +0000 (00:18 +0000)]
Cleanup: DAG building is specific to either SD or MI scheduling. Not part of the target interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152174
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Andrew Trick [Wed, 7 Mar 2012 00:18:08 +0000 (00:18 +0000)]
misched comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152173
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Andrew Trick [Wed, 7 Mar 2012 00:18:05 +0000 (00:18 +0000)]
misched: Use the StartBlock/FinishBlock hooks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152172
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Eric Christopher [Wed, 7 Mar 2012 00:15:19 +0000 (00:15 +0000)]
Add the DW_AT_APPLE_runtime_class attribute to forward declarations
as well as completely defined classes.
This fixes rdar://
10956070
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152171
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Evan Cheng [Tue, 6 Mar 2012 23:33:32 +0000 (23:33 +0000)]
Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152162
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Jim Grosbach [Tue, 6 Mar 2012 23:10:38 +0000 (23:10 +0000)]
ARM more NEON VLD/VST composite physical register refactoring.
Register pair, all lanes subscripting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157
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Jakob Stoklund Olesen [Tue, 6 Mar 2012 22:27:13 +0000 (22:27 +0000)]
Hoist common code out of if statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152153
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Jim Grosbach [Tue, 6 Mar 2012 22:01:44 +0000 (22:01 +0000)]
ARM refactor more NEON VLD/VST instructions to use composite physregs
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150
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Owen Anderson [Tue, 6 Mar 2012 21:48:32 +0000 (21:48 +0000)]
Fix support for encodings up to 64-bits in length. TableGen was silently truncating them to 32-bits prior to this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152148
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Benjamin Kramer [Tue, 6 Mar 2012 20:40:02 +0000 (20:40 +0000)]
SmallPtrSet: Provide a more efficient implementation of swap than the default triple-copy std::swap.
This currently assumes that both sets have the same SmallSize to keep the implementation simple,
a limitation that can be lifted if someone cares.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152143
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Eli Friedman [Tue, 6 Mar 2012 19:58:46 +0000 (19:58 +0000)]
Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152136
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Ted Kremenek [Tue, 6 Mar 2012 19:54:44 +0000 (19:54 +0000)]
Add new load commands for MachO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152135
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Daniel Dunbar [Tue, 6 Mar 2012 19:07:38 +0000 (19:07 +0000)]
build/Darwin: Make it easy to cause all tools to get codesigned (with make CODESIGN_TOOLS=1).
- On OS X 10.7+ this is apparently recommended practice. This maybe should
become a configurey thing one day, but I'm not sure it is right to
automatically turn it on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152133
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Jim Grosbach [Tue, 6 Mar 2012 18:59:19 +0000 (18:59 +0000)]
Tidy up. Kill some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152131
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Jakob Stoklund Olesen [Tue, 6 Mar 2012 18:44:11 +0000 (18:44 +0000)]
Allow the same types in DPair as in QPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152129
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Kevin Enderby [Tue, 6 Mar 2012 18:33:12 +0000 (18:33 +0000)]
Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152127
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Roman Divacky [Tue, 6 Mar 2012 16:41:49 +0000 (16:41 +0000)]
Convert PowerPC to register mask operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152122
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Benjamin Kramer [Tue, 6 Mar 2012 13:32:36 +0000 (13:32 +0000)]
Remove excess const, a const_iterator shouldn't be const itself.
Fixes 1242 warnings from gcc during clang build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152120
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Jay Foad [Tue, 6 Mar 2012 10:43:52 +0000 (10:43 +0000)]
Change ConstantAggrUniqueMap to use Chandler's new hashing
implementation. Patch by Meador Inge
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152116
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Bill Wendling [Tue, 6 Mar 2012 09:23:25 +0000 (09:23 +0000)]
Add column width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152115
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Bill Wendling [Tue, 6 Mar 2012 09:22:03 +0000 (09:22 +0000)]
Remove short tag marker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152114
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Bill Wendling [Tue, 6 Mar 2012 09:20:59 +0000 (09:20 +0000)]
Appease the HTML validation gods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152113
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Bill Wendling [Tue, 6 Mar 2012 09:17:39 +0000 (09:17 +0000)]
Fix validation errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152112
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Bill Wendling [Tue, 6 Mar 2012 09:17:04 +0000 (09:17 +0000)]
Fix validation errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152111
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Bill Wendling [Tue, 6 Mar 2012 08:59:13 +0000 (08:59 +0000)]
Add missing end tags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152110
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Argyrios Kyrtzidis [Tue, 6 Mar 2012 07:14:58 +0000 (07:14 +0000)]
[TinyPtrVector] Add erase method and const-goodness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152107
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Argyrios Kyrtzidis [Tue, 6 Mar 2012 07:14:54 +0000 (07:14 +0000)]
PointerUnion::getAddrOf() does not need to be template since we can only
use the first pointer type for it. Rename it to getAddrOfPtr1().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152106
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Craig Topper [Tue, 6 Mar 2012 06:04:39 +0000 (06:04 +0000)]
Use uint16_t to store indices into string table since C++ only allows 64K string literals so the index into the big string can never be larger than that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152105
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Craig Topper [Tue, 6 Mar 2012 04:39:52 +0000 (04:39 +0000)]
Add asserts to ensure that values will fit into the tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152104
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Craig Topper [Tue, 6 Mar 2012 03:44:22 +0000 (03:44 +0000)]
Increase number of allowed registers in register classes to 64k instead of 256. Widen register class ID to 16-bits. Widen register size and alignment to be up to 64k bytes instead of 256 bytes. This partially reverts r152019 to be less restrictive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152100
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Craig Topper [Tue, 6 Mar 2012 03:28:45 +0000 (03:28 +0000)]
Revert r152016 and allow overlap, sub, super register tables to be more than 64k entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152099
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Argyrios Kyrtzidis [Tue, 6 Mar 2012 03:02:16 +0000 (03:02 +0000)]
Remove UsuallyTinyPtrVector.
It is just a worse version of TinyPtrVector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152097
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Jakob Stoklund Olesen [Tue, 6 Mar 2012 02:48:17 +0000 (02:48 +0000)]
Add <imp-def> operands when reloading into physregs.
When an instruction only writes sub-registers, it is still necessary to
add an <imp-def> operand for the super-register. When reloading into a
virtual register, rewriting will add the operand, but when loading
directly into a virtual register, the <imp-def> operand is still
necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152095
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Eric Christopher [Tue, 6 Mar 2012 02:25:41 +0000 (02:25 +0000)]
Fix up link and a couple small edits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152094
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Eric Christopher [Tue, 6 Mar 2012 02:25:38 +0000 (02:25 +0000)]
Add the beginnings of documentation for the Name Accelerator Tables.
Based on a writeup originally by Greg Clayton.
Abuse div and pre tags horribly. Needs a bit more cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152093
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Eric Christopher [Tue, 6 Mar 2012 02:25:36 +0000 (02:25 +0000)]
Delete trailing whitespace to clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152092
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Argyrios Kyrtzidis [Tue, 6 Mar 2012 02:08:48 +0000 (02:08 +0000)]
Add include/llvm/ADT/UsuallyTinyPtrVector.h which is a vector that
optimizes the case where there is only one element.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152090
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Evan Cheng [Tue, 6 Mar 2012 02:00:52 +0000 (02:00 +0000)]
Avoid finalizeBundles infinite looping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152089
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Owen Anderson [Tue, 6 Mar 2012 00:29:31 +0000 (00:29 +0000)]
Make it possible for a target to mark FSUB as Expand. This requires providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152079
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Lang Hames [Tue, 6 Mar 2012 00:19:55 +0000 (00:19 +0000)]
Split fpscr into two registers: FPSCR and FPSCR_NZCV.
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076
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Eli Friedman [Mon, 5 Mar 2012 23:22:40 +0000 (23:22 +0000)]
A few more cases of missing masking in ComputeMaskedBits; found by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152070
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Jim Grosbach [Mon, 5 Mar 2012 23:16:31 +0000 (23:16 +0000)]
ARM vpush/vpop assembler mnemonics accept an optional size suffix.
rdar://
10988114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152068
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Jim Grosbach [Mon, 5 Mar 2012 23:09:51 +0000 (23:09 +0000)]
Nuke a bit of dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152067
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Eli Friedman [Mon, 5 Mar 2012 23:09:40 +0000 (23:09 +0000)]
Make sure we don't return bits outside the mask in ComputeMaskedBits. PR12189.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152066
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