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Vedant Kumar [Mon, 4 Jun 2018 21:43:28 +0000 (21:43 +0000)]
[Debugify] Preserve analyses in -check-debugify
The -check-debugify pass should preserve all analyses. Otherwise, it may
invalidate an optional analysis and inadvertently alter codegen.
The test case is reduced from deopt-bundle.ll. The result of `opt -O1`
on this file would differ when -debugify-each was toggled. That happened
because CheckDebugify failed to preserve GlobalsAA.
Thanks to Davide Italiano for his help chasing this down!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333959
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David Blaikie [Mon, 4 Jun 2018 21:33:56 +0000 (21:33 +0000)]
Add missing header
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333957
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David Blaikie [Mon, 4 Jun 2018 21:23:21 +0000 (21:23 +0000)]
Move Analysis/Utils/Local.h back to Transforms
Review feedback from r328165. Split out just the one function from the
file that's used by Analysis. (As chandlerc pointed out, the original
change only moved the header and not the implementation anyway - which
was fine for the one function that was used (since it's a
template/inlined in the header) but not in general)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333954
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Amaury Sechet [Mon, 4 Jun 2018 21:20:45 +0000 (21:20 +0000)]
Revert "Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC"
This reverts commit
f0e85c194ae5e87476bc767304470dec85b6774f.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333953
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Jessica Paquette [Mon, 4 Jun 2018 21:14:16 +0000 (21:14 +0000)]
[MachineOutliner] NFC - Move intermediate data structures to MachineOutliner.h
This is setting up to fix bug 37573 cleanly.
This moves data structures that are technically both used in some way by the
target and the general-purpose outlining algorithm into MachineOutliner.h. In
particular, the `Candidate` class is of importance.
Before, the outliner passed the locations of `Candidates` to the target, which
would then make some decisions about the prospective outlined function. This
change allows us to just pass `Candidates` along to the target. This will allow
the target to discard `Candidates` that would be considered unsafe before cost
calculation. Thus, we will be able to remove the unsafe candidates described in
the bug without resorting to torching the entire prospective function.
Also, as a side-effect, it makes the outliner a bit cleaner.
https://bugs.llvm.org/show_bug.cgi?id=37573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333952
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Alexander Ivchenko [Mon, 4 Jun 2018 21:07:35 +0000 (21:07 +0000)]
[X86][ELF][CET] Adding the .note.gnu.property ELF section in X86
In preparation for the proposed linker ABI changes
(https://github.com/hjl-tools/linux-abi/wiki/linux-abi-draft.pdf,
https://github.com/hjl-tools/x86-psABI/wiki/x86-64-psABI-cet.pdf),
this patch enables emission of the .note.gnu.property section to
ELF object files when building CET-enabled modules.
patch by mike.dvoretsky
Differential Revision: https://reviews.llvm.org/D47145
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333951
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Amaury Sechet [Mon, 4 Jun 2018 20:57:27 +0000 (20:57 +0000)]
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333950
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Amaury Sechet [Mon, 4 Jun 2018 20:47:00 +0000 (20:47 +0000)]
Regenerate expected test results for test/CodeGen/X86/pr23103.ll . NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333949
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Scott Linder [Mon, 4 Jun 2018 20:19:45 +0000 (20:19 +0000)]
[CodeGen] Always update divergence in SelectionDAG::UpdateNodeOperands
Some overloads failed to update divergence.
Differential Revision: https://reviews.llvm.org/D47148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333947
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Zachary Turner [Mon, 4 Jun 2018 19:38:11 +0000 (19:38 +0000)]
[Support] Add functions that operate on native file handles on Windows.
Windows' CRT has a limit of 512 open file descriptors, and fds which are
generated by converting a HANDLE via _get_osfhandle count towards this
limit as well.
Regardless, often you find yourself marshalling back and forth between
native HANDLE objects and fds anyway. If we know from the getgo that
we're going to need to work directly with the handle, we can cut out the
marshalling layer while also not contributing to filling up the CRT's
very limited handle table.
On Unix these functions just delegate directly to the existing set of
functions since an fd *is* the native file type. It would be nice, very
long term, if we could convert most uses of fds to file_t.
Differential Revision: https://reviews.llvm.org/D47688
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333945
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Amaury Sechet [Mon, 4 Jun 2018 19:23:22 +0000 (19:23 +0000)]
[DAGcombine] Teach the combiner about -a = ~a + 1
Summary: This include variant for add, uaddo and addcarry. usubo and subcarry require the carry to be flipped to preserve semantic, but we chose to do the transform anyway in that case as to push the transform down the carry chain.
Reviewers: efriedma, spatel, RKSimon, zvi, bkramer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333943
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Teresa Johnson [Mon, 4 Jun 2018 19:20:02 +0000 (19:20 +0000)]
Fix for llvm-dis/llvm-bcanalyzer overflows
Summary:
These tools failed for a very large bitcode file produced by LTO due to
64-bit values being assigned to 32-bit types. For the BitstreamReader.h
fix, the value initially fit into the 32-bit unsigned, but there was an
overflow when multiplying by 32 furter below to compute the bit offset.
No test case in the patch as this requires a huge bitcode file.
Reviewers: pcc, george.karpenkov
Subscribers: mehdi_amini, a.sidorin, llvm-commits
Differential Revision: https://reviews.llvm.org/D47731
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333942
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Alexander Shaposhnikov [Mon, 4 Jun 2018 18:55:41 +0000 (18:55 +0000)]
[llvm-strip] Add missing aliases for --strip-debug
Add missing aliases for --strip-debug: -g, -S, -d.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D47674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333940
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Amaury Sechet [Mon, 4 Jun 2018 18:36:22 +0000 (18:36 +0000)]
Get rid of SETCCE
Summary: It has been deprecated in favor of SETCCCARRY for a year now and isn't used by any in tree backend.
Reviewers: efriedma, craig.topper, dblaikie, bkramer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47685
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333939
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Dmitry Mikulin [Mon, 4 Jun 2018 18:18:12 +0000 (18:18 +0000)]
In thin and full LTO + CFI, direct function calls may go through jump table
entries to reach the target. Since these calls don't require type checks,
we can short-circuit them to their real targets, except in cases when they
can be pre-empted.
Differential Revision: https://reviews.llvm.org/D46326
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333937
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Craig Topper [Mon, 4 Jun 2018 17:58:45 +0000 (17:58 +0000)]
[X86] Don't pass ParitySrc array into isAddSubOrSubAddMask. Instead use a bool output parameter to get the real piece of info we care about. NFC
The ParitySrc array is more of an implementation detail. A single bool to get the final parity is sufficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333935
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Stanislav Mekhanoshin [Mon, 4 Jun 2018 17:57:40 +0000 (17:57 +0000)]
[AMDGPU] Small refactoring in the scheduler
After last changes some code can be simplified.
Differential Revision: https://reviews.llvm.org/D47661
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333934
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Stanislav Mekhanoshin [Mon, 4 Jun 2018 17:21:54 +0000 (17:21 +0000)]
[AMDGPU] Factored out common part of GCNRPTracker::reset()
Differential Revision: https://reviews.llvm.org/D47664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333931
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Sam Clegg [Mon, 4 Jun 2018 17:01:20 +0000 (17:01 +0000)]
[MachO] Add out-of-bounds check to MachOObjectFile.cpp
This is a followup to rL333496.
Differential Revision: https://reviews.llvm.org/D47544
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333929
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Sam Clegg [Mon, 4 Jun 2018 16:59:26 +0000 (16:59 +0000)]
[WebAssembly] Fix .td files after rL333900
Differential Revision: https://reviews.llvm.org/D47727
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333928
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John Brawn [Mon, 4 Jun 2018 16:53:57 +0000 (16:53 +0000)]
[ValueTracking] Match select abs pattern when there's an sext involved
When checking a select to see if it matches an abs, allow the true/false values
to be a sign-extension of the comparison value instead of requiring that they're
directly the comparison value, as all the comparison cares about is the sign of
the value.
This fixes a regression due to r333702, where we were no longer generating ctlz
due to isKnownNonNegative failing to match such a pattern.
Differential Revision: https://reviews.llvm.org/D47631
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333927
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Mark Searles [Mon, 4 Jun 2018 16:51:59 +0000 (16:51 +0000)]
[AMDGPU][Waitcnt] Fix handling of flat instrs
On GFX9 and earlier, flat memory ops may decrement VMCNT out-of-order as well as LGKMCNT out-of-order.
Differential Revision: https://reviews.llvm.org/D46616
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333926
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Simon Pilgrim [Mon, 4 Jun 2018 16:48:13 +0000 (16:48 +0000)]
[X86] Only accept const SelectionDAG to resolveTargetShuffleInputs/getFauxShuffleMask
These methods should only be using SelectionDAG for analysis (known/sign bits etc), not node creation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333925
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Benjamin Kramer [Mon, 4 Jun 2018 16:12:33 +0000 (16:12 +0000)]
[NVPTX] Delete dead code from the AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333924
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Andrea Di Biagio [Mon, 4 Jun 2018 15:43:09 +0000 (15:43 +0000)]
[RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca.
This patch is the last of a sequence of three patches related to LLVM-dev RFC
"MC support for variant scheduling classes".
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html
This fixes PR36672.
The main goal of this patch is to teach llvm-mca how to solve variant scheduling
classes. This patch does that, plus it adds new variant scheduling classes to
the BtVer2 scheduling model to identify so-called zero-idioms (i.e. so-called
dependency breaking instructions that are known to generate zero, and that are
optimized out in hardware at register renaming stage).
Without the BtVer2 change, this patch would not have had any meaningful tests.
This patch is effectively the union of two changes:
1) a change that teaches llvm-mca how to resolve variant scheduling classes.
2) a change to the BtVer2 scheduling model that allows us to special-case
packed XOR zero-idioms (this partially fixes PR36671).
Differential Revision: https://reviews.llvm.org/D47374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333909
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Alexander Ivchenko [Mon, 4 Jun 2018 15:14:18 +0000 (15:14 +0000)]
[llvm-readobj] Support GNU_PROPERTY_X86_FEATURE_1_AND notes in .note.gnu.property
Resubmit of r333424. This version contains the fix for fails found by buildbots
on some targets.
This patch allows parsing GNU_PROPERTY_X86_FEATURE_1_AND
notes in .note.gnu.property sections. These notes
indicate that the object file is built to support Intel CET.
patch by mike.dvoretsky
Differential Revision: https://reviews.llvm.org/D47473
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333908
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Krzysztof Parzyszek [Mon, 4 Jun 2018 14:54:53 +0000 (14:54 +0000)]
[SelectionDAG] Add missing closing parentheses in comments, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333907
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Nicolai Haehnle [Mon, 4 Jun 2018 14:45:20 +0000 (14:45 +0000)]
AMDGPU: Make various NamedOperands upper case
Summary:
Avoid name clashes with the corresponding bit fields in the instruction
encoding.
Change-Id: Id1644e703e976e78f7af93788d9f44cb48c3251f
Reviewers: arsenm, rampitec, kzhuravl
Subscribers: wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D47433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333905
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Nicolai Haehnle [Mon, 4 Jun 2018 14:45:12 +0000 (14:45 +0000)]
TableGen/DAGPatterns: Allow bit constants in addition to int constants
Summary:
Implicit casting is a simple quality of life improvement.
Change-Id: I3d2b31b8b8f12cbb1e84f691e359fa713a9c4b42
Reviewers: tra, simon_tatham, craig.topper, MartinO, arsenm
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D47432
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333904
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Nicola Zaghen [Mon, 4 Jun 2018 14:40:34 +0000 (14:40 +0000)]
[ReleaseNotes] Formatting fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333902
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Nicolai Haehnle [Mon, 4 Jun 2018 14:26:12 +0000 (14:26 +0000)]
TableGen: some LangRef doc fixes
Summary: Change-Id: I1442e2daa09cab727a01d8c31893b50e644a5cd3
Reviewers: tra, simon_tatham, craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47530
Change-Id: I397655dd18b7ff978c1affa3174740d9c1a82594
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333901
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Nicolai Haehnle [Mon, 4 Jun 2018 14:26:05 +0000 (14:26 +0000)]
TableGen: Streamline the semantics of NAME
Summary:
The new rules are straightforward. The main rules to keep in mind
are:
1. NAME is an implicit template argument of class and multiclass,
and will be substituted by the name of the instantiating def/defm.
2. The name of a def/defm in a multiclass must contain a reference
to NAME. If such a reference is not present, it is automatically
prepended.
And for some additional subtleties, consider these:
3. defm with no name generates a unique name but has no special
behavior otherwise.
4. def with no name generates an anonymous record, whose name is
unique but undefined. In particular, the name won't contain a
reference to NAME.
Keeping rules 1&2 in mind should allow a predictable behavior of
name resolution that is simple to follow.
The old "rules" were rather surprising: sometimes (but not always),
NAME would correspond to the name of the toplevel defm. They were
also plain bonkers when you pushed them to their limits, as the old
version of the TableGen test case shows.
Having NAME correspond to the name of the toplevel defm introduces
"spooky action at a distance" and breaks composability:
refactoring the upper layers of a hierarchy of nested multiclass
instantiations can cause unexpected breakage by changing the value
of NAME at a lower level of the hierarchy. The new rules don't
suffer from this problem.
Some existing .td files have to be adjusted because they ended up
depending on the details of the old implementation.
Change-Id: I694095231565b30f563e6fd0417b41ee01a12589
Reviewers: tra, simon_tatham, craig.topper, MartinO, arsenm, javed.absar
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D47430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333900
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Nicola Zaghen [Mon, 4 Jun 2018 13:55:09 +0000 (13:55 +0000)]
[ReleaseNotes] Add release note for the new LLVM_DEBUG macro.
This is to provide a way to migrate from the old DEBUG macro to the new one.
Differential Revision: https://reviews.llvm.org/D47528
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333898
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Simon Dardis [Mon, 4 Jun 2018 12:50:32 +0000 (12:50 +0000)]
[mips] Restore the availablity of trap for microMIPS
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D47584
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333895
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Greg Bedwell [Mon, 4 Jun 2018 12:30:10 +0000 (12:30 +0000)]
[llvm-mca][UpdateTestChecks] Prevent an IndexError being raised when given empty input
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333894
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Greg Bedwell [Mon, 4 Jun 2018 12:30:03 +0000 (12:30 +0000)]
[llvm-mca] Regenerate a test to remove a double newline
Command used: py update_mca_test_checks.py ..\test\tools\llvm-mca\*\*.s ..\test\tools\llvm-mca\*\*\*.s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333893
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Andrea Di Biagio [Mon, 4 Jun 2018 12:23:07 +0000 (12:23 +0000)]
[llvm-mca] Track cycles contributed by resources that are in a 'Super' relationship.
This is required if we want to correctly match the behavior of method
SubtargetEmitter::ExpandProcResource() in Tablegen. When computing the set of
"consumed" processor resources and resource cycles, the logic in
ExpandProcResource() doesn't update the number of resource cycles contributed by
a "Super" resource to a group. We need to take this into account when a model
declares a processor resource which is part of a 'processor resource group', and
it is also used as the "Super" of other resources.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333892
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Roman Lebedev [Mon, 4 Jun 2018 11:48:46 +0000 (11:48 +0000)]
[llvm-mca] Make sure not to end the test files with an empty line.
Summary:
It's super irritating.
[properly configured] git client then complains about that double-newline,
and you have to use `--force` to ignore the warning, since even if you
fix it manually, it will be reintroduced the very next runtime :/
Reviewers: RKSimon, andreadb, courbet, craig.topper, javed.absar, gbedwell
Reviewed By: gbedwell
Subscribers: javed.absar, tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D47697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333887
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Clement Courbet [Mon, 4 Jun 2018 11:43:40 +0000 (11:43 +0000)]
[llvm-exegesis][NFC] Use an enum instead of a string for benchmark mode.
Summary: YAML encoding is backwards-compatible.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D47705
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333886
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Clement Courbet [Mon, 4 Jun 2018 11:11:55 +0000 (11:11 +0000)]
[llvm-exegesis] Analysis: Show inconsistencies between checked-in and measured data.
Summary:
We now highlight any sched classes whose measurements do not match the
LLVM SchedModel. "bad" clusters are marked in red.
Screenshot in phabricator diff.
Reviewers: gchatelet
Subscribers: tschuett, mgrang, RKSimon, llvm-commits
Differential Revision: https://reviews.llvm.org/D47639
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333884
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Luke Geeson [Mon, 4 Jun 2018 09:41:32 +0000 (09:41 +0000)]
[AArch64] Audit on rL333634 to fix FP16 Disasm BitPatterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333879
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Sander de Smalen [Mon, 4 Jun 2018 07:24:23 +0000 (07:24 +0000)]
[AArch64][SVE] Fix range for DUP immediates (16bit elts)
For immediates used in DUP instructions that have the range
-128 to 127, or a multiple of 256 in the range -32768 to 32512,
one could argue that when the result element size is 16bits (.h),
the value can be considered both signed and unsigned.
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333873
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Sander de Smalen [Mon, 4 Jun 2018 07:07:35 +0000 (07:07 +0000)]
[AArch64][SVE] Asm: Print indexed element 0 as FPR.
Print the first indexed element as a FP register, for example:
mov z0.d, z1.d[0]
Is now printed as:
mov z0.d, d1
Next to printing, this patch also adds aliases to parse 'mov z0.d, d1'.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47571
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333872
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Sander de Smalen [Mon, 4 Jun 2018 06:40:55 +0000 (06:40 +0000)]
[AArch64][SVE] Asm: Support for indexed DUP instructions.
Unpredicated copy of indexed SVE element to SVE vector,
along with MOV-aliases.
For example:
dup z0.h, z1.h[0]
duplicates the first 16-bit element from z1 to all elements in
the result vector z0.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D47570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333871
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Sander de Smalen [Mon, 4 Jun 2018 05:58:06 +0000 (05:58 +0000)]
[AArch64][SVE] Asm: Support for FCPY immediate instructions.
Predicated copy of floating-point immediate value to SVE vector,
along with MOV-aliases.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: javed.absar
Differential Revision: https://reviews.llvm.org/D47518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333869
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Sander de Smalen [Mon, 4 Jun 2018 05:40:46 +0000 (05:40 +0000)]
[AArch64][SVE] Asm: Support for CPY immediate instructions
Predicated copy of possibly shifted immediate value into SVE
vector, along with MOV-aliases.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47517
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333868
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Vedant Kumar [Mon, 4 Jun 2018 03:33:01 +0000 (03:33 +0000)]
[Debugify] Add debug intrinsics before terminating musttail calls
After r333856, opt -debugify would just stop emitting debug value
intrinsics after encountering a musttail call. This wasn't sufficient to
avoid verifier failures.
Debug value intrinicss for all instructions preceding a musttail call
must also be emitted before the musttail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333866
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Serguei Katkov [Mon, 4 Jun 2018 02:52:36 +0000 (02:52 +0000)]
[InstCombine] Fix div handling
When we optimize select basing on fact that div by 0 is undef
we should not traverse the instruction which are not guaranteed to
transfer execution to next instruction. Guard intrinsic is an example.
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47576
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333864
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Vedant Kumar [Mon, 4 Jun 2018 00:11:49 +0000 (00:11 +0000)]
[Debugify] Don't apply DI before the bitcode writer pass
Applying synthetic debug info before the bitcode writer pass has no
testing-related purpose. This commit prevents that from happening.
It also adds tests which check that IR produced with/without
-debugify-each enabled is identical after stripping. This makes it
possible to check that individual passes (or full pipelines) are
invariant to debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333861
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Vedant Kumar [Mon, 4 Jun 2018 00:11:48 +0000 (00:11 +0000)]
[opt] Add a -strip-module-flags option
The -strip-module-flags option strips llvm.module.flags metadata from a
module at the beginning of the opt pipeline.
This will be used to test whether the output of a pass is debug info
(DI) invariant.
E.g, after applying synthetic debug info to a test case, we'd like to
strip out all DI-related metadata and check that the final IR is
identical to a baseline file without any DI applied, to check that
optimizations aren't inhibited by debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333860
91177308-0d34-0410-b5e6-
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Vedant Kumar [Mon, 4 Jun 2018 00:11:47 +0000 (00:11 +0000)]
Reformat overflowing lines, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333859
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Craig Topper [Sun, 3 Jun 2018 23:24:17 +0000 (23:24 +0000)]
[X86] Remove and autoupgrade masked avx512vnni intrinsics using the unmasked intrinsics and select instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333857
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Vedant Kumar [Sun, 3 Jun 2018 22:50:22 +0000 (22:50 +0000)]
[Debugify] Skip dbg.value placement for EH pads, musttail
Placing meta-instructions into EH pads breaks certain IR invariants, as
does placing instructions after a musttail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333856
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Chris Bieneman [Sun, 3 Jun 2018 20:33:42 +0000 (20:33 +0000)]
Re-land: [MachO] Fixing ub in MachO BinaryFormat
This re-lands r333797 with a fix for big endian systems.
Original commit message:
This isn't encountered anywhere inside LLVM, so I wrote a test case to expose the issue and verify that it is fixed.
The basic problem is that the macho_load_command union contains all load comamnd structs. Load command structs in 32-bit macho files can be 32-bit aligned instead of 64-bit aligned.
There are some strange circumstances in which this can be exposed in a 64-bit macho if the load commands are invalid or if a 32-bit aligned load command is used. In the past we've worked around this type of problem with changes like r264232.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333854
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Lang Hames [Sun, 3 Jun 2018 19:22:48 +0000 (19:22 +0000)]
[ORC] Add a constructor to create an IRMaterializationUnit from a module and
pre-existing SymbolFlags and SymbolToDefinition maps.
This constructor is useful when delegating work from an existing
IRMaterialiaztionUnit to a new one, as it avoids the cost of re-computing these
maps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333852
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Simon Pilgrim [Sun, 3 Jun 2018 18:15:06 +0000 (18:15 +0000)]
[X86][TBM] Use realistic BEXTR control bits
Avoid constant values that are guaranteed to give zero
Found while investigating BEXTR optimizations for PR34042.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333849
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Sanjay Patel [Sun, 3 Jun 2018 16:35:26 +0000 (16:35 +0000)]
[InstCombine] improve sub with bool folds
There's a patchwork of existing transforms trying to handle
these cases, but as seen in the changed test, we weren't
catching them all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333845
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Simon Pilgrim [Sun, 3 Jun 2018 14:56:04 +0000 (14:56 +0000)]
[X86][AVX512] Cleanup intrinsics tests
Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage.
Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333843
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Simon Pilgrim [Sun, 3 Jun 2018 14:31:30 +0000 (14:31 +0000)]
[X86][AVX512BW] Regenerate arithmetic tests using update_llc_test_checks.py script
Require manual stripping of existing CHECKs as update_llc_test_checks doesn't remove them if they're outside the function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333842
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Simon Pilgrim [Sun, 3 Jun 2018 14:11:34 +0000 (14:11 +0000)]
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests
Further refactoring will wait until D47452 has landed.
Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333841
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Simon Pilgrim [Sun, 3 Jun 2018 13:55:17 +0000 (13:55 +0000)]
[X86][BMI] Remove CTTZ tests - this is fully covered in clz.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333840
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Simon Pilgrim [Sun, 3 Jun 2018 13:38:52 +0000 (13:38 +0000)]
[X86][TBM] Branch off i32 intrinsics and test on 32/64 bits
Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333839
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Amaury Sechet [Sun, 3 Jun 2018 12:56:24 +0000 (12:56 +0000)]
Remove SETCCE use from Lanai's backend
Summary: This creates a small perf regression, but after talking with Jacques Pienaar, he was good with it to get things moving toward removng SETCCE.
Reviewers: jpienaar, bryant
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47626
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333838
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Lang Hames [Sun, 3 Jun 2018 02:18:03 +0000 (02:18 +0000)]
[ORC] Use JITEvaluatedSymbol for IndirectStubsManager findStub and findPointer.
Existing implementations of these methods do not require lazy materialization,
and switching to JITEvaluatedSymbol allows us to remove error checking on the
client side.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333835
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Simon Pilgrim [Sat, 2 Jun 2018 21:35:48 +0000 (21:35 +0000)]
[X86][SSE] Cleanup AVX1 intrinsics tests
Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary, strip -mcpu usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333834
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Simon Pilgrim [Sat, 2 Jun 2018 20:25:56 +0000 (20:25 +0000)]
[X86][SSE] Cleanup SSE1 intrinsics tests
Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333833
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Simon Pilgrim [Sat, 2 Jun 2018 19:43:14 +0000 (19:43 +0000)]
[X86][SSE] Cleanup SSE2 intrinsics tests
Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333832
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Simon Pilgrim [Sat, 2 Jun 2018 18:41:46 +0000 (18:41 +0000)]
[X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests
Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333831
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Simon Pilgrim [Sat, 2 Jun 2018 18:01:09 +0000 (18:01 +0000)]
[X86][SSE4] Tweak rL333828 sse41/sse42 cleanup to recover SKX/EVEX2VEX testing
Just testing for avx512f was missing the tests for EVEX TO VEX Compression encoding etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333830
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Simon Pilgrim [Sat, 2 Jun 2018 17:33:26 +0000 (17:33 +0000)]
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests
Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary
Added some missing encoding checks to SSE4A tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333828
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Simon Pilgrim [Sat, 2 Jun 2018 17:22:13 +0000 (17:22 +0000)]
[X86][BMI2] Test i32 intrinsics on 32/64 bits + branch off i64 tests
I had to tweak the i32 tests so we check both reg-reg and reg-mem cases.
I also added i64 load tests.
Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333827
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Simon Pilgrim [Sat, 2 Jun 2018 17:02:27 +0000 (17:02 +0000)]
[X86][BMI1] Remove test for non-existent andn i16 instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333826
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Ivan A. Kosarev [Sat, 2 Jun 2018 16:40:03 +0000 (16:40 +0000)]
[NEON] Support VLD1xN intrinsics in AArch32 mode (LLVM part)
We currently support them only in AArch64. The NEON Reference,
however, says they are 'ARMv7, ARMv8' intrinsics.
Differential Revision: https://reviews.llvm.org/D47120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333825
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Ivan A. Kosarev [Sat, 2 Jun 2018 16:38:38 +0000 (16:38 +0000)]
Revert r333819 "[NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)"
The LLVM part was committed instead of the Clang part.
Differential Revision: https://reviews.llvm.org/D47121
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333824
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Michael J. Spencer [Sat, 2 Jun 2018 16:33:01 +0000 (16:33 +0000)]
[MC] Add assembler support for .cg_profile.
Object FIle Representation
At codegen time this is emitted into the ELF file a pair of symbol indices and a weight. In assembly it looks like:
.cg_profile a, b, 32
.cg_profile freq, a, 11
.cg_profile freq, b, 20
When writing an ELF file these are put into a SHT_LLVM_CALL_GRAPH_PROFILE (0x6fff4c02) section as (uint32_t, uint32_t, uint64_t) tuples as (from symbol index, to symbol index, weight).
Differential Revision: https://reviews.llvm.org/D44965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333823
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Craig Topper [Sat, 2 Jun 2018 16:30:39 +0000 (16:30 +0000)]
[X86] Add tied source operand to AVX5124FMAPS and AVX5124VNNIW instructions.
This doesn't affect the assembly or disassembly, but is more accurate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333822
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Craig Topper [Sat, 2 Jun 2018 16:30:36 +0000 (16:30 +0000)]
[X86] Fix warning message for AVX5124FMAPS and AVX5124VNNIW instructions in the assembly parser.
The caret was positioned on the wrong operand. It's too hard to get right so just put the caret at the beginning of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333821
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Sanjay Patel [Sat, 2 Jun 2018 16:27:44 +0000 (16:27 +0000)]
[InstCombine] call simplify before trying vector folds
As noted in the review thread for rL333782, we could have
made a bug harder to hit if we were simplifying instructions
before trying other folds.
The shuffle transform in question isn't ever a simplification;
it's just a canonicalization. So I've renamed that to make that
clearer.
This is NFCI at this point, but I've regenerated the test file
to show the cosmetic value naming difference of using
instcombine's RAUW vs. the builder.
Possible follow-ups:
1. Move reassociation folds after simplifies too.
2. Refactor common code; we shouldn't have so much repetition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333820
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Ivan A. Kosarev [Sat, 2 Jun 2018 16:26:42 +0000 (16:26 +0000)]
[NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)
We currently support them only in AArch64. The NEON Reference,
however, says they are 'ARMv7, ARMv8' intrinsics.
Differential Revision: https://reviews.llvm.org/D47121
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333819
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Sanjay Patel [Sat, 2 Jun 2018 16:16:42 +0000 (16:16 +0000)]
[InstCombine] add more tests for shuffle-binop; NFC
As noted in the review thread for rL333782, we're lacking coverage
for this transform, so add tests for each binop opcode with constant
operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333818
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Fangrui Song [Sat, 2 Jun 2018 06:00:35 +0000 (06:00 +0000)]
[Support] Remove unused raw_ostream::handle whose anchor role was superseded by anchor()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333817
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Craig Topper [Sat, 2 Jun 2018 02:15:10 +0000 (02:15 +0000)]
[X86] Add encoding information for the AVX5124FMAPS and AVX5124VNNIW instructions so they can be assembled and disassembled.
These instructions are unusual in that they operate on 4 consecutive registers so supporting them in codegen will be more difficult than normal.
Includes an assembler check to warn if the source register is not the first register of a 4 register group.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333812
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Chandler Carruth [Sat, 2 Jun 2018 01:29:01 +0000 (01:29 +0000)]
[PM/LoopUnswitch] Fix how the cloned loops are handled when updating analyses.
Summary:
I noticed this issue because we didn't put the primary cloned loop into
the `NonChildClonedLoops` vector and so never iterated on it. Once
I fixed that, it made it clear why I had to do a really complicated and
unnecesasry dance when updating the loops to remain in canonical form --
I was unwittingly working around the fact that the primary cloned loop
wasn't in the expected list of cloned loops. Doh!
Now that we include it in this vector, we don't need to return it and we
can consolidate the update logic as we correctly have a single place
where it can be handled.
I've just added a test for the iteration order aspect as every time
I changed the update logic partially or incorrectly here, an existing
test failed and caught it so that seems well covered (which is also
evidenced by the extensive working around of this missing update).
Reviewers: asbirlea, sanjoy
Subscribers: mcrosier, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D47647
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333811
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Vedant Kumar [Sat, 2 Jun 2018 00:05:17 +0000 (00:05 +0000)]
Remove the test from r333801
In r333801 I added a test for a dump method that, for reasons I don't
understand, fails on an msvc bot:
http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/12306/
I'll remove the test for now to unblock the bot and try to look into why
there's a discrepancy on this platform later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333807
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Roman Tereshin [Fri, 1 Jun 2018 23:15:09 +0000 (23:15 +0000)]
[DebugInfo] Refactoring DIType::setFlags to DIType::cloneWithFlags, NFC
and using the latter in DIBuilder::createArtificialType and
DIBuilder::createObjectPointerType methods as well as introducing
mirroring DISubprogram::cloneWithFlags and
DIBuilder::createArtificialSubprogram methods.
The primary goal here is to add createArtificialSubprogram to support
a pass downstream while keeping the method consistent with the
existing ones and making sure we don't encourage changing already
created DI-nodes.
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D47615
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333806
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Chris Bieneman [Fri, 1 Jun 2018 23:09:37 +0000 (23:09 +0000)]
Revert "Re-land: [MachO] Fixing ub in MachO BinaryFormat"
This reverts commit r333803.
Still breaking on big endian. Will sort this out later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333805
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Craig Topper [Fri, 1 Jun 2018 22:59:07 +0000 (22:59 +0000)]
[X86] Do something sensible when an expand load intrinsic is passed a 0 mask.
Previously we just returned undef, but really we should be returning the pass thru input. We also need to make sure we preserve the chain output that the original intrinsic node had to maintain connectivity in the DAG. So we should just return the incoming chain as the output chain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333804
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Chris Bieneman [Fri, 1 Jun 2018 22:52:59 +0000 (22:52 +0000)]
Re-land: [MachO] Fixing ub in MachO BinaryFormat
This re-lands r333797 with a fix for big endian systems.
Original commit message:
This isn't encountered anywhere inside LLVM, so I wrote a test case to expose the issue and verify that it is fixed.
The basic problem is that the macho_load_command union contains all load comamnd structs. Load command structs in 32-bit macho files can be 32-bit aligned instead of 64-bit aligned.
There are some strange circumstances in which this can be exposed in a 64-bit macho if the load commands are invalid or if a 32-bit aligned load command is used. In the past we've worked around this type of problem with changes like r264232.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333803
91177308-0d34-0410-b5e6-
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Vedant Kumar [Fri, 1 Jun 2018 22:33:15 +0000 (22:33 +0000)]
Add a debug dump for DbgValueHistoryMap
This makes it easier to inspect the results of
DbgValueHistoryCalculator.
Differential Revision: https://reviews.llvm.org/D47663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333801
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Craig Topper [Fri, 1 Jun 2018 22:28:28 +0000 (22:28 +0000)]
[X86] Add isel patterns to use vexpand with zero masking when the passthru value is a zero vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333800
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Chris Bieneman [Fri, 1 Jun 2018 22:28:23 +0000 (22:28 +0000)]
Revert "[MachO] Fixing ub in MachO BinaryFormat"
This reverts commit r333797.
This patch is failing on BigEndian bots. I will fix and re-land:
http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/19505/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333799
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Zachary Turner [Fri, 1 Jun 2018 22:23:46 +0000 (22:23 +0000)]
Move some function declarations out of WindowsSupport.h
The idea behind WindowsSupport.h is that it's in the source directory so
that windows.h'isms don't leak out into the larger LLVM project. To that
end, any symbol that references a symbol from windows.h must be in this
private header, and not in a public header.
However, we had some useful utility functions in WindowsSupport.h which
have no dependency on the Windows API, but still only make sense on
Windows. Those functions should be usable outside of Support since there
is no risk of causing a windows.h leak. Although this introduces some
preprocessor logic in some header files, It's not too egregious and it's
better than the alternative of duplicating a ton of code.
Differential Revision: https://reviews.llvm.org/D47662
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333798
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Chris Bieneman [Fri, 1 Jun 2018 22:07:36 +0000 (22:07 +0000)]
[MachO] Fixing ub in MachO BinaryFormat
This isn't encountered anywhere inside LLVM, so I wrote a test case to expose the issue and verify that it is fixed.
The basic problem is that the macho_load_command union contains all load comamnd structs. Load command structs in 32-bit macho files can be 32-bit aligned instead of 64-bit aligned.
There are some strange circumstances in which this can be exposed in a 64-bit macho if the load commands are invalid or if a 32-bit aligned load command is used. In the past we've worked around this type of problem with changes like r264232.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333797
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Craig Topper [Fri, 1 Jun 2018 21:59:24 +0000 (21:59 +0000)]
[X86] Expand the testing of expand and compress intrinsics
The avx512f intrinsic tests were in the avx512vl file. We were also missing some combinations of masking.
This does show that we fail to use the zero masking form of expand loads when the passthru is zero. I'll try to get that fixed shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333795
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Craig Topper [Fri, 1 Jun 2018 21:59:22 +0000 (21:59 +0000)]
[X86] Add fast-isel tests for avx512vbmi2 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333794
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Karl-Johan Karlsson [Fri, 1 Jun 2018 19:34:35 +0000 (19:34 +0000)]
[ConstantFold] Disallow folding vector geps into bitcasts
Summary:
Getelementptr returns a vector of pointers, instead of a single address,
when one or more of its arguments is a vector. In such case it is not
possible to simplify the expression by inserting a bitcast of operand(0)
into the destination type, as it will create a bitcast between different
sizes.
Reviewers: majnemer, mkuper, mssimpso, spatel
Reviewed By: spatel
Subscribers: lebedev.ri, llvm-commits
Differential Revision: https://reviews.llvm.org/D46379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333783
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Sanjay Patel [Fri, 1 Jun 2018 19:23:18 +0000 (19:23 +0000)]
[InstCombine] fix vector shuffle transform to replace undef elements (PR37648)
This bug:
https://bugs.llvm.org/show_bug.cgi?id=37648
...was created with the enhancement to this transform with rL332479.
The urem test shows the disaster potential: any undef divisor lane makes
the whole op undef.
The test diffs show that vector demanded elements turns some of the potential,
but not all, unused binop operands back into undef already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333782
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Sanjay Patel [Fri, 1 Jun 2018 18:52:38 +0000 (18:52 +0000)]
[InstCombine] add tests for broken shuffle transform (PR37648)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333779
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Simon Atanasyan [Fri, 1 Jun 2018 16:37:53 +0000 (16:37 +0000)]
[mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructions
The `MipsAsmParser::loadImmediate` can load immediates of various sizes
into a register. Idea of this change is to use `loadImmediate` in the
`MipsAsmParser::expandMemInst` method to load offset into a register and
then call required load/store instruction.
The patch removes separate `expandLoadInst` and `expandStoreInst`
methods and does everything in the `expandMemInst` method to escape code
duplication.
Differential Revision: https://reviews.llvm.org/D47316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333774
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Simon Atanasyan [Fri, 1 Jun 2018 16:37:42 +0000 (16:37 +0000)]
[mips] Extend list of relocations supported by the `.reloc` directive
Supporting GOT and TLS related relocations by the `.reloc` directive is
useful for purpose of testing various tools like a linker, for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333773
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