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Vedant Kumar [Wed, 12 Sep 2018 21:59:38 +0000 (21:59 +0000)]
[llvm-cov] Delete custom JSON serialization code (NFC)
Teach llvm-cov to use the new llvm JSON library, and remove some
redundant/brittle JSON serialization tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342088
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Lang Hames [Wed, 12 Sep 2018 21:49:02 +0000 (21:49 +0000)]
[ORC] Merge ExecutionSessionBase with ExecutionSession by moving a couple of
template methods in JITDylib out-of-line.
This also splits JITDylib::define into a pair of template methods, one taking an
lvalue reference and the other an rvalue reference. This simplifies the
templates at the cost of a small amount of code duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342087
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Lang Hames [Wed, 12 Sep 2018 21:48:59 +0000 (21:48 +0000)]
[ORC] Add a special 'main' JITDylib that is created on ExecutionSession
construction, a new convenience lookup method, and add-to layer methods.
ExecutionSession now creates a special 'main' JITDylib upon construction. All
subsequently created JITDylibs are added to the main JITDylib's search order by
default (controlled by the AddToMainDylibSearchOrder parameter to
ExecutionSession::createDylib). The main JITDylib's search order will be used in
the future to properly handle cross-JITDylib weak symbols, with the first
definition in this search order selected.
This commit also adds a new ExecutionSession::lookup convenience method that
performs a blocking lookup using the main JITDylib's search order, as this will
be a very common operation for clients.
Finally, new convenience overloads of IRLayer and ObjectLayer's add methods are
introduced that add the given program representations to the main dylib, which
is likely to be the common case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342086
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Heejin Ahn [Wed, 12 Sep 2018 21:34:39 +0000 (21:34 +0000)]
[WebAssembly] Make tied inline asm operands work again
Summary:
rL341389 broke code with tied register operands in inline assembly. For
example, `asm("" : "=r"(var) : "0"(var));`
The code above specifies the input operand to be in the same register
with the output operand, tying the two register. This patch makes this
kind of code work again.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, eraman, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D51991
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342084
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Sanjay Patel [Wed, 12 Sep 2018 21:29:11 +0000 (21:29 +0000)]
revert r341288 - [Reassociate] swap binop operands to increase factoring potential
This causes or exposes indeterminism that is visible in the output of -reassociate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342083
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Sanjay Patel [Wed, 12 Sep 2018 21:13:37 +0000 (21:13 +0000)]
[InstCombine] add tests for unsigned add overflow; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342082
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Michael Berg [Wed, 12 Sep 2018 21:09:59 +0000 (21:09 +0000)]
Guard FMF context by excluding some FP operators from FPMathOperator
Summary:
Some FPMathOperators succeed and the retrieve FMF context when they never have it, we should omit these cases to keep from removing FMF context.
For instance when we visit some FPMathOperator mapped Instructions which never have FMF flags and a Node was associated which does have FMF flags, that Node today will have all its flags cleared via the intersect operation. With this change, we exclude associating Nodes that never have FPMathOperator status under FMF.
Reviewers: spatel, wristow, arsenm, hfinkel, aemerson
Reviewed By: spatel
Subscribers: llvm-commits, wdng
Differential Revision: https://reviews.llvm.org/D51145
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342081
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Zachary Turner [Wed, 12 Sep 2018 21:02:01 +0000 (21:02 +0000)]
[PDB] Emit old fpo data to the PDB file.
r342003 added support for emitting FPO data from the
DEBUG_S_FRAMEDATA subsection of the .debug$S section to the PDB
file. However, that is not the end of the story. FPO can end
up in two different destinations in a PDB, each corresponding to
a different FPO data source.
The case handled by r342003 involves copying data from the
DEBUG_S_FRAMEDATA subsection of the .debug$S section to the
"New FPO" stream in the PDB, which is then referred to by the
DBI stream. The case handled by this patch involves copying
records from the .debug$F section of an object file to the "FPO"
stream (or perhaps more aptly, the "Old FPO" stream) in the PDB
file, which is also referred to by the DBI stream.
The formats are largely similar, and the difference is mostly
only visible in masm generated object files, such as some of the
low-level CRT object files like memcpy. MASM doesn't appear to
support writing the DEBUG_S_FRAMEDATA subsection, and instead
just writes these records to the .debug$F section.
Although clang-cl does not emit a .debug$F section ever, lld still
needs to support it so we have good debugging for CRT functions.
Differential Revision: https://reviews.llvm.org/D51958
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342080
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Krzysztof Parzyszek [Wed, 12 Sep 2018 20:58:48 +0000 (20:58 +0000)]
[Hexagon] Use legalized type for extracted elements in scalarizeShuffle
Scalarization of a shuffle will break up the source vectors into individual
elements, and use them to assemble the resulting vector. An element type of
a legal vector type may not necessarily be a legal scalar type, so make
sure that the extracted values are extended to a legal scalar type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342079
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Konstantin Zhuravlyov [Wed, 12 Sep 2018 20:25:39 +0000 (20:25 +0000)]
AMDGPU: Print all kernel descriptor directives (including the ones with default values)
Change by Tony Tye
Differential Revision: https://reviews.llvm.org/D51954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342077
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Roman Lebedev [Wed, 12 Sep 2018 20:06:46 +0000 (20:06 +0000)]
[NFC][InstCombine] Drop newly-added interference-tests-for-high-bit-check.ll
Now that i have actually double-checked, no,
there is no such interference possible...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342076
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Roman Lebedev [Wed, 12 Sep 2018 19:44:26 +0000 (19:44 +0000)]
[NFC][InstCombine] R38708 - inefficient pattern for high-bits checking.
More complicated, canonical pattern:
https://rise4fun.com/Alive/uhA
https://godbolt.org/z/o4RB8D
Also, we need to be careful not to skip some patters...
https://bugs.llvm.org/show_bug.cgi?id=38708
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342074
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Konstantin Zhuravlyov [Wed, 12 Sep 2018 18:50:47 +0000 (18:50 +0000)]
AMDGPU: Re-apply r341982 after fixing the layering issue
Move isa version determination into TargetParser.
Also switch away from target features to CPU string when
determining isa version. This fixes an issue when we
output wrong isa version in the object code when features
of a particular CPU are altered (i.e. gfx902 w/o xnack
used to result in gfx900).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342069
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Roman Lebedev [Wed, 12 Sep 2018 18:19:43 +0000 (18:19 +0000)]
[InstCombine] Inefficient pattern for high-bits checking (PR38708)
Summary:
It is sometimes important to check that some newly-computed value
is non-negative and only `n` bits wide (where `n` is a variable.)
There are **many** ways to check that:
https://godbolt.org/z/o4RB8D
The last variant seems best?
(I'm sure there are some other variations i haven't thought of..)
Let's handle the second variant first, since it is much simpler.
https://rise4fun.com/Alive/LYjY
https://bugs.llvm.org/show_bug.cgi?id=38708
Reviewers: spatel, craig.topper, RKSimon
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D51985
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342067
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Julie Hockett [Wed, 12 Sep 2018 17:56:31 +0000 (17:56 +0000)]
[objcopy] make objcopy follow program header standards
Submitted on behalf of Armando Montanez (amontanez@google.com).
Objects with unused program headers copied by objcopy would always have
nonzero values for program header offset and program header entry size.
While technically valid, this atypical behavior triggers warnings in some
tools. This change sets the two fields to zero when the program header is
unused, better fitting the general expectations for unused program header
data.
Section headers behaved somewhat similarly (though only with the entry size),
and are fixed in this revision as well.
Differential Revision: https://reviews.llvm.org/D51961
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342065
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Thomas Lively [Wed, 12 Sep 2018 17:56:00 +0000 (17:56 +0000)]
[WebAssembly] SIMD comparisons
Summary:
Match the ordering semantics of non-vector comparisons. For
floating point comparisons that do not correspond to instructions, the
tests check that some vector comparison instruction was emitted but do
not care about the full implementation.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D51765
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342064
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Diogo N. Sampaio [Wed, 12 Sep 2018 16:24:43 +0000 (16:24 +0000)]
[ARM] Tighten f64<->f16 conversion requirements
Fix missing Requires fields.
Patch by Bernard Ogden (bogden)
Reviewers: SjoerdMeijer, javed.absar, t.p.northover
Reviewed By: t.p.northover
Differential Revision: https://reviews.llvm.org/D51631
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342061
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Craig Topper [Wed, 12 Sep 2018 15:47:34 +0000 (15:47 +0000)]
[X86] Remove isel patterns for ADCX instruction
There's no advantage to this instruction unless you need to avoid touching other flag bits. It's encoding is longer, it can't fold an immediate, it doesn't write all the flags.
I don't think gcc will generate this instruction either.
Fixes PR38852.
Differential Revision: https://reviews.llvm.org/D51754
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342059
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Florian Hahn [Wed, 12 Sep 2018 14:52:38 +0000 (14:52 +0000)]
[PatternMatch] Use generic One,Two,ThreeOps_match classes (NFC).
Currently we have a few duplicated matcher classes, which all do pretty
much the same thing. This patch introduces generic
One,Tow,ThreeOps_match classes which take the opcode the match as
template argument.
Reviewers: SjoerdMeijer, dneilson, spatel, arsenm
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D51044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342058
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Wolfgang Pieb [Wed, 12 Sep 2018 14:40:04 +0000 (14:40 +0000)]
Reverting r342048, which caused UBSan failures in dsymutil.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342056
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Alexandros Lamprineas [Wed, 12 Sep 2018 14:28:23 +0000 (14:28 +0000)]
[GVNHoist] computeInsertionPoints() miscalculates IDF
Fix for https://bugs.llvm.org/show_bug.cgi?id=38912.
In GVNHoist::computeInsertionPoints() we iterate over the Value
Numbers and calculate the Iterated Dominance Frontiers without
clearing the IDFBlocks vector first. IDFBlocks ends up accumulating
an insane number of basic blocks, which bloats the compilation time
of SemaChecking.cpp with ubsan enabled.
Differential Revision: https://reviews.llvm.org/D51980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342055
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Roman Lebedev [Wed, 12 Sep 2018 14:11:37 +0000 (14:11 +0000)]
[NFC][InstCombine] R38708 - inefficient pattern for high-bits checking.
The simplest pattern for now:
https://rise4fun.com/Alive/LYjY
https://godbolt.org/z/o4RB8D
https://bugs.llvm.org/show_bug.cgi?id=38708
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342054
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Sander de Smalen [Wed, 12 Sep 2018 12:10:22 +0000 (12:10 +0000)]
[AArch64] Implement aarch64_vector_pcs codegen support.
This patch adds codegen support for the saving/restoring
V8-V23 for functions specified with the aarch64_vector_pcs
calling convention attribute, as added in patch D51477.
Reviewers: t.p.northover, gberry, thegameg, rengolin, javed.absar, MatzeB
Reviewed By: thegameg
Differential Revision: https://reviews.llvm.org/D51479
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342049
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Wolfgang Pieb [Wed, 12 Sep 2018 12:01:19 +0000 (12:01 +0000)]
[DWARF] Refactoring range list dumping to fold DWARF v4 functionality into v5 handling
Eliminating some duplication of rangelist dumping code at the expense of
some version-dependent code in dump and extract routines.
Reviewer: dblaikie, JDevlieghere, vleschuk
Differential revision: https://reviews.llvm.org/D51081
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342048
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Kristof Umann [Wed, 12 Sep 2018 11:20:15 +0000 (11:20 +0000)]
[ADT] Made numerous methods of ImmutableList const
Also added ImmutableList<T>::iterator::operator->.
Differential Revision: https://reviews.llvm.org/D51881
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342045
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David Green [Wed, 12 Sep 2018 10:19:10 +0000 (10:19 +0000)]
[CGP] Ensure splitgep gives deterministic output
The output of splitLargeGEPOffsets does not appear to be deterministic because
of the way that we iterate over a DenseMap. I've changed it to a MapVector for
consistent output.
The test here isn't particularly great, only showing a consmetic difference in
output. The original reproducer is much larger but show a diffierence in
instruction ordering, leading to different codegen.
Differential Revision: https://reviews.llvm.org/D51851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342043
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Sam Parker [Wed, 12 Sep 2018 09:58:56 +0000 (09:58 +0000)]
[ARM] Follow-up to rL342033
Fixed typo which can cause segfault.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342040
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David Green [Wed, 12 Sep 2018 09:54:17 +0000 (09:54 +0000)]
[SimplifyCFG] Put an alignment on generated switch tables
Previously the alignment on the newly created switch table data was not set,
meaning that DataLayout::getPreferredAlignment was free to overalign it to 16
bytes. This causes unnecessary code bloat.
Differential Revision: https://reviews.llvm.org/D51800
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342039
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Sander de Smalen [Wed, 12 Sep 2018 09:44:46 +0000 (09:44 +0000)]
[AArch64] NFC: Refactoring to prepare for vector PCS.
This patch refactors several parts of AArch64FrameLowering
so that it can be easily extended to support saving/restoring
of FPR128 (Q) registers.
Reviewers: t.p.northover, gberry, thegameg, rengolin, javed.absar
Reviewed By: thegameg
Differential Revision: https://reviews.llvm.org/D51478
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342038
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Clement Courbet [Wed, 12 Sep 2018 09:26:32 +0000 (09:26 +0000)]
[llvm-exegesis][NFC]Remove dead function parameter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342035
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Sam Parker [Wed, 12 Sep 2018 09:17:44 +0000 (09:17 +0000)]
[ARM] Exchange MAC operands in ARMParallelDSP
SMLAD and SMLALD instructions also come in the form of SMLADX and
SMLALDX which perform an exchange on their second operand. To support
this, more of the loads in the MAC candidates are compared for
sequential access and a boolean value has been added to BinOpChain.
AddMACCandiate has been refactored into a small pattern matching
state machine to reduce the amount of duplicated code, but also to
enable the matching to be more flexible. CreateParallelMACPairs now
iterates through all the candidates to find parallel ones.
Differential Revision: https://reviews.llvm.org/D51424
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342033
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Sam Parker [Wed, 12 Sep 2018 09:11:48 +0000 (09:11 +0000)]
[ARM] Allow bitcasts in ARMCodeGenPrepare
Allow bitcasts in the use-def chains, treating them as sources.
Differential Revision: https://reviews.llvm.org/D50758
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342032
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Sander de Smalen [Wed, 12 Sep 2018 08:54:06 +0000 (08:54 +0000)]
[AArch64] Add parsing of aarch64_vector_pcs attribute.
This patch adds parsing support for the 'aarch64_vector_pcs'
calling convention attribute to calls and function declarations.
More information describing the vector ABI and procedure call standard
can be found here:
https://developer.arm.com/products/software-development-tools/\
hpc/arm-compiler-for-hpc/vector-function-abi
Reviewers: t.p.northover, rnk, rengolin, javed.absar, thegameg, SjoerdMeijer
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D51477
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342030
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Florian Hahn [Wed, 12 Sep 2018 08:01:57 +0000 (08:01 +0000)]
[LV] Move InterleaveGroup and InterleavedAccessInfo to VectorUtils.h (NFC)
Move the 2 classes out of LoopVectorize.cpp to make it easier to re-use
them for VPlan outside LoopVectorize.cpp
Reviewers: Ayal, mssimpso, rengolin, dcaballe, mkuper, hsaito, hfinkel, xbolva00
Reviewed By: rengolin, xbolva00
Differential Revision: https://reviews.llvm.org/D49488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342027
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Ilya Biryukov [Wed, 12 Sep 2018 07:22:46 +0000 (07:22 +0000)]
Remove unused include from IVDescriptors.cpp.
This fixes a layering violation:
Analysis/IVDescrtors.cpp can't include Transforms/Utils/BasicBlockUtils.h,
since TransformUtils depends on Analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342024
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Ilya Biryukov [Wed, 12 Sep 2018 07:05:30 +0000 (07:05 +0000)]
Revert "AMDGPU: Move isa version and EF_AMDGPU_MACH_* determination into TargetParser."
This reverts commit r341982.
The change introduced a layering violation. Reverting to unbreak
our integrate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342023
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Craig Topper [Wed, 12 Sep 2018 05:25:41 +0000 (05:25 +0000)]
[SelectionDAG] Remove some code from PromoteIntOp_MGATHER that handles UpdateNodeOperands returning an existing node instead of updating.
I suspect this became unecessary when the CSE of mgather was fixed in r338080. It may still be possible to hit this if we widen the element type of a gather outside of type legalization and the promote the mask of a separate gather node so they become the same. But that seems pretty unlikely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342022
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Vikram TV [Wed, 12 Sep 2018 01:59:43 +0000 (01:59 +0000)]
Break LoopUtils into an Analysis file.
Summary:
The InductionDescriptor and RecurrenceDescriptor classes basically analyze the IR to identify the respective IVs. So, it is better to have them in the "Analysis" directory instead of the "Transforms" directory.
The rationale for this is to make the Induction and Recurrence descriptor classes available for analysis passes. Currently including them in an analysis pass produces link error (http://lists.llvm.org/pipermail/llvm-dev/2018-July/124456.html).
Induction and Recurrence descriptors are moved from Transforms/Utils/LoopUtils.h|cpp to Analysis/IVDescriptors.h|cpp.
Reviewers: dmgreen, llvm-commits, hfinkel
Reviewed By: dmgreen
Subscribers: mgorny
Differential Revision: https://reviews.llvm.org/D51153
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342016
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Craig Topper [Wed, 12 Sep 2018 01:57:22 +0000 (01:57 +0000)]
[X86] Teach X86SelectionDAGInfo::EmitTargetCodeForMemcpy about GNUX32
Summary:
In GNUX23, is64BitMode returns true, but pointers are 32-bits. So we shouldn't copy pointer values into RSI/RDI since the widths don't match.
Fixes PR38865 despite what the title says. I think the llvm_unreachable in the copyPhysReg code tricked the optimizer and made the fatal error trigger.
Reviewers: rnk, efriedma, MatzeB, echristo
Reviewed By: efriedma
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D51893
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342015
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Lang Hames [Wed, 12 Sep 2018 00:35:03 +0000 (00:35 +0000)]
[ORC] Remove some unused typedefs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342013
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Jessica Paquette [Tue, 11 Sep 2018 23:05:34 +0000 (23:05 +0000)]
[MachineOutliner] Add codegen size remarks to the MachineOutliner
Since the outliner is a module pass, it doesn't get codegen size remarks like
the other codegen passes do. This adds size remarks *to* the outliner.
This is kind of a workaround, so it's peppered with FIXMEs; size remarks
really ought to not ever be handled by the pass itself. However, since the
outliner is the only "MachineModulePass", this works for now. Since the
entire purpose of the MachineOutliner is to produce code size savings, it
really ought to be included in codgen size remarks.
If we ever go ahead and make a MachineModulePass (say, something similar to
MachineFunctionPass), then all of this ought to be moved there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342009
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Sanjay Patel [Tue, 11 Sep 2018 22:40:20 +0000 (22:40 +0000)]
[InstCombine] add folds for unsigned-overflow compares
Name: op_ugt_sum
%a = add i8 %x, %y
%r = icmp ugt i8 %x, %a
=>
%notx = xor i8 %x, -1
%r = icmp ugt i8 %y, %notx
Name: sum_ult_op
%a = add i8 %x, %y
%r = icmp ult i8 %a, %x
=>
%notx = xor i8 %x, -1
%r = icmp ugt i8 %y, %notx
https://rise4fun.com/Alive/ZRxI
AFAICT, this doesn't interfere with any add-saturation patterns
because those have >1 use for the 'add'. But this should be
better for IR analysis and codegen in the basic cases.
This is another fold inspired by PR14613:
https://bugs.llvm.org/show_bug.cgi?id=14613
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342004
91177308-0d34-0410-b5e6-
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Zachary Turner [Tue, 11 Sep 2018 22:35:01 +0000 (22:35 +0000)]
[PDB] Write FPO Data to the PDB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342003
91177308-0d34-0410-b5e6-
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Reid Kleckner [Tue, 11 Sep 2018 22:25:13 +0000 (22:25 +0000)]
[cmake] Speed up check-llvm 5x by delay loading shell32 and ole32
Summary:
Previously, check-llvm on my Windows 10 workstation took about 300s to
run, and it would lock up my mouse. Now, it takes just under 60s.
Previously running the tests only used about 15% of the available CPU
time, now it uses up to 60%.
Shell32.dll and ole32.dll have direct dependencies on user32.dll and
gdi32.dll. These DLLs are mostly used to for Windows GUI functionality,
which most LLVM tools don't need. It seems that these DLLs acquire and
release some system resources on startup and exit, and that requires
acquiring the same highly contended lock discussed in this post:
https://randomascii.wordpress.com/2017/07/09/24-core-cpu-and-i-cant-move-my-mouse/
Most LLVM tools still have a transitive dependency on
SHGetKnownFolderPathW, which is used to look up the user home directory
and local AppData directory. We also use SHFileOperationW to recursively
delete a directory, but only LLDB and clang-doc use this today. At some
point, we might consider removing these last shell32.dll deps, but for
now, I would like to take this free performance.
Many thanks to Bruce Dawson for suggesting this fix. He looked at an ETW
trace of an LLVM test run, noticed these DLLs, and suggested avoiding
them.
Reviewers: zturner, pcc, thakis
Subscribers: mgorny, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D51952
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342002
91177308-0d34-0410-b5e6-
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Alexandros Lamprineas [Tue, 11 Sep 2018 22:10:57 +0000 (22:10 +0000)]
Revert "[GVNHoist] Re-enable GVNHoist by default"
This reverts rL341954.
The builder `sanitizer-x86_64-linux-bootstrap-ubsan` has been
failing with timeouts at stage2 clang/ubsan:
[3065/3073] Linking CXX executable bin/lld
command timed out: 1200 seconds without output running python
../sanitizer_buildbot/sanitizers/buildbot_selector.py,
attempting to kill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342001
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Reid Kleckner [Tue, 11 Sep 2018 22:02:31 +0000 (22:02 +0000)]
Apply local fixes intended to be part of r341999.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342000
91177308-0d34-0410-b5e6-
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Reid Kleckner [Tue, 11 Sep 2018 22:00:50 +0000 (22:00 +0000)]
[codeview] Decode and dump FP regs from S_FRAMEPROC records
Summary:
There are two registers encoded in the S_FRAMEPROC flags: one for locals
and one for parameters. The encoding is described by the
ExpandEncodedBasePointerReg function in cvinfo.h. Two bits are used to
indicate one of four possible values:
0: no register - Used when there are no variables.
1: SP / standard - Variables are stored relative to the standard SP
for the ISA.
2: FP - Variables are addressed relative to the ISA frame
pointer, i.e. EBP on x86. If realignment is required, parameters
use this. If a dynamic alloca is used, locals will be EBP relative.
3: Alternative - Variables are stored relative to some alternative
third callee-saved register. This is required to address highly
aligned locals when there are dynamic stack adjustments. In this
case, both the incoming SP saved in the standard FP and the current
SP are at some dynamic offset from the locals. LLVM uses ESI in
this case, MSVC uses EBX.
Most of the changes in this patch are to pass around the CPU so that we
can decode these into real, named architectural registers.
Subscribers: hiraditya
Differential Revision: https://reviews.llvm.org/D51894
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341999
91177308-0d34-0410-b5e6-
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Alexander Shaposhnikov [Tue, 11 Sep 2018 22:00:47 +0000 (22:00 +0000)]
[object] Improve the performance of getSymbols used by ArchiveWriter
In this diff we adjust the code of getSymbols to avoid creating LLVMContext when it's not necessary.
Without this patch when the function getSymbols was called on a MachO object with a __bitcode section
it was parsing the embedded bitcode and then ignoring the result.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D51759
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341998
91177308-0d34-0410-b5e6-
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Sanjay Patel [Tue, 11 Sep 2018 22:00:15 +0000 (22:00 +0000)]
[InstCombine] add folds for icmp with xor mask constant
These are the folds in Alive;
Name: xor_ult
Pre: isPowerOf2(-C1)
%xor = xor i8 %x, C1
%r = icmp ult i8 %xor, C1
=>
%r = icmp ugt i8 %x, ~C1
Name: xor_ugt
Pre: isPowerOf2(C1+1)
%xor = xor i8 %x, C1
%r = icmp ugt i8 %xor, C1
=>
%r = icmp ugt i8 %x, C1
https://rise4fun.com/Alive/Vty
The ugt case in its simplest form was already handled by DemandedBits,
but that's not ideal as shown in the multi-use test.
I'm not sure if these are all of the symmetrical folds, but I adjusted
the existing code for one of the folds to try to show the similarities.
There's no obvious connection, but this is another preliminary step
for PR14613...
https://bugs.llvm.org/show_bug.cgi?id=14613
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341997
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Michael Berg [Tue, 11 Sep 2018 21:35:32 +0000 (21:35 +0000)]
add IR flags to MI
Summary: Initial support for nsw, nuw and exact flags in MI
Reviewers: spatel, hfinkel, wristow
Reviewed By: spatel
Subscribers: nlopes
Differential Revision: https://reviews.llvm.org/D51738
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341996
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Matt Morehouse [Tue, 11 Sep 2018 21:15:41 +0000 (21:15 +0000)]
Revert "[SanitizerCoverage] Create comdat for global arrays."
This reverts r341987 since it will cause trouble when there's a module
ID collision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341995
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Sanjay Patel [Tue, 11 Sep 2018 21:13:20 +0000 (21:13 +0000)]
[InstCombine] add tests for icmp with xor; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341993
91177308-0d34-0410-b5e6-
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Reid Kleckner [Tue, 11 Sep 2018 21:02:03 +0000 (21:02 +0000)]
[Support] Quote arguments containing \n on Windows
Fixes at_file.c test failure caused by r341988. We may want to change
how we treat \n in our tokenizer, but this is probably a good fix
regardless, since we can invoke all kinds of programs with different
interpretations of the command line quoting rules.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341992
91177308-0d34-0410-b5e6-
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Reid Kleckner [Tue, 11 Sep 2018 20:22:39 +0000 (20:22 +0000)]
[Support] Avoid calling CommandLineToArgvW from shell32.dll
Summary:
Shell32.dll depends on gdi32.dll and user32.dll, which are mostly DLLs
for Windows GUI functionality. LLVM's utilities don't typically need GUI
functionality, and loading these DLLs seems to be slowing down startup.
Also, we already have an implementation of Windows command line
tokenization in cl::TokenizeWindowsCommandLine, so we can just use it.
The goal is to get the original argv in UTF-8, so that it can pass
through most LLVM string APIs. A Windows process starts life with a
UTF-16 string for its command line, and it can be retreived with
GetCommandLineW from kernel32.dll.
Previously, we would:
1. Get the wide command line
2. Call CommandLineToArgvW to handle quoting rules and separate it into
arguments.
3. For each wide argument, expand wildcards (* and ?) using
FindFirstFileW.
4. Convert each argument to UTF-8
Now we:
1. Get the wide command line, convert the whole thing to UTF-8
2. Tokenize the UTF-8 command line with cl::TokenizeWindowsCommandLine
3. For each argument, expand wildcards if present
- This requires converting back to UTF-16 to call FindFirstFileW
- Results of FindFirstFileW must be converted back to UTF-8
Reviewers: zturner
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D51941
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341988
91177308-0d34-0410-b5e6-
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Matt Morehouse [Tue, 11 Sep 2018 20:10:40 +0000 (20:10 +0000)]
[SanitizerCoverage] Create comdat for global arrays.
Summary:
Place global arrays in comdat sections with their associated functions.
This makes sure they are stripped along with the functions they
reference, even on the BFD linker.
Reviewers: eugenis
Reviewed By: eugenis
Subscribers: eraman, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D51902
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341987
91177308-0d34-0410-b5e6-
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Alina Sbirlea [Tue, 11 Sep 2018 19:19:21 +0000 (19:19 +0000)]
Update MemorySSA in LoopUnswitch.
Summary:
Update MemorySSA in old LoopUnswitch pass.
Actual dependency and update is disabled by default.
Subscribers: sanjoy, jlebar, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D45301
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341984
91177308-0d34-0410-b5e6-
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Konstantin Zhuravlyov [Tue, 11 Sep 2018 18:56:51 +0000 (18:56 +0000)]
AMDGPU: Move isa version and EF_AMDGPU_MACH_* determination
into TargetParser.
Also switch away from target features to CPU string when
determining isa version. This fixes an issue when we
output wrong isa version in the object code when features
of a particular CPU are altered (i.e. gfx902 w/o xnack
used to result in gfx900).
Differential Revision: https://reviews.llvm.org/D51890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341982
91177308-0d34-0410-b5e6-
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Sanjay Patel [Tue, 11 Sep 2018 18:49:00 +0000 (18:49 +0000)]
[InstCombine] enhance vector demanded elements to look at a vector select condition operand
I noticed that we were not back-propagating undef lanes to shuffle masks when we have a
shuffle that reduces the vector width. This is part of investigating/solving PR38691:
https://bugs.llvm.org/show_bug.cgi?id=38691
The DAG equivalent was proposed with:
D51696
Differential Revision: https://reviews.llvm.org/D51433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341981
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Matt Davis [Tue, 11 Sep 2018 18:47:48 +0000 (18:47 +0000)]
[llvm-mca] Delay calculation of Cycles per Resources, separate the cycles and resource quantities.
Summary:
This patch removes the storing of accumulated floating point data
within the llvm-mca library.
This patch splits-up the two quantities: cycles and number of resource units.
By splitting-up these two quantities, we delay the calculation of "cycles per resource unit"
until that value is read, reducing the chance of accumulating floating point error.
I considered using the APFloat, but after measuring performance, for a large (many iteration)
sample, I decided to go with this faster solution.
Reviewers: andreadb, courbet, RKSimon
Reviewed By: andreadb
Subscribers: llvm-commits, javed.absar, tschuett, gbedwell
Differential Revision: https://reviews.llvm.org/D51903
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341980
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Sanjay Patel [Tue, 11 Sep 2018 18:45:28 +0000 (18:45 +0000)]
[InstCombine] add tests for add-with-overflow compares; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341979
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Vedant Kumar [Tue, 11 Sep 2018 18:38:34 +0000 (18:38 +0000)]
[gcov] Fix branch counters with switch statements (fix PR38821)
Right now, the counters are added in regards of the number of successors
for a given BasicBlock: it's good when we've only 1 or 2 successors (at
least with BranchInstr). But in the case of a switch statement, the
BasicBlock after switch has several predecessors and we need know from
which BB we're coming from.
So the idea is to revert what we're doing: add a PHINode in each block
which will select the counter according to the incoming BB. They're
several pros for doing that:
- we fix the "switch" bug
- we remove the function call to "__llvm_gcov_indirect_counter_increment"
and the lookup table stuff
- we replace by PHINodes, so the optimizer will probably makes a better
job.
Patch by calixte!
Differential Revision: https://reviews.llvm.org/D51619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341977
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Xin Tong [Tue, 11 Sep 2018 18:06:03 +0000 (18:06 +0000)]
Add some context to fatal verifier errors
Summary: Add function name when verification fails as an initial breadcrumb for debugging.
Patch by David Callahan.
Reviewers: mehdi_amini, modocache
Reviewed By: modocache
Subscribers: llvm-commits, modocache
Differential Revision: https://reviews.llvm.org/D51386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341974
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Craig Topper [Tue, 11 Sep 2018 17:57:27 +0000 (17:57 +0000)]
[X86] Prefer unpckhpd over movhlps in isel for fake unary cases
In r337348, I changed lowering to prefer X86ISD::UNPCKL/UNPCKH opcodes over MOVLHPS/MOVHLPS for v2f64 {0,0} and {1,1} shuffles when we have SSE2. This enabled the removal of a bunch of weirdly bitcasted isel patterns in r337349. To avoid changing the tests I placed a gross hack in isel to still emit movhlps instructions for fake unary unpckh nodes. A similar hack was not needed for unpckl and movlhps because we do execution domain switching for those. But unpckh and movhlps have swapped operand order.
This patch removes the hack.
This is a code size increase since unpckhpd requires a 0x66 prefix and movhlps does not. But if that's a big concern we should be using movhlps for all unpckhpd opcodes and let commuteInstruction turnit into unpckhpd when its an advantage.
Differential Revision: https://reviews.llvm.org/D49499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341973
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 11 Sep 2018 17:57:23 +0000 (17:57 +0000)]
[X86] Teach X86FastISel::X86SelectRet to use EAX for the sret pointer in GNUX32
GNUX32 uses 32-bit pointers despite is64BitMode being true. So we should use EAX to return the value.
Fixes ones of the failures from PR38865.
Differential Revision: https://reviews.llvm.org/D51940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341972
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 11 Sep 2018 17:57:20 +0000 (17:57 +0000)]
[InstCombine] Fix incorrect usage of getPrimitiveSizeInBits when we should be using the element size for vectors
For vectors, getPrimitiveSizeInBits returns the full vector width. This code should using the element size for vectors. This could be fixed by calling getScalarSizeInBits, but its even easier to just get it from the APInt we're checking.
Differential Revision: https://reviews.llvm.org/D51938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341971
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Florian Hahn [Tue, 11 Sep 2018 17:55:58 +0000 (17:55 +0000)]
[CallSiteSplitting] Add debug location to created PHI nodes.
There are 2 cases when we create PHI nodes:
* For the result of the call that was duplicated in the split blocks.
Those PHI nodes should have the debug location of the call.
* For values produced before the call. Those instructions need to be
duplicated in the split blocks and the PHI nodes should have the
debug locations of those instructions.
Fixes PR37962.
Reviewers: junbuml, gbedwell, vsk
Reviewed By: junbuml
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D51919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341970
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Josh Stone [Tue, 11 Sep 2018 17:52:01 +0000 (17:52 +0000)]
[GlobalISel] Lower dbg.declare into indirect DBG_VALUE
Summary:
D31439 changed the semantics of dbg.declare to take the address of a
variable as the first argument, making it indirect. It specifically
updated FastISel for this change here:
https://reviews.llvm.org/D31439#change-WVArzi177jPl
GlobalISel needs to follow suit, or else it will be missing a level of
indirection in the generated debuginfo. This problem was seen in a Rust
debuginfo test on aarch64, since GlobalISel is used at -O0 for aarch64.
https://github.com/rust-lang/rust/issues/49807
https://bugzilla.redhat.com/show_bug.cgi?id=
1611597
https://bugzilla.redhat.com/show_bug.cgi?id=
1625768
Reviewers: dblaikie, aprantl, t.p.northover, javed.absar, rnk
Reviewed By: rnk
Subscribers: #debug-info, rovka, kristof.beyls, JDevlieghere, llvm-commits, tstellar
Differential Revision: https://reviews.llvm.org/D51749
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341969
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Johannes Doerfert [Tue, 11 Sep 2018 17:49:43 +0000 (17:49 +0000)]
[LoopInfo][FIX] Remove leftover dump in unit test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341968
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Josh Stone [Tue, 11 Sep 2018 17:28:43 +0000 (17:28 +0000)]
Test commit: remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341966
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Matt Morehouse [Tue, 11 Sep 2018 17:20:14 +0000 (17:20 +0000)]
Revert "[SanitizerCoverage] Create comdat for global arrays."
This reverts r341951 due to bot breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341965
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Craig Topper [Tue, 11 Sep 2018 16:51:26 +0000 (16:51 +0000)]
[InstCombine] Use dyn_cast instead of match(m_Constant). NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341962
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 11 Sep 2018 16:51:24 +0000 (16:51 +0000)]
[InstCombine] Support (mul (sext x), cst) --> (sext (mul x, cst')) and (mul (zext x), cst) --> (zext (mul x, cst')) for vectors constants.
Similar to D51236, but for mul instead of add.
Differential Revision: https://reviews.llvm.org/D51900
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341961
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Jessica Paquette [Tue, 11 Sep 2018 16:38:46 +0000 (16:38 +0000)]
[NFC] Fix typo in comment
Fore -> For
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341960
91177308-0d34-0410-b5e6-
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Jessica Paquette [Tue, 11 Sep 2018 16:33:46 +0000 (16:33 +0000)]
[MachineOutliner][NFC] Factor out instruction mapping into its own function
Just some tidy-up. Pull the mapper stuff into `populateMapper`. This makes it
a bit easier to read what's going on in `runOnModule`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341959
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 11 Sep 2018 16:05:03 +0000 (16:05 +0000)]
[X86] Correct the one use check from r341915.
The one use check should be on the bitcast, not the input to the bitcast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341956
91177308-0d34-0410-b5e6-
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Alexandros Lamprineas [Tue, 11 Sep 2018 15:55:45 +0000 (15:55 +0000)]
[GVNHoist] Re-enable GVNHoist by default
Rebase rL340922 since https://bugs.llvm.org/show_bug.cgi?id=38807
has been fixed by rL341947.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341954
91177308-0d34-0410-b5e6-
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Roman Lebedev [Tue, 11 Sep 2018 15:34:26 +0000 (15:34 +0000)]
[DagCombine][NFC] Some more tests fo for X % C == 0 (UREM case) transform
For https://reviews.llvm.org/D50222
Patch by: hermord (Dmytro Shynkevych)!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341953
91177308-0d34-0410-b5e6-
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Simon Atanasyan [Tue, 11 Sep 2018 15:32:47 +0000 (15:32 +0000)]
[MIPS] Fix illegal type assert in single-float mode
An fp_to_sint node would be incorrectly lowered to a TruncIntFP node in
single-float mode. This would trigger an "Unexpected illegal type!"
assert.
Patch by Dan Ravensloft.
Differential revision: https://reviews.llvm.org/D51810
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341952
91177308-0d34-0410-b5e6-
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Matt Morehouse [Tue, 11 Sep 2018 15:23:14 +0000 (15:23 +0000)]
[SanitizerCoverage] Create comdat for global arrays.
Summary:
Place global arrays in comdat sections with their associated functions.
This makes sure they are stripped along with the functions they
reference, even on the BFD linker.
Reviewers: eugenis
Reviewed By: eugenis
Subscribers: eraman, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D51902
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341951
91177308-0d34-0410-b5e6-
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Alexandros Lamprineas [Tue, 11 Sep 2018 14:29:59 +0000 (14:29 +0000)]
[MemorySSAUpdater] Avoid creating self-referencing MemoryDefs
Fix for https://bugs.llvm.org/show_bug.cgi?id=38807, which occurred
while compiling SemaTemplateInstantiate.cpp with clang and GVNHoist
enabled. In the following example:
1=def(entry)
/ \
2=def(1) 4=def(1)
3=def(2) 5=def(4)
When removing the MemoryDef 2=def(1) from its basic block, and just
before adding it to the end of the parent basic block, we first
replace all its uses with the defining memory access:
3=def(2) -> 3=def(1)
Then we call insertDef for adding 2=def(1) to the parent basic block,
where we replace the uses of 1=def(entry) with 2=def(1). Doing so we
create a self reference:
2=def(1) -> 2=def(2) (bad)
3=def(1) -> 3=def(2) (ok)
4=def(1) -> 4=def(2) (ok)
Differential Revision: https://reviews.llvm.org/D51801
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341947
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Nico Weber [Tue, 11 Sep 2018 14:11:52 +0000 (14:11 +0000)]
pdb output: Initialize padding in PublicsStreamHeader.
Makes the produced pdbs more deterministic; before they'd contain 2 arbitary
bytes where this padding was.
Also reorder initialization to match the order of the fields in the struct (nfc)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341945
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Nico Weber [Tue, 11 Sep 2018 14:10:33 +0000 (14:10 +0000)]
Make malformed-machos.test pass on my Mac.
For some reason, llvm-objdump defaults to -arch=i386 on this system while
the test checks x86_64 output. Explicitly pass -arch=x86_64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341944
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Roman Lebedev [Tue, 11 Sep 2018 14:06:14 +0000 (14:06 +0000)]
[Hexagon] [Test] Remove undef and infinite loop from test
Summary:
The undef and the infinite loop at the end cause this test to be translated
unpredictably. In particular, the checked-for `mpy` disappears under
certain legal optimizations (e.g. the one in D50222).
Since the use of these constructs is not relevant to the behavior tested,
according to the header comment, this change, suggested by @kparzysz,
eliminates them.
Was initially committed in r341046, but was reverted.
Patch by: hermord (Dmytro Shynkevych)!
Reviewers: kparzysz
Reviewed By: kparzysz
Subscribers: lebedev.ri, llvm-commits, kparzysz
Differential Revision: https://reviews.llvm.org/D50944
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341943
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Sam Parker [Tue, 11 Sep 2018 14:01:22 +0000 (14:01 +0000)]
[ARM] Add smlald support in ARMParallelDSP
Search from i64 reducing phis, as well as i32, to allow the
generation of smlald instructions.
Differential Revision: https://reviews.llvm.org/D51101
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341941
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Sanjay Patel [Tue, 11 Sep 2018 13:21:28 +0000 (13:21 +0000)]
[AArch64] test codegen for unsigned saturated add; NFC
This is identical to the tests added for x86 at rL341845.
A semi-generic DAGCombine should improve things universally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341935
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Petar Jovanovic [Tue, 11 Sep 2018 13:10:04 +0000 (13:10 +0000)]
[MIPS] ORC JIT support
This patch adds support for ORC JIT for mips/mips64 architecture.
In common code $static is changed to __ORCstatic because on MIPS
architecture "$" is a reserved character.
Patch by Luka Ercegovcevic
Differential Revision: https://reviews.llvm.org/D49665
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341934
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Sam Parker [Tue, 11 Sep 2018 12:45:43 +0000 (12:45 +0000)]
[ARM] Enable ARMCodeGenPrepare by default
We've had the pass enabled downstream for a couple of weeks and it
seems to be okay, so enable it by default.
Differential Revision: https://reviews.llvm.org/D51920
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341932
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Alexander Timofeev [Tue, 11 Sep 2018 11:56:50 +0000 (11:56 +0000)]
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
Differential revision: https://reviews.llvm.org/D51734
Reviewers: rampitec
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341928
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Johannes Doerfert [Tue, 11 Sep 2018 11:51:29 +0000 (11:51 +0000)]
[FuncAttrs] Remove "access range attributes" for read-none functions
The presence of readnone and an access range attribute (argmemonly,
inaccessiblememonly, inaccessiblemem_or_argmemonly) is considered an
error by the verifier. This seems strict but also not wrong. This
patch makes sure function attribute detection will remove all access
range attributes for readnone functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341927
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Johannes Doerfert [Tue, 11 Sep 2018 11:44:17 +0000 (11:44 +0000)]
[LoopInfo] Fix Loop::getLoopID() for loops with multiple latches
The previous implementation traversed all loop blocks and bailed if one
was not a latch block. Since we are only interested in latch blocks, we
should only traverse those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341926
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Simon Atanasyan [Tue, 11 Sep 2018 09:57:25 +0000 (09:57 +0000)]
[mips] Add a pattern for 64-bit GPR variant of the `rdhwr` instruction
MIPS ISAs start to support third operand for the `rdhwr` instruction
starting from Revision 6. But LLVM generates assembler code with
three-operands version of this instruction on any MIPS64 ISA. The third
operand is always zero, so in case of direct code generation we get
correct code.
This patch fixes the bug by adding an instruction alias. The same alias
already exists for 32-bit ISA.
Ideally, we also need to reject three-operands version of the `rdhwr`
instruction in an assembler code if ISA revision is less than 6. That is
a task for a separate patch.
This fixes PR38861 (https://bugs.llvm.org/show_bug.cgi?id=38861)
Differential revision: https://reviews.llvm.org/D51773
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341919
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Max Kazantsev [Tue, 11 Sep 2018 08:46:19 +0000 (08:46 +0000)]
[NFC] Sanitizing asserts for OrderedBasicBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341917
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Craig Topper [Tue, 11 Sep 2018 08:20:02 +0000 (08:20 +0000)]
[X86] In combineMOVMSK, look through int->fp bitcasts before callling SimplifyDemandedBits.
MOVMSKPS and MOVMSKPD both take FP types, but likely the operations before it are on integer types with just a int->fp bitcast between them. If the bitcast isn't used by anything else and doesn't change the element width we can look through it to simplify the integer ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341915
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Dean Michael Berris [Tue, 11 Sep 2018 08:03:30 +0000 (08:03 +0000)]
[XRay] Ensure lambda outlives llvm::function_ref
Follow-up to D51912.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341912
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Dean Michael Berris [Tue, 11 Sep 2018 07:27:59 +0000 (07:27 +0000)]
[XRay] Write the TSC along with CPUID
Fixes builds in non-little-endian systems.
This is a follow-up to D51911.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341909
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Craig Topper [Tue, 11 Sep 2018 07:23:29 +0000 (07:23 +0000)]
[X86] Add test cases inspired by PR38840.
These are test cases inspired by sequences like below for extracting the same bit from every vector element and checking for all zeros/ones.
define i1 @and256_x8(<8 x i32>) {
%a = trunc <8 x i32> %0 to <8 x i1>
%b = bitcast <8 x i1> %a to i8
%d = icmp eq i8 %b, -1
ret i1 %d
}
This is what the above looks like after InstCombine.
define i1 @and256_x8_opt(<8 x i32>) {
%2 = and <8 x i32> %0, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%a = icmp ne <8 x i32> %2, zeroinitializer
%b = bitcast <8 x i1> %a to i8
%d = icmp eq i8 %b, -1
ret i1 %d
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341908
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Dean Michael Berris [Tue, 11 Sep 2018 06:45:59 +0000 (06:45 +0000)]
[XRay] Use FDR Records+Visitors for Trace Loading
Summary:
In this change, we overhaul the implementation for loading
`llvm::xray::Trace` objects from files by using the combination of
specific FDR Record types and visitors breaking up the logic to
reconstitute an execution trace from flight-data recorder mode traces.
This change allows us to handle out-of-temporal order blocks as written
in files, and more consistently recreate an execution trace spanning
multiple blocks and threads. To do this, we use the `WallclockRecord`
associated with each block to maintain temporal order of blocks, before
attempting to recreate an execution trace.
The new addition in this change is the `TraceExpander` type which can be
thought of as a decompression/decoding routine. This allows us to
maintain the state of an execution environment (thread+process) and
create `XRayRecord` instances that fit nicely into the `Trace`
container. We don't have a specific unit test for the TraceExpander
type, since the end-to-end tests for the `llvm-xray convert` tools
already cover precisely this codepath.
This change completes the refactoring started with D50441.
Depends on D51911.
Reviewers: mboerger, eizan
Subscribers: mgorny, hiraditya, mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D51912
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341906
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Dean Michael Berris [Tue, 11 Sep 2018 06:36:51 +0000 (06:36 +0000)]
[XRay] Add TSC to NewCPUId Records
Summary:
This more correctly reflects the data written by the FDR mode runtime.
This is a continuation of the work in D50441.
Reviewers: mboerger, eizan
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D51911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341905
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Max Kazantsev [Tue, 11 Sep 2018 06:34:43 +0000 (06:34 +0000)]
[NFC] Specify test's option to reduce reliance on defaults
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341904
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Max Kazantsev [Tue, 11 Sep 2018 05:10:01 +0000 (05:10 +0000)]
[NFC] Rename variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341901
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