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Sanjay Patel [Fri, 26 Oct 2018 14:58:13 +0000 (14:58 +0000)]
[x86] commute blendvb with constant condition op to allow load folding
This is a narrow fix for 1 of the problems mentioned in PR27780:
https://bugs.llvm.org/show_bug.cgi?id=27780
I looked at more general solutions, but it's a mess. We canonicalize shuffle masks
based on the number of elements accessed from each operand, and that's not optional.
If you remove that, we'll crash because we fail to match isel patterns. So I'm
waiting until we're sure that we have blendvb with constant condition and then
commuting based on the load potential. Other cases like blend-with-immediate are
already handled elsewhere, so this is probably not a common problem anyway.
I didn't use "MayFoldLoad" because that checks for one-use and in these cases, we've
screwed that up by creating a temporary PSHUFB using these operands that we're counting
on to be killed later. Undoing that didn't look like a simple task because it's
intertwined with determining if we actually use both operands of the shuffle or not.a
Differential Revision: https://reviews.llvm.org/D53737
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345390
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Simon Pilgrim [Fri, 26 Oct 2018 14:39:28 +0000 (14:39 +0000)]
[X86] Use existing pulled out VT variables. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345388
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Max Kazantsev [Fri, 26 Oct 2018 14:20:11 +0000 (14:20 +0000)]
[SimpleLoopUnswitch] Unswitch by experimental.guard intrinsics
This patch adds support of `llvm.experimental.guard` intrinsics to non-trivial
simple loop unswitching. These intrinsics represent implicit control flow which
has pretty much the same semantics as usual conditional branches. The
algorithm of dealing with them is following:
- Consider guards as unswitching candidates;
- If a guard is considered the best candidate, turn it into a branch;
- Apply normal unswitching algorithm on this branch.
The patch has no compile time effect on code that does not contain any guards.
Differential Revision: https://reviews.llvm.org/D53744
Reviewed By: chandlerc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345387
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Sjoerd Meijer [Fri, 26 Oct 2018 14:19:57 +0000 (14:19 +0000)]
[ARM] Fix ARMCodeGenPrepare test cases
While working on FileCheck producing better diagnostics in D53710, I noticed
that our test case is broken in a few different ways. The test was running, but
results were not checked as prefix CHECK-COMMON wasn't defined (which is what
FileCheck should warn about). Also, the output was different in 2 cases because
of recent changes in ARMCodeGenPrepare.
Differential Revision: https://reviews.llvm.org/D53746
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345386
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Francis Visoiu Mistrih [Fri, 26 Oct 2018 13:37:25 +0000 (13:37 +0000)]
[CodeGen] Remove out operands from PATCHABLE_OP
The current model requires 1 out operand, but it is not used nor created.
This fixed an x86 machine verifier issue.
Part of PR27481.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345384
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Owen Reynolds [Fri, 26 Oct 2018 13:34:38 +0000 (13:34 +0000)]
[llvm-ar] Access ADDLIB in llvm-ar via command line
ADDLIB is called to add the contents of an archive to another archive.
Previously this was only accessible through the use of an MRI script.
With the use of a new "L" modifier, archive files can treated in the
manner above when using quick append.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345383
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Scott Linder [Fri, 26 Oct 2018 13:18:36 +0000 (13:18 +0000)]
[AMDGPU] Add a pass to promote bitcast calls
AMDGPU currently only supports direct calls, but at lower optimisation levels it
fails to lower statically direct calls which appear indirect due to a bitcast.
Add a pass to visit all CallSites and use CallPromotionUtils to "devirtualize"
calls.
Differential Revision: https://reviews.llvm.org/D52741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345382
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Simon Pilgrim [Fri, 26 Oct 2018 12:33:56 +0000 (12:33 +0000)]
Regenerate test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345379
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Sam McCall [Fri, 26 Oct 2018 12:19:48 +0000 (12:19 +0000)]
[llvm-mca] Fix -wreorder and -Wunused-private-field after r345376. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345378
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George Rimar [Fri, 26 Oct 2018 11:25:12 +0000 (11:25 +0000)]
[Codegen] - Implement basic .debug_loclists section emission (DWARF5).
.debug_loclists is the DWARF 5 version of the .debug_loc.
With that patch, it will be emitted when DWARF 5 is used.
Differential revision: https://reviews.llvm.org/D53365
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345377
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Andrea Di Biagio [Fri, 26 Oct 2018 10:48:04 +0000 (10:48 +0000)]
[llvm-mca] Removed dependency on mca::SourcMgr in some Views. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345376
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Max Kazantsev [Fri, 26 Oct 2018 09:52:58 +0000 (09:52 +0000)]
[SimpleLoopUnswitch] Make all checks before actual non-trivial unswitch
We should be able to make all relevant checks before we actually start the non-trivial
unswitching, so that we could guarantee that once we have started the transform,
it will always succeed.
Reviewed By: chandlerc
Differential Revision: https://reviews.llvm.org/D53747
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345375
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Fangrui Song [Fri, 26 Oct 2018 06:59:08 +0000 (06:59 +0000)]
[SystemZ] Fix -Wcovered-switch-default as coding standard regulates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345369
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Kristina Brooks [Fri, 26 Oct 2018 06:57:02 +0000 (06:57 +0000)]
[NFC] Add periods to CREDITS.txt (testing git-llvm)
NFC commit to test git-llvm bridge for current GitHub monorepo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345368
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Fangrui Song [Fri, 26 Oct 2018 06:56:51 +0000 (06:56 +0000)]
[llvm-nm] Simplify. NFC
Change a \t to spaces
Change some zero-filling memcpy to aggregate initialization
Delete redundant ArchiveName.clear() after declaration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345367
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Li Jia He [Fri, 26 Oct 2018 06:48:53 +0000 (06:48 +0000)]
[PowerPC] Fix some missed optimization opportunities in combineSetCC
For both operands are bool, short, int, long, long long, add the following optimization.
1. 0-x == y --> x+y ==0
2. 0-x != y --> x+y != 0
Review: nemanjai
Differential Revision: https://reviews.llvm.org/D53360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345366
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Li Jia He [Fri, 26 Oct 2018 05:02:10 +0000 (05:02 +0000)]
[PowerPC][NFC] Add tests for some missed optimization opportunities in combineSetCC
For both operands are bool, short, int, long, long long, add the following optimization test case.
1. 0-x == y --> x+y ==0
2. 0-x != y --> x+y != 0
Review: nemanjai
Differential Revision: https://reviews.llvm.org/D53358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345365
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Li Jia He [Fri, 26 Oct 2018 04:54:56 +0000 (04:54 +0000)]
This reverts commit r345357, It is wrong to create a new directory and put the test file into it. I am sorry for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345364
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Nemanja Ivanovic [Fri, 26 Oct 2018 03:30:28 +0000 (03:30 +0000)]
[NFC] Fix the regular expression for BE PPC in update_llc_test_checks.py
Currently, the regular expression that matches the lines of assembly for PPC LE
(ELFv2) does not work for the assembly for BE (ELFv1). This patch fixes it.
Differential revision: https://reviews.llvm.org/D53059
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345363
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Nemanja Ivanovic [Fri, 26 Oct 2018 03:19:13 +0000 (03:19 +0000)]
[PowerPC] Keep vector int to fp conversions in vector domain
At present a v2i16 -> v2f64 convert is implemented by extracts to scalar,
scalar converts, and merge back into a vector. Use vector converts instead,
with the int data permuted into the proper position and extended if necessary.
Patch by RolandF.
Differential revision: https://reviews.llvm.org/D53346
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345361
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Fangrui Song [Fri, 26 Oct 2018 03:15:56 +0000 (03:15 +0000)]
[Pipeliner] Mark swp-art-deps-rec.ll as REQUIRES: asserts after rL345319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345359
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Fangrui Song [Fri, 26 Oct 2018 03:04:54 +0000 (03:04 +0000)]
Add dependency from SystemZAsmParser to SystemZAsmPrinter after rL345349
This fixes -DBUILD_SHARED_LIBS=on build. The dependency is similar to that of X86's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345358
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Li Jia He [Fri, 26 Oct 2018 02:34:57 +0000 (02:34 +0000)]
[PowerPC][NFC] Add tests for some missed optimization opportunities in combineSetCC
For both operands are bool, short, int, long, long long, add the following optimization test case.
1. 0-x == y --> x+y ==0
2. 0-x != y --> x+y != 0
Review: nemanjai
Differential Revision: https://reviews.llvm.org/D53358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345357
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Vlad Tsyrklevich [Fri, 26 Oct 2018 02:00:14 +0000 (02:00 +0000)]
Revert "[AArch64] Create proper memoperand for multi-vector stores"
This reverts commit r345315, it was causing test failures on
sanitizer-x86_64-linux-fast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345356
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Li Jia He [Fri, 26 Oct 2018 01:58:23 +0000 (01:58 +0000)]
add myself to the CREDITS.TXT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345355
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Chijun Sima [Fri, 26 Oct 2018 01:28:36 +0000 (01:28 +0000)]
Teach the DominatorTree fallback to recalculation when applying updates to speedup JT (PR37929)
Summary:
This patch makes the dominatortree recalculate when applying updates with the size of the update vector larger than a threshold. Directly applying updates is usually slower than recalculating the whole domtree in this case. This patch fixes an issue which causes JT running slowly on some inputs.
In bug 37929, the dominator tree is trying to apply 19,000+ updates several times, which takes several minutes.
After this patch, the time used by DT.applyUpdates:
| Input | Before (s) | After (s) | Speedup |
| the 2nd Reproducer in 37929 | 297 | 0.15 | 1980x |
| clang-5.0.0.0.bc | 9.7 | 4.3 | 2.26x |
| clang-5.0.0.4.bc | 11.6 | 2.6 | 4.46x |
Reviewers: kuhar, brzycki, trentxintong, davide, dmgreen, grosser
Reviewed By: kuhar, brzycki
Subscribers: kristina, llvm-commits
Differential Revision: https://reviews.llvm.org/D53245
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345353
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Jonas Paulsson [Fri, 26 Oct 2018 00:36:00 +0000 (00:36 +0000)]
[SystemZ] Implement SystemZOperand::print()
SystemZAsmParser can now handle -debug by printing the operands neatly to the
output stream. Before this patch this lead to an llvm_unreachable().
It seems that now '-mllvm -debug' does not cause any crashes anywhere (at
least not on SPEC).
Review: Ulrich Weigand
https://reviews.llvm.org/D53328
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345349
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Zachary Turner [Fri, 26 Oct 2018 00:17:31 +0000 (00:17 +0000)]
Dump public symbol records in pdb2yaml mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345348
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Jonas Paulsson [Fri, 26 Oct 2018 00:02:33 +0000 (00:02 +0000)]
[SystemZ] Pass the DAG pointer from SystemZAddressingMode::dump().
In order to print the IR slot number for the memory operand, the DAG pointer
must be passed to SDNode::dump().
The isel-debug.ll test updated to also check for the IR Value reference being
printed correctly.
Review: Ulrich Weigand
https://reviews.llvm.org/D53333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345347
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Heejin Ahn [Thu, 25 Oct 2018 23:55:10 +0000 (23:55 +0000)]
Reland "[WebAssembly] LSDA info generation"
Summary:
This adds support for LSDA (exception table) generation for wasm EH.
Wasm EH mostly follows the structure of Itanium-style exception tables,
with one exception: a call site table entry in wasm EH corresponds to
not a call site but a landing pad.
In wasm EH, the VM is responsible for stack unwinding. After an
exception occurs and the stack is unwound, the control flow is
transferred to wasm 'catch' instruction by the VM, after which the
personality function is called from the compiler-generated code. (Refer
to WasmEHPrepare pass for more information on this part.)
This patch:
- Changes wasm.landingpad.index intrinsic to take a token argument, to
make this 1:1 match with a catchpad instruction
- Stores landingpad index info and catch type info MachineFunction in
before instruction selection
- Lowers wasm.lsda intrinsic to an MCSymbol pointing to the start of an
exception table
- Adds WasmException class with overridden methods for table generation
- Adds support for LSDA section in Wasm object writer
Reviewers: dschuff, sbc100, rnk
Subscribers: mgorny, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52748
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345345
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Heejin Ahn [Thu, 25 Oct 2018 23:45:48 +0000 (23:45 +0000)]
[WebAssembly] Support EH instructions in InstPrinter
Summary: This adds support for exception handling instructions to InstPrinter.
Reviewers: dschuff, aardappel
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345343
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Jonas Paulsson [Thu, 25 Oct 2018 23:39:07 +0000 (23:39 +0000)]
Fix in MachineOperand::printIRValueReference().
Handle the case where getCurrentFunction() returns nullptr by passing -1 to
printIRSlotNumber(). This will result in <badref> being printed instead of an
assertion failure.
Review: Francis Visoiu Mistrih
https://reviews.llvm.org/D53333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345342
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Bryan Chan [Thu, 25 Oct 2018 23:36:41 +0000 (23:36 +0000)]
[AArch64] Implement FP16FML intrinsics
Add LLVM intrinsics for the ARMv8.2-A FP16FML vector-form instructions. Add a
DAG pattern to define the indexed-form intrinsics in terms of the vector-form
ones, similarly to how the Dot Product intrinsics were implemented.
Based on a patch by Gao Yiling.
Differential Revision: https://reviews.llvm.org/D53632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345337
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Heejin Ahn [Thu, 25 Oct 2018 23:35:15 +0000 (23:35 +0000)]
Delete test case. Assertions can't be tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345336
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Heejin Ahn [Thu, 25 Oct 2018 23:35:15 +0000 (23:35 +0000)]
Tidy up test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345335
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Heejin Ahn [Thu, 25 Oct 2018 23:35:14 +0000 (23:35 +0000)]
Address comments
- Add llvm-mc test case (and delete the old one)
- Change report_fatal_error to assertions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345334
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Heejin Ahn [Thu, 25 Oct 2018 23:35:13 +0000 (23:35 +0000)]
[WebAssembly] Error out when block/loop markers mismatch
Summary:
Currently InstPrinter ignores if there are mismatches between block/loop
and end markers by skipping the case if ControlFlowStack is empty. I
guess it is better to explicitly error out in this case, because this
signals invalid input.
Reviewers: aardappel
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53620
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345333
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Jonas Paulsson [Thu, 25 Oct 2018 22:53:27 +0000 (22:53 +0000)]
[SystemZ] NFC reformatting in SystemZTargetTransformInfo.cpp
Some lines more than 80 characters long reformatted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345331
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Jonas Paulsson [Thu, 25 Oct 2018 22:28:25 +0000 (22:28 +0000)]
[SystemZ] Improve getMemoryOpCost() to find foldable loads that are converted.
The SystemZ backend can do arithmetic of memory by loading and then extending
one of the operands. Similarly, a load + truncate can be folded into an
operand.
This patch improves the SystemZ TTI cost function to recognize this.
Review: Ulrich Weigand
https://reviews.llvm.org/D52692
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345327
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David Blaikie [Thu, 25 Oct 2018 22:26:25 +0000 (22:26 +0000)]
DebugInfo: Explain why DW_LLE_(GNU_)startx_length is used
This isn't the most object-size efficient encoding, but it's the only
one GDB supports for the pre-standard fission format. I've written fixes
for this twice now... - so perhaps this comment will help me remember
why neither of these have been committed and why I shouldn't try to
write a third fix another year from now...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345326
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Sanjay Patel [Thu, 25 Oct 2018 22:23:27 +0000 (22:23 +0000)]
[x86] add tests for missed load folding; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345325
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Jonas Paulsson [Thu, 25 Oct 2018 21:47:22 +0000 (21:47 +0000)]
[SystemZ] Improve handling and cost estimates of vector integer div/rem
Enable the DAG optimization that converts vector div/rem with constants into
multiply+shifts sequences by expanding them early. This is needed since
ISD::SMUL_LOHI is 'Custom' lowered on SystemZ, and will therefore not be
available to BuildSDIV after legalization.
Better cost values for these instructions based on how they will be
implemented (a constant divisor is cheaper).
Review: Ulrich Weigand
https://reviews.llvm.org/D53196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345321
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David Blaikie [Thu, 25 Oct 2018 21:35:59 +0000 (21:35 +0000)]
llvm-dwarfdump: loclists: Don't expect an (albeit empty) expression for LLE_base_address
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345320
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Sumanth Gundapaneni [Thu, 25 Oct 2018 21:27:08 +0000 (21:27 +0000)]
[Pipeliner] Ignore Artificial dependences while computing recurrences.
The artificial dependencies are not real dependencies. In some cases, they
form circuits with bigger MII. However, they are used to schedule instructions
better.
Differential Revision: https://reviews.llvm.org/D53450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345319
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Sumanth Gundapaneni [Thu, 25 Oct 2018 21:25:30 +0000 (21:25 +0000)]
[Pipeliner] Remove the unneeded include header(NFC).
Differential Revision: https://reviews.llvm.org/D53451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345318
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Craig Topper [Thu, 25 Oct 2018 21:16:06 +0000 (21:16 +0000)]
[X86] Change X86 backend to look for 'min-legal-vector-width' attribute instead of 'required-vector-width' when determining whether 512-bit vectors should be legal.
The required-vector-width attribute was only used for backend testing and has never been generated by clang.
I believe clang is now generating min-legal-vector-width for vector uses in user code.
With this I believe passing -mprefer-vector-width=256 to clang should prevent use of zmm registers in the generated assembly unless the user used a 512-bit intrinsic in their source code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345317
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Francis Visoiu Mistrih [Thu, 25 Oct 2018 21:12:15 +0000 (21:12 +0000)]
[CodeGen] Remove operands from FENTRY_CALL
FENTRY_CALL is actually not taking any input / output operands. The
machine verifier complains now because the target description says that:
* It needs 1 unknown output
* It needs 1 or more variable inputs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345316
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David Greene [Thu, 25 Oct 2018 21:10:39 +0000 (21:10 +0000)]
[AArch64] Create proper memoperand for multi-vector stores
Include all of the store's source vector operands when creating the
MachineMemOperand. Previously, we were missing the first operand,
making the store size seem smaller than it really is.
Differential Revision: https://reviews.llvm.org/D52816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345315
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Volkan Keles [Thu, 25 Oct 2018 20:01:19 +0000 (20:01 +0000)]
[AArch64][GlobalISel] Simplify a legalizer test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345307
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Thomas Lively [Thu, 25 Oct 2018 19:06:13 +0000 (19:06 +0000)]
[WebAssembly] Use target-independent saturating add
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53721
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345299
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Craig Topper [Thu, 25 Oct 2018 18:23:48 +0000 (18:23 +0000)]
[X86] Add some non-AVX512VL command lines to the *vl-vec-test-testn.ll tests.
This will expose some regressions in the WIP and/or/xor promotion removal patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345297
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Cameron McInally [Thu, 25 Oct 2018 18:09:33 +0000 (18:09 +0000)]
[FPEnv] Last BinaryOperator::isFNeg(...) to m_FNeg(...) changes
Replacing BinaryOperator::isFNeg(...) to avoid regressions when we
separate FNeg from the FSub IR instruction.
Differential Revision: https://reviews.llvm.org/D53650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345295
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Craig Topper [Thu, 25 Oct 2018 18:06:25 +0000 (18:06 +0000)]
[X86] Add KNL command lines to movmsk-cmp.ll.
Some of this code looks pretty bad and we should probably still be using movmskb more with avx512f.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345293
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Volkan Keles [Thu, 25 Oct 2018 17:52:19 +0000 (17:52 +0000)]
[GlobalISel] LegalizerHelper: Fix the incorrect alignment when splitting loads/stores in narrowScalar
Reviewers: dsanders, bogner, jpaquette, aemerson, ab, paquette
Reviewed By: dsanders
Subscribers: rovka, kristof.beyls, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D53664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345292
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Simon Pilgrim [Thu, 25 Oct 2018 17:43:36 +0000 (17:43 +0000)]
[LegalizeDAG] Remove dead SINT_TO_FP legalization code
As noticed on D52965, the SINT_TO_FP i64 to f32 legalization code has been dead for years - protected by an assert.
Differential Revision: https://reviews.llvm.org/D53703
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345290
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Volkan Keles [Thu, 25 Oct 2018 17:37:07 +0000 (17:37 +0000)]
[GISel] LegalizerInfo: Rename MemDesc::Size to SizeInBits to make the value clearer
Requested in D53679.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345288
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Craig Topper [Thu, 25 Oct 2018 17:29:00 +0000 (17:29 +0000)]
[X86] Remove ProcIntelKNL and replace with a SlowPMADDWD flag to use in the one place it was checked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345286
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Craig Topper [Thu, 25 Oct 2018 17:28:57 +0000 (17:28 +0000)]
[X86] Remove some uarch tuning flags from KNL that look to have been inherited from SNB/IVB incorrectly
KNL is based on a modified Silvermont core so I don't think these features apply. I think the LEA flag is probably also wrong, but I'm less sure as I barely understand the 3 LEA flags we have currently.
Differential Revision: https://reviews.llvm.org/D53671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345285
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Volkan Keles [Thu, 25 Oct 2018 17:23:25 +0000 (17:23 +0000)]
[AArch64][GlobalISel] Fix the LegalityPredicate for lowerIf for G_LOAD/G_STORE
Summary:
Currently, Legalizer is trying to lower G_LOAD with a vector type
that has more than two elements due to the incorrect LegalityPredicate.
This patch fixes the issue by removing the multiplication by 8
as `MemDesc.Size` already contains the size in bits.
Reviewers: dsanders, aemerson
Reviewed By: dsanders
Subscribers: rovka, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D53679
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345282
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Andrea Di Biagio [Thu, 25 Oct 2018 17:03:51 +0000 (17:03 +0000)]
[llvm-mca] Introduce a new base class for mca::Instruction, and change how read/write information is stored.
This patch introduces a new base class for Instruction named InstructionBase.
Class InstructionBase is responsible for tracking data dependencies with the
help of ReadState and WriteState objects. Class Instruction now derives from
InstructionBase, and adds extra information related to the `InstrStage` as well
as the `RCUTokenID`.
ReadState and WriteState objects are no longer unique pointers. This avoids
extra heap allocation and pointer checks that weren't really needed. Now, those
objects are simply stored into SmallVectors. We use a SmallVector instead of a
std::vector because we expect most instructions to only have a very small number
of reads and writes. By using a simple SmallVector we also avoid extra heap
allocations most of the time.
In a debug build, this improves the performance of llvm-mca by roughly 10% (I
still have to verify the impact in performance on a release build).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345280
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Evandro Menezes [Thu, 25 Oct 2018 16:45:46 +0000 (16:45 +0000)]
[AArch64] Refactor Exynos feature sets (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345279
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Simon Pilgrim [Thu, 25 Oct 2018 15:33:47 +0000 (15:33 +0000)]
[ARM] Regenerate vdup tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345276
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John Brawn [Thu, 25 Oct 2018 15:31:51 +0000 (15:31 +0000)]
[AArch64] Add EXT patterns for 64-bit EXT of a subvector of a 128-bit vector
If we have a 64-bit EXT where one of the operands is a subvector of a 128-bit
vector then in some cases we can eliminate an extract_subvector by converting
to a 128-bit EXT of the 128-bit vector.
Differential Revision: https://reviews.llvm.org/D53582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345275
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Sam Parker [Thu, 25 Oct 2018 15:08:29 +0000 (15:08 +0000)]
[ARM] Use Cortex-A57 sched model for Cortex-A72
This mirrors what we already do for AArch64 as the cores are similar.
As discussed in the review, enabling the machine scheduler causes
more variations in performance changes so it is not enabled for now.
This patch improves LNT scores by a geomean of 1.57% at -O3.
Differential Revision: https://reviews.llvm.org/D53562
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345272
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John Brawn [Thu, 25 Oct 2018 15:00:10 +0000 (15:00 +0000)]
[AArch64] Refactor definition of EXT patterns to use a multiclass
Using a multiclass reduces duplication, and makes it easier to add new patterns
later. This refactoring does add some new patterns, but as far as I can tell
there's no IR that will end up triggering them so this is effectively NFC.
Differential Revision: https://reviews.llvm.org/D53580
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345271
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John Brawn [Thu, 25 Oct 2018 14:56:48 +0000 (14:56 +0000)]
[AArch64] Do 64-bit vector move of 0 and -1 by extracting from the 128-bit move
Currently a vector move of 0 or -1 will use different instructions depending on
the size of the vector. Using a single instruction (the 128-bit one) for both
gives more opportunity for Machine CSE to eliminate instructions.
Differential Revision: https://reviews.llvm.org/D53579
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345270
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Alexey Bataev [Thu, 25 Oct 2018 14:27:27 +0000 (14:27 +0000)]
[DEBUG_INFO][NVPTX]Fix processing of DBG_VALUES.
Summary:
If the instruction in the eliminateFrameIndex function is a DBG_VALUE
instruction, it requires special processing. The frame register is set
to VRFrame and the offset is based on the object offset.
The code is similar to the code used in
lib/CodeGen/PrologEpilogInserter.cpp.
Reviewers: tra
Subscribers: jholewinski, llvm-commits
Differential Revision: https://reviews.llvm.org/D53657
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345269
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Francis Visoiu Mistrih [Thu, 25 Oct 2018 14:11:07 +0000 (14:11 +0000)]
[X86] Fix llc invocation on MIR test case
The current state of the llc invocation is:
* Running all the passes from dwarfehprepare to stack coloring
(included)
* It runs it from the LLVM IR included in the file
* It *ADDS* the generated MI from ISel to the MI in the MIR file
* The machine verifier doesn't like it.
Differential Revision: https://reviews.llvm.org/D53698
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345266
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Amara Emerson [Thu, 25 Oct 2018 14:04:54 +0000 (14:04 +0000)]
[GlobalISel] Use the target preferred type for G_EXTRACT_VECTOR_ELT index.
Allows for better imported pattern re-use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345265
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Krasimir Georgiev [Thu, 25 Oct 2018 13:38:07 +0000 (13:38 +0000)]
IR: Optimize StructType::get to perform one hash lookup instead of two, NFCI
Summary:
This function was performing two hash lookups when a new struct type was requested: first checking if it exists and second to insert it. This patch updates the function to perform a single hash lookup in this case by updating the value in the hash table in-place in case the struct type was not there before.
Similar to r345151.
Reviewers: bkramer
Reviewed By: bkramer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53689
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345264
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Simon Pilgrim [Thu, 25 Oct 2018 13:06:20 +0000 (13:06 +0000)]
[CostModel][X86] Add realistic vXi64 uitofp vXf64 costs
Match codegen improvements from D53649/rL345256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345263
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Alex Bradbury [Thu, 25 Oct 2018 12:45:20 +0000 (12:45 +0000)]
[RISCV] Use PatFrags for variable shift patterns
This follows SystemZ and I think is cleaner vs the multiclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345262
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Simon Pilgrim [Thu, 25 Oct 2018 12:42:10 +0000 (12:42 +0000)]
[CostModel][X86] Add realistic i64 uitofp f64 scalar costs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345261
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Andrea Di Biagio [Thu, 25 Oct 2018 11:51:34 +0000 (11:51 +0000)]
[llvm-mca] Removed a couple of redundant method declarations, and simplified code in ResourcePressureView. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345259
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Simon Pilgrim [Thu, 25 Oct 2018 11:38:17 +0000 (11:38 +0000)]
Missing semicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345257
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Simon Pilgrim [Thu, 25 Oct 2018 11:15:57 +0000 (11:15 +0000)]
[TargetLowering] Improve vXi64 UINT_TO_FP vXf64 support (P38226)
As suggested on D52965, this patch moves the i64 to f64 UINT_TO_FP expansion code from LegalizeDAG into TargetLowering and makes it available to LegalizeVectorOps as well.
Not only does this help perform X86 lowering as a true vectorization instead of (partially vectorized) scalar conversions, it avoids the HADDPD op from the scalar code which can be slow on most targets.
The AVX512F does have the vcvtusi2sdq scalar operation but we don't unroll to use it as it seems to only help for the v2f64 case - otherwise the unrolling cost will certainly be too high. My feeling is that we should leave it to the vectorizers - and if it generates the vector UINT_TO_FP we should use it.
Differential Revision: https://reviews.llvm.org/D53649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345256
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George Rimar [Thu, 25 Oct 2018 10:56:44 +0000 (10:56 +0000)]
[llvm-dwarfdump] - Fix incorrect parsing of the DW_LLE_startx_length
As was already mentioned in comments for D53364, DWARF 5
spec says about DW_LLE_startx_length:
"This is a form of bounded location description that has two unsigned ULEB operands.
The first value is an address index (into the .debug_addr section) that indicates the beginning of the address range
over which the location is valid. The second value is the length of the range. ")
Currently, the length is always parsed as U32.
Patch change the behavior to parse DW_LLE_startx_length as ULEB128 for DWARF 5
and keeps it as U32 for DWARF4+(pre-DWARF5) for compatibility.
Differential revision: https://reviews.llvm.org/D53564
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345254
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Simon Pilgrim [Thu, 25 Oct 2018 10:52:36 +0000 (10:52 +0000)]
[TTI] Add generic SK_Broadcast shuffle costs
I noticed while fixing PR39368 that we don't have generic shuffle costs for broadcast style shuffles.
This patch adds SK_BROADCAST handling, but exposes ARM/AARCH64 lack of handling of this type, which I've added a fix for at the same time.
Differential Revision: https://reviews.llvm.org/D53570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345253
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Simon Pilgrim [Thu, 25 Oct 2018 10:45:38 +0000 (10:45 +0000)]
Fix MSVC llvm-exegesis build. NFCI.
MSVC is a bit funny about is_pod.....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345252
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Carlos Alberto Enciso [Thu, 25 Oct 2018 09:58:59 +0000 (09:58 +0000)]
[DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG.
When SimplifyCFG changes the PHI node into a select instruction, the debug line records becomes ambiguous. It causes the debugger to display unreachable source lines.
Differential Revision: https://reviews.llvm.org/D53287
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345250
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Gabor Buella [Thu, 25 Oct 2018 08:32:29 +0000 (08:32 +0000)]
Add -instcombine-code-sinking option
Reviewers: craig.topper, andrew.w.kaylor, efriedma
Reviewed By: craig.topper, andrew.w.kaylor, efriedma
Differential Revision: https://reviews.llvm.org/D52709
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345248
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Clement Courbet [Thu, 25 Oct 2018 08:11:35 +0000 (08:11 +0000)]
[llvm-exegesis] Add missing initializer.
This is a better fix than rL345245.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345246
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Clement Courbet [Thu, 25 Oct 2018 08:08:58 +0000 (08:08 +0000)]
[llvm-exegesis] Fix VC build of r345243.
"const members cannot be default initialized unless their type has a user defined default constructor"
Make members non-const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345245
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Clement Courbet [Thu, 25 Oct 2018 08:06:35 +0000 (08:06 +0000)]
[llvm-exegesis] Fix warning in r345243.
warning C4099: 'llvm::exegesis::PfmCountersInfo': type name first seen using 'class' now seen using 'struct'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345244
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Clement Courbet [Thu, 25 Oct 2018 07:44:01 +0000 (07:44 +0000)]
[MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.
Summary:
The pfm counters are now in the ExegesisTarget rather than the
MCSchedModel (PR39165).
This also compresses the pfm counter tables (PR37068).
Reviewers: RKSimon, gchatelet
Subscribers: mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D52932
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345243
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Craig Topper [Thu, 25 Oct 2018 07:00:09 +0000 (07:00 +0000)]
[X86] Don't use the OriginalDemandedBits to calculate the DemandedMask for PMULUDQ/PMULDQ inputs.
Multiply a is complex operation so just because some bit of the output isn't used doesn't mean that bit of the input isn't used.
We might able to bound it, but it will require some more thought.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345241
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Simon Atanasyan [Thu, 25 Oct 2018 05:39:27 +0000 (05:39 +0000)]
[llvm-readobj] Print ELF header flags names in GNU output
GNU readelf tool prints hex value of the ELF header flags field and the
flags names. This change adds the same functionality to llvm-readobj.
Now llvm-readobj can print MIPS and RISCV flags.
New GNUStyle::printFlags() method is a copy of ScopedPrinter::printFlags()
routine. Probably we can escape code duplication and / or simplify the
printFlags() method. But it's a task for separate commit.
Differential revision: https://reviews.llvm.org/D52027
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345238
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Craig Topper [Thu, 25 Oct 2018 05:00:20 +0000 (05:00 +0000)]
[X86] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345236
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Thomas Lively [Thu, 25 Oct 2018 01:46:07 +0000 (01:46 +0000)]
[WebAssembly] Set LoadExt and TruncStore actions for SIMD types
Summary: Fixes part of the problem reported in bug 39275.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits, alexcrichton
Differential Revision: https://reviews.llvm.org/D53542
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345230
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Reid Kleckner [Wed, 24 Oct 2018 23:52:33 +0000 (23:52 +0000)]
[X86] Adjust MIR test case to pacify machine verifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345227
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Reid Kleckner [Wed, 24 Oct 2018 23:52:22 +0000 (23:52 +0000)]
[X86] Fix pipeline tests when enabling MIR verification, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345226
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David Blaikie [Wed, 24 Oct 2018 23:36:29 +0000 (23:36 +0000)]
DebugInfo: Reuse common addresses for rnglist base address selections
This makes the offsets larger (since they are further from the base
address) but those are in the .dwo - and allows removing addresses and
relocations from the .o file.
This could be built into the AddressPool more fundamentally, perhaps -
when you ask for an AddressPool entry you could say "or give me some
other entry and an offset I need to use" - though what to do about
situations where the first use of an address in a section is not the
earliest address in that section... is tricky.
At least with range addresses we can be fairly sure we've seen the
earliest address first because we see the start address for the
function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345224
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Heejin Ahn [Wed, 24 Oct 2018 23:31:24 +0000 (23:31 +0000)]
[WebAssembly] Fix immediate of rethrow when throwing to caller
Summary:
Currently when assigning depths 'rethrow' does not take the whole
control flow stack into accounts but only considers EH pad stacks. When
assigning depth immmediates to rethrows, in normal cases it is done
correctly but when a rethrow instruction throws up to a caller, i.e., we
convert a pseudo RETHROW_TO_CALLER instruction to a rethrow, it
mistakenly compute the whole stack depth.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345223
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Thomas Lively [Wed, 24 Oct 2018 23:27:40 +0000 (23:27 +0000)]
[WebAssembly] Retain shuffle types during custom lowering
Summary:
Changing the node type in lowering was violating assumptions made in
the DAG combiner, so don't change the node type any more. This fixes
one of the issues reported in bug 39275.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits, alexcrichton
Differential Revision: https://reviews.llvm.org/D53537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345221
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Thomas Lively [Wed, 24 Oct 2018 23:14:59 +0000 (23:14 +0000)]
Make fminimum/fmaximum SDNodes commutative and associative
Reviewers: aheejin, dschuff
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345220
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Reid Kleckner [Wed, 24 Oct 2018 22:57:28 +0000 (22:57 +0000)]
[ELF] Fix large code model MIR verifier errors
Instead of using the MOVGOT64r pseudo, use the existing
MO_PIC_BASE_OFFSET support on symbol operands. Now I don't have to
create a "scratch register operand" for the pseudo to use, and the
register allocator can make better decisions.
Fixes some X86 verifier errors tracked in PR27481.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345219
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Thomas Lively [Wed, 24 Oct 2018 22:49:55 +0000 (22:49 +0000)]
[NFC] Rename minnan and maxnan to minimum and maximum
Summary:
Changes all uses of minnan/maxnan to minimum/maximum
globally. These names emphasize that the semantic difference between
these operations is more than just NaN-propagation.
Reviewers: arsenm, aheejin, dschuff, javed.absar
Subscribers: jholewinski, sdardis, wdng, sbc100, jgravelle-google, jrtc27, atanasyan, llvm-commits
Differential Revision: https://reviews.llvm.org/D53112
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345218
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Alexander Shaposhnikov [Wed, 24 Oct 2018 22:49:06 +0000 (22:49 +0000)]
[llvm-objcopy] Introduce dispatch mechanism based on the input
In this diff we introduce dispatch mechanism based on
the type of the input (archive, object file, raw binary)
and the format (coff, elf, macho).
We also move the ELF-specific code into the namespace llvm::objcopy::elf.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D53311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345217
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Alina Sbirlea [Wed, 24 Oct 2018 22:46:45 +0000 (22:46 +0000)]
Update MemorySSA in LoopRotate.
Summary:
Teach LoopRotate to preserve MemorySSA.
Enable tests for correctness, dependency disabled by default.
Subscribers: sanjoy, jlebar, Prazek, george.burgess.iv, llvm-commits
Differential Revision: https://reviews.llvm.org/D51718
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345216
91177308-0d34-0410-b5e6-
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David Blaikie [Wed, 24 Oct 2018 22:44:54 +0000 (22:44 +0000)]
llvm-dwarfdump: Account for skeleton addr_base when dumping addresses in split unit in the same file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345215
91177308-0d34-0410-b5e6-
96231b3b80d8