OSDN Git Service
Jacob Gravelle [Tue, 10 Oct 2017 16:20:18 +0000 (16:20 +0000)]
[WebAssembly] Narrow the scope of WebAssemblyFixFunctionBitcasts
Summary:
The pass to fix function bitcasts generates thunks for functions that
are called directly with a mismatching signature. It was also generating
thunks in cases where the function was address-taken, causing aliasing
problems in otherwise valid cases.
This patch tightens the restrictions for when the pass runs.
Reviewers: sunfish, dschuff
Subscribers: jfb, sbc100, llvm-commits, aheejin
Differential Revision: https://reviews.llvm.org/D38640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315326
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Simon Pilgrim [Tue, 10 Oct 2017 15:58:54 +0000 (15:58 +0000)]
[X86][AVX512] Regenerate element insertion/extraction tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315322
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Javed Absar [Tue, 10 Oct 2017 15:58:45 +0000 (15:58 +0000)]
[TableGen] Convert VarDef to range_loop. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315321
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Simon Dardis [Tue, 10 Oct 2017 14:41:11 +0000 (14:41 +0000)]
[mips] Duplicate the reciprocal instruction definitions for FP32
Add instruction definitions for FP32 mode for recip.d and rsqrt.d.
Previously these instructions were only defined when targeting the
full 64-bit FPU model but were not guarded properly.
Reviewers: nitesh.jain, atanasyan
Differential Revision: https://reviews.llvm.org/D38400
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315318
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Jonas Devlieghere [Tue, 10 Oct 2017 14:15:25 +0000 (14:15 +0000)]
Re-land "[llvm-dwarfdump] Print type names in DW_AT_type DIEs"
This patch adds printing for DW_AT_type DIEs like it is already the case
for DW_AT_specification DIEs. This is a rather naive approach and only a
start. We should have pretty printers for different languages.
Recommit after being reverted in r315299.
Differential revision: https://reviews.llvm.org/D36993
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315316
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Stefan Pintilie [Tue, 10 Oct 2017 13:45:35 +0000 (13:45 +0000)]
[PowerPC] Add missing record form instructions to the P9 Scheduling Model
A number of record form instructions were missing from the P9 scheduling
model. Added those instructions and marked the P9 model as complete.
Differential Revision: https://reviews.llvm.org/D38560
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315313
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Sanjay Patel [Tue, 10 Oct 2017 13:45:25 +0000 (13:45 +0000)]
[x86] add tests for insertelement; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315312
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Uriel Korach [Tue, 10 Oct 2017 13:43:09 +0000 (13:43 +0000)]
after fixing the i386 case
Change-Id: If6fe0b6ec01f111115fb734fe31c0e152dbc165f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315311
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Simon Dardis [Tue, 10 Oct 2017 13:34:45 +0000 (13:34 +0000)]
[mips] Partially fix PR34391
Previously, the parsing of the 'subu $reg, ($reg,) imm' relied on a parser
which also rendered the operand to the instruction. In some cases the
general parser could construct an MCExpr which was not a MCConstantExpr
which MipsAsmParser was expecting.
Address this by altering the special handling to cope with unexpected inputs
and fine-tune the handling of cases where an register name that is not
available in the current ABI is regarded as not a match for the custom parser
but also not as an outright error.
Also enforces the binutils restriction that only constants are accepted.
This partially resolves PR34391.
Thanks to Ed Maste for reporting the issue!
Reviewers: nitesh.jain, arichardson
Differential Revision: https://reviews.llvm.org/D37476
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315310
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David Stuttard [Tue, 10 Oct 2017 12:45:45 +0000 (12:45 +0000)]
[DAGCombine] Fix for shuffle to vector extend for non power 2 vectors
Summary:
See https://llvm.org/PR33743 for more details
It seems that for non-power of 2 vector sizes, the algorithm can produce
non-matching sizes for input and result causing an assert.
This usually isn't a problem as the isAnyExtend check will weed these out, but
in some cases (most often with lots of undefined values for the mask indices) it
can pass this check for non power of 2 vectors.
Adding in an extra check that ensures that bit size will match for the result
and input (as required)
Subscribers: nhaehnle
Differential Revision: https://reviews.llvm.org/D35241
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315307
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Oliver Stannard [Tue, 10 Oct 2017 12:38:22 +0000 (12:38 +0000)]
[ARM, Asm] Harden GNU LDRD/STRD aliases against invalid inputs
Previously, the code that implemented the GNU assembler aliases for the
LDRD and STRD instructions (where the second register is omitted)
assumed that the input was a valid instruction. This caused assertion
failures for every example in ldrd-strd-gnu-bad-inst.s.
This improves this code so that it bails out if the instruction is not
in the expected format, the check bails out, and the asm parser is run
on the unmodified instruction.
It also relaxes the alias on thumb targets, so that unaligned pairs of
registers can be used. The restriction that Rt must be even-numbered
only applies to the ARM versions of these instructions.
Differential revision: https://reviews.llvm.org/D36732
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315305
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Oliver Stannard [Tue, 10 Oct 2017 12:35:09 +0000 (12:35 +0000)]
[ARM, Asm] Add diagnostics for floating-point register operands
This adds diagnostic strings for the ARM floating-point register
classes, which will be used when these classes are expected by the
assembler, but the provided operand is not valid.
One of these, DPR, requires C++ code to select the correct error
message, as that class contains different registers depending on the
FPU. The rest can all have their diagnostic strings stored in the
tablegen decription of them.
Differential revision: https://reviews.llvm.org/D36693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315304
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Oliver Stannard [Tue, 10 Oct 2017 12:31:53 +0000 (12:31 +0000)]
[ARM, Asm] Add diagnostics for general-purpose register operands
This adds diagnostic strings for the ARM general-purpose register
classes, which will be used when these classes are expected by the
assembler, but the provided operand is not valid.
One of these, rGPR, requires C++ code to select the correct error
message, as that class contains different registers in pre-v8 and v8
targets. The rest can all have their diagnostic strings stored in the
tablegen description of them.
Differential revision: https://reviews.llvm.org/D36692
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315303
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Nicolai Haehnle [Tue, 10 Oct 2017 12:22:23 +0000 (12:22 +0000)]
AMDGPU: Split MUBUF offset into aligned components
Summary:
Atomic buffer operations do not work (and trap on gfx9) when the
components are unaligned, even if their sum is aligned.
Previously, we generated an offset of 4156 without an SGPR by
splitting it as 4095 + 61 (immediate + inline constant). The
highest offset for which we can do this correctly is 4156 = 4092 + 64.
Fixes dEQP-GLES31.functional.ssbo.atomic.*
Reviewers: arsenm
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D37850
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315302
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Jonas Devlieghere [Tue, 10 Oct 2017 11:49:56 +0000 (11:49 +0000)]
Revert "[llvm-dwarfdump] Print type names in DW_AT_type DIEs"
This reverts commit r315297.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315299
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Jonas Devlieghere [Tue, 10 Oct 2017 11:24:41 +0000 (11:24 +0000)]
[llvm-dwarfdump] Print type names in DW_AT_type DIEs
This patch adds printing for DW_AT_type DIEs like it is already the case
for DW_AT_specification DIEs. This is a rather naive approach and only a
start. We should have pretty printers for different languages.
Differential revision: https://reviews.llvm.org/D36993
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315297
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Oliver Stannard [Tue, 10 Oct 2017 11:00:40 +0000 (11:00 +0000)]
[AsmParser] Add DiagnosticString to register classes in tablegen
This allows a DiagnosticType and/or DiagnosticString to be associated
with a RegisterClass in tablegen, so that we can emit diagnostics in the
assembler when a register operand is incorrect.
DiagnosticType creates a predictable enum value, which gets returned as
the error code when an operand does not match, and can be used by the
assembly parser to map to a user-facing diagnostic. DiagnosticString
creates an anonymous enum value (currently based on the tablegen class
name), and a function to map from enum values to strings will be
generated. Both of these work the same was as they do for AsmOperand.
This isn't used by any targets yet, but has one (positive) side-effect.
It improves the diagnostic codes returned by validateOperandClass - we
always want to emit the diagnostic that relates to the expected operand
class, but this wasn't always being done when the expected and actual
classes were completely different (token/register/custom). This causes a
few AArch64 diagnostics to be improved, as Match_InvalidOperand was
being returned instead of a specific diagnostic type.
Differential revision: https://reviews.llvm.org/D36691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315295
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Florian Hahn [Tue, 10 Oct 2017 10:33:45 +0000 (10:33 +0000)]
[SCCP] Fix mem-sanitizer failure introduced by r315288.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315294
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Gadi Haber [Tue, 10 Oct 2017 09:53:18 +0000 (09:53 +0000)]
[X86][SKYLAKE] Update regression test to differentiate between HASWELL and SKYLAKE scheduling.<NFC>
NFC.
Updated 6 regression tests to differentiate between HASWELL and SKYLAKE scheduling information.
The fix is in preparation of a patch to update the information of the Skylake Client scheduling to include the appropriate load and store latencies.
Reviewers: zvi, RKSimon
Differential Revision: https://reviews.llvm.org/D38685
Change-Id: Ifc6b98d9eaf266913698f24c766fd994fc977555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315291
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Florian Hahn [Tue, 10 Oct 2017 09:32:38 +0000 (09:32 +0000)]
[SCCP] Propagate integer range info for parameters in IPSCCP.
Summary:
This updates the SCCP solver to use of the ValueElement lattice for
parameters, which provides integer range information. The range
information is used to remove unneeded icmp instructions.
For the following function, f() can be optimized to `ret i32 2` with
this change
source_filename = "sccp.c"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: norecurse nounwind readnone uwtable
define i32 @main() local_unnamed_addr #0 {
entry:
%call = tail call fastcc i32 @f(i32 1)
%call1 = tail call fastcc i32 @f(i32 47)
%add3 = add nsw i32 %call, %call1
ret i32 %add3
}
; Function Attrs: noinline norecurse nounwind readnone uwtable
define internal fastcc i32 @f(i32 %x) unnamed_addr #1 {
entry:
%c1 = icmp sle i32 %x, 100
%cmp = icmp sgt i32 %x, 300
%. = select i1 %cmp, i32 1, i32 2
ret i32 %.
}
attributes #1 = { noinline }
Reviewers: davide, sanjoy, efriedma, dberlin
Reviewed By: davide, dberlin
Subscribers: mcrosier, gberry, mssimpso, dberlin, llvm-commits
Differential Revision: https://reviews.llvm.org/D36656
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315288
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Nemanja Ivanovic [Tue, 10 Oct 2017 08:46:10 +0000 (08:46 +0000)]
Fix for PR34888.
The issue is that we assume operand zero of the input to the add instruction
is a register. In this case, the input comes from inline assembly and
operand zero is not a register thereby causing a crash.
The code will bail anyway if the input instruction doesn't have the right
opcode. So do that check first and let short-circuiting prevent the crash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315285
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NAKAMURA Takumi [Tue, 10 Oct 2017 08:30:53 +0000 (08:30 +0000)]
SILoadStoreOptimizer.cpp: Fix build; Clang doesn't like "using anonymous struct" since rL315256.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315283
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NAKAMURA Takumi [Tue, 10 Oct 2017 08:30:45 +0000 (08:30 +0000)]
MCWinCOFFObjectWriter.h: Fix modules build in rL315257.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315282
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Clement Courbet [Tue, 10 Oct 2017 08:00:45 +0000 (08:00 +0000)]
Re-land "[MergeICmps] Disable mergeicmps if the target does not want to handle memcmp expansion."
(fixed stability issues)
This reverts commit
d6492333d3b478a1d88163315002022f8d5e58dc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315281
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Bjorn Steinbrink [Tue, 10 Oct 2017 07:46:17 +0000 (07:46 +0000)]
Ignore all duplicate frame index expression
Some passes might duplicate calls to llvm.dbg.declare creating
duplicate frame index expression which currently trigger an assertion
which is meant to catch erroneous, overlapping fragment declarations.
But identical frame index expressions are just redundant and don't
actually conflict with each other, so we can be more lenient and just
ignore the duplicates.
Reviewers: aprantl, rnk
Subscribers: llvm-commits, JDevlieghere
Differential Revision: https://reviews.llvm.org/D38540
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315279
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Alex Bradbury [Tue, 10 Oct 2017 07:19:18 +0000 (07:19 +0000)]
[RISCV] Fix build after r315254
createELFObjectWriter now takes a std::unique_ptr<MCELFObjectTargetWriter>
rather than a MCELFObjectTargetWriter*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315275
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Craig Topper [Tue, 10 Oct 2017 06:36:46 +0000 (06:36 +0000)]
[AVX512] Add patterns to commute integer comparison instructions during isel.
This enables broadcast loads to be commuted and allows normal loads to be folded without the peephole pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315274
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Xinliang David Li [Tue, 10 Oct 2017 05:07:54 +0000 (05:07 +0000)]
Renable r314928
Eliminate inttype phi with inttoptr/ptrtoint.
This version fixed a bug in finding the matching
phi -- the order of the incoming blocks may be
different (triggered in self build on Windows).
A new test case is added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315272
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Reid Kleckner [Tue, 10 Oct 2017 01:49:21 +0000 (01:49 +0000)]
[MC] Properly diagnose badly scoped .cfi_ directives
Removes two report_fatal_errors.
Implement this by removing EmitCFICommon, and do the checking in
getCurrentDwarfFrameInfo. Have the callers check for null before
dereferencing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315264
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Reid Kleckner [Tue, 10 Oct 2017 01:34:31 +0000 (01:34 +0000)]
Give a test a triple
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315263
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Reid Kleckner [Tue, 10 Oct 2017 01:26:25 +0000 (01:26 +0000)]
[SEH] Use reportError instead of report_fatal_error for bad directives
This makes the .seh_ directives slightly more usable from standalone
assembly files.
This removes a large number of report_fatal_errors and recovers from the
error by ignoring the directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315262
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Lang Hames [Tue, 10 Oct 2017 01:15:10 +0000 (01:15 +0000)]
[MC] Plumb unique_ptr<MCWasmObjectTargetWriter> through createWasmObjectWriter
to WasmObjectWriter's constructor.
Fixes the same ownership issue for COFF that r315245 did for MachO:
WasmObjectWriter takes ownership of its MCWasmObjectTargetWriter, so we want to
pass this through to the constructor via a unique_ptr, rather than a raw ptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315260
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Reid Kleckner [Tue, 10 Oct 2017 00:57:36 +0000 (00:57 +0000)]
[MC] Suppress .Lcfi labels when emitting textual assembly
Summary:
This suppresses the generation of .Lcfi labels in our textual assembler.
It was annoying that this generated cascading .Lcfi labels:
llc foo.ll -o - | llvm-mc | llvm-mc
After three trips through MCAsmStreamer, we'd have three labels in the
output when none are necessary. We should only bother creating the
labels and frame data when making a real object file.
This supercedes D38605, which moved the entire .seh_ implementation into
MCObjectStreamer.
This has the advantage that we do more checking when emitting textual
assembly, as a minor efficiency cost. Outputting textual assembly is not
performance critical, so this shouldn't matter.
Reviewers: majnemer, MatzeB
Subscribers: qcolombet, nemanjai, javed.absar, eraman, hiraditya, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D38638
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315259
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Reid Kleckner [Tue, 10 Oct 2017 00:52:40 +0000 (00:52 +0000)]
Fix Wasm build after r315254
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315258
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Lang Hames [Tue, 10 Oct 2017 00:50:29 +0000 (00:50 +0000)]
[MC] Plumb unique_ptr<MCWinCOFFObjectTargetWriter> through
createWinCOFFObjectWriter to WinCOFFObjectWriter's constructor.
Fixes the same ownership issue for COFF that r315245 did for MachO:
WinCOFFObjectWriter takes ownership of its MCWinCOFFObjectTargetWriter, so we
want to pass this through to the constructor via a unique_ptr, rather than a
raw ptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315257
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Lang Hames [Mon, 9 Oct 2017 23:53:15 +0000 (23:53 +0000)]
[MC] Plumb unique_ptr<MCELFObjectTargetWriter> through createELFObjectWriter to
ELFObjectWriter's constructor.
Fixes the same ownership issue for ELF that r315245 did for MachO:
ELFObjectWriter takes ownership of its MCELFObjectTargetWriter, so we want to
pass this through to the constructor via a unique_ptr, rather than a raw ptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315254
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Adam Nemet [Mon, 9 Oct 2017 23:19:02 +0000 (23:19 +0000)]
Rename OptimizationDiagnosticInfo.* to OptimizationRemarkEmitter.*
Sync it up with the name of the class actually defined here. This has been
bothering me for a while...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315249
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Zachary Turner [Mon, 9 Oct 2017 22:59:40 +0000 (22:59 +0000)]
[llvm-rc] Try again to fix errors on big endian systems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315248
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Eugene Zemtsov [Mon, 9 Oct 2017 22:43:35 +0000 (22:43 +0000)]
Fix LLDB build for Android.
Currently libstdc++ on Android doesn't support std::to_string().
Differential Revision: https://reviews.llvm.org/D38701
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315246
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Lang Hames [Mon, 9 Oct 2017 22:38:13 +0000 (22:38 +0000)]
[MC] Plumb unique_ptr<MCMachObjectTargetWriter> through createMachObjectWriter
to MCObjectWriter's constructor.
MCObjectWriter takes ownership of its MCMachObjectTargetWriter argument -- this
patch plumbs that ownership relationship through the constructor (which
previously took raw MCMachObjectTargetWriter*) and the createMachObjectWriter
function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315245
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Jonas Devlieghere [Mon, 9 Oct 2017 22:33:53 +0000 (22:33 +0000)]
[DWARF] DW_TAG_imported_unit is not a unit type.
As pointed out by David in D38453 and confirmed with the DWARF mailing
list, DW_TAG_imported_unit is not a valid unit type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315244
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Francis Ricci [Mon, 9 Oct 2017 20:27:14 +0000 (20:27 +0000)]
[llvm-objdump] Use initializer list for scoped xar api constructors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315243
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Aditya Nandakumar [Mon, 9 Oct 2017 20:07:43 +0000 (20:07 +0000)]
[GISel]: Fix generation of illegal COPYs during CallLowering
We end up creating COPY's that are either truncating/extending and this
should be illegal.
https://reviews.llvm.org/D37640
Patch for X86 and ARM by igorb, rovka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315240
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Aditya Nandakumar [Mon, 9 Oct 2017 20:07:41 +0000 (20:07 +0000)]
Add a helper to build Copy instructions in MachineIRBuilder
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315239
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Zvi Rackover [Mon, 9 Oct 2017 20:01:10 +0000 (20:01 +0000)]
[X86] Unsigned saturation subtraction canonicalization [the backend part]
Summary:
On behalf of julia.koval@intel.com
The patch transforms canonical version of unsigned saturation, which is sub(max(a,b),a) or sub(a,min(a,b)) to special psubus insturuction on targets, which support it(8bit and 16bit uints).
umax(a,b) - b -> subus(a,b)
a - umin(a,b) -> subus(a,b)
There is also extra case handled, when right part of sub is 32 bit and can be truncated, using UMIN(this transformation was discussed in https://reviews.llvm.org/D25987).
The example of special case code:
```
void foo(unsigned short *p, int max, int n) {
int i;
unsigned m;
for (i = 0; i < n; i++) {
m = *--p;
*p = (unsigned short)(m >= max ? m-max : 0);
}
}
```
Max in this example is truncated to max_short value, if it is greater than m, or just truncated to 16 bit, if it is not. It is vaid transformation, because if max > max_short, result of the expression will be zero.
Here is the table of types, I try to support, special case items are bold:
| Size | 128 | 256 | 512
| ----- | ----- | ----- | -----
| i8 | v16i8 | v32i8 | v64i8
| i16 | v8i16 | v16i16 | v32i16
| i32 | | **v8i32** | **v16i32**
| i64 | | | **v8i64**
Reviewers: zvi, spatel, DavidKreitzer, RKSimon
Reviewed By: zvi
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37534
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315237
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Mon, 9 Oct 2017 19:08:15 +0000 (19:08 +0000)]
[SLP] Add test for reversed load, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315232
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Mon, 9 Oct 2017 18:50:29 +0000 (18:50 +0000)]
Fix some C++ value / reference semantics issues.
Some functions were taking Twine's not by const&, these are all
fixed to take by const&. We also had a case where some functions
were overloaded to accept by const& and &&. Now there is only
one version which accepts by value and move's the value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315229
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Mon, 9 Oct 2017 18:14:53 +0000 (18:14 +0000)]
[globalisel] Add support for ValueType operands in patterns.
It's rare but there are a small number of patterns like this:
(set i64:$dst, (add i64:$src1, i64:$src2))
These should be equivalent to register classes except they shouldn't check for
a specific register bank.
This doesn't occur in AArch64/ARM/X86 but does occasionally come up in other
in-tree targets such as BPF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315226
91177308-0d34-0410-b5e6-
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Lang Hames [Mon, 9 Oct 2017 18:11:04 +0000 (18:11 +0000)]
[MC] Use a unique_ptr<MCAssembler> for MCObjectStreamer's Assembler member.
Removes manual new/delete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315225
91177308-0d34-0410-b5e6-
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Sanjay Patel [Mon, 9 Oct 2017 17:54:46 +0000 (17:54 +0000)]
[InstCombine] fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315223
91177308-0d34-0410-b5e6-
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Adrian McCarthy [Mon, 9 Oct 2017 17:50:01 +0000 (17:50 +0000)]
Fix after r315079
Microsoft's debug implementation of std::copy checks if the destination is an
array and then does some bounds checking. This was causing an assertion
failure in fs::rename_internal which copies to a buffer of the appropriate
size but that's type-punned to an array of length 1 for API compatibility
reasons.
Fix is to make make the destination a pointer rather than an array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315222
91177308-0d34-0410-b5e6-
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Francis Ricci [Mon, 9 Oct 2017 17:27:47 +0000 (17:27 +0000)]
[dsymutil] Emit valid debug locations when no symbol flags are set
Summary:
swiftc emits symbols without flags set, which led dsymutil to ignore
them when searching for global symbols, causing dwarf location data
to be omitted. Xcode's dsymutil handles this case correctly, and emits
valid location data. Add this functionality to llvm-dsymutil by
allowing parsing of symbols with no flags set.
Reviewers: aprantl, friss, JDevlieghere
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315218
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Mon, 9 Oct 2017 17:14:03 +0000 (17:14 +0000)]
[SLP] Test for wrongly vectorized set of extractelements, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315217
91177308-0d34-0410-b5e6-
96231b3b80d8
Javed Absar [Mon, 9 Oct 2017 16:21:25 +0000 (16:21 +0000)]
[TableGen] remove make_range where not necessary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315209
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Mon, 9 Oct 2017 15:46:13 +0000 (15:46 +0000)]
[llvm-rc] Have the tokenizer discard single & block comments.
This allows rc files to have comments. Eventually we should
just use clang's c preprocessor, but that's a bit larger
effort for minimal gain, and this is straightforward.
Differential Revision: https://reviews.llvm.org/D38651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315207
91177308-0d34-0410-b5e6-
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Sanjay Patel [Mon, 9 Oct 2017 15:22:20 +0000 (15:22 +0000)]
[DAG] combine assertsexts around a trunc
This was a suggested follow-up to:
D37017 / https://reviews.llvm.org/rL313577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315206
91177308-0d34-0410-b5e6-
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Amara Emerson [Mon, 9 Oct 2017 15:15:09 +0000 (15:15 +0000)]
[AArch64] Improve codegen for inverted overflow checking intrinsics
E.g. if we have a (xor(overflow-bit), 1) where overflow-bit comes from an
intrinsic like llvm.sadd.with.overflow then we can kill the xor and use the
inverted condition code for the CSEL.
rdar://
28495949
Reviewed By: kristof.beyls
Differential Revision: https://reviews.llvm.org/D38160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315205
91177308-0d34-0410-b5e6-
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Sanjay Patel [Mon, 9 Oct 2017 15:01:58 +0000 (15:01 +0000)]
[x86] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315204
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Mon, 9 Oct 2017 01:29:54 +0000 (01:29 +0000)]
[AArch64] fix typos in test assertions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315203
91177308-0d34-0410-b5e6-
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Craig Topper [Mon, 9 Oct 2017 01:05:16 +0000 (01:05 +0000)]
[X86] Remove a setLoadExtAction from the AVX512 section that uses an AVX512BW type and is alraedy present in the AVX512BW section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315202
91177308-0d34-0410-b5e6-
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Craig Topper [Mon, 9 Oct 2017 01:05:15 +0000 (01:05 +0000)]
[X86] Enable extended comparison predicate support for SETUEQ/SETONE when targeting AVX instructions.
We believe that despite AMD's documentation, that they really do support all 32 comparision predicates under AVX.
Differential Revision: https://reviews.llvm.org/D38609
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315201
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Sun, 8 Oct 2017 21:23:02 +0000 (21:23 +0000)]
Remove unused variables. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315196
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 8 Oct 2017 20:58:14 +0000 (20:58 +0000)]
[X86][SSE] Don't call combineTo inside combineX86ShufflesRecursively. NFCI.
Return the combined shuffle from combineX86ShufflesRecursively and perform the combineTo in the caller.
Makes it easier for future patches to use this in functions that aren't actually shuffles themselves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315195
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 8 Oct 2017 19:24:30 +0000 (19:24 +0000)]
Tidyup with clang-format. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315187
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 8 Oct 2017 19:18:10 +0000 (19:18 +0000)]
[X86][SSE] Add test case for PR27708
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315186
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Sun, 8 Oct 2017 19:11:02 +0000 (19:11 +0000)]
Remove unused variables. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315185
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 8 Oct 2017 17:54:50 +0000 (17:54 +0000)]
[X86] Regenerate fast-isel-select-pseudo-cmov.ll to prepare for D38609.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315184
91177308-0d34-0410-b5e6-
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Javed Absar [Sun, 8 Oct 2017 17:23:30 +0000 (17:23 +0000)]
[TableGen] Simplify, add range_loop in CodeGenSchedule
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315183
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 8 Oct 2017 17:21:18 +0000 (17:21 +0000)]
[X86] getTargetConstantBitsFromNode - add support for decoding scalar constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315182
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 8 Oct 2017 16:57:23 +0000 (16:57 +0000)]
[X86] Prefer MOVSS/SD over BLENDI during legalization. Remove BLENDI versions of scalar arithmetic patterns
Summary:
We currently disable some converting of shuffles to MOVSS/MOVSD during legalization if SSE41 is enabled. But later during shuffle combining we go back to prefering MOVSS/MOVSD.
Additionally we have patterns that look for BLENDIs to detect scalar arithmetic operations. I believe due to the combining using MOVSS/MOVSD these are unnecessary.
Interestingly, we still codegen blend instructions even though lowering/isel emit movss/movsd instructions. Turns out machine CSE commutes them to blend, and then commuting those blends back into blends that are equivalent to the original movss/movsd.
This patch fixes the inconsistency in legalization to prefer MOVSS/MOVSD. The one test change was caused by this change. The problem is that we have integer types and are mostly selecting integer instructions except for the shufps. This shufps forced the execution domain, but the vpblendw couldn't have its domain changed with a naive instruction swap. We could fix this by special casing VPBLENDW based on the immediate to widen the element type.
The rest of the patch is removing all the excess scalar patterns.
Long term we should probably add isel patterns to make MOVSS/MOVSD emit blends directly instead of relying on the double commute. We may also want to consider emitting movss/movsd for optsize. I also wonder if we should still use the VEX encoded blendi instructions even with AVX512. Blends have better throughput, and that may outweigh the register constraint.
Reviewers: RKSimon, zvi
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315181
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Benjamin Kramer [Sun, 8 Oct 2017 15:59:35 +0000 (15:59 +0000)]
Make more constructors constexpr or use =default.
This lets the compiler reason about the type more easily. No
functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315180
91177308-0d34-0410-b5e6-
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Amara Emerson [Sun, 8 Oct 2017 15:29:35 +0000 (15:29 +0000)]
[AArch64][GlobalISel] Add a test case for G_PHI of p0 instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315179
91177308-0d34-0410-b5e6-
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Amara Emerson [Sun, 8 Oct 2017 15:29:31 +0000 (15:29 +0000)]
[AArch64][GlobalISel] Add a test case for G_PHI of p0 regbank selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315178
91177308-0d34-0410-b5e6-
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Amara Emerson [Sun, 8 Oct 2017 15:29:11 +0000 (15:29 +0000)]
[AArch64][GlobalISel] Make G_PHI of p0 types legal.
Differential Revision: https://reviews.llvm.org/D38621
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315177
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 8 Oct 2017 12:58:15 +0000 (12:58 +0000)]
[X86][XOP] Add XOP oddshuffles tests
XOP codegen is often different to generic AVX - thank you vpperm!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315176
91177308-0d34-0410-b5e6-
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Gadi Haber [Sun, 8 Oct 2017 12:52:54 +0000 (12:52 +0000)]
[X86][SKX] Adding the scheduling information for the SKX target.
Adding the scheduling information for the SkylakeServer (SKX) target.
This patch adds the instruction scheduling information for the SkylakeServer (SKX) architecture target by adding the file X86SchedSkylakeServer.td located under the X86 Target.
We used the scheduling information retrieved from the Skylake architects in order to create the file.
The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction.
The patch continues the scheduling replacement and insertion effort started with the SNB target in r310792, the HSW target in r311879 and the SkylakeClient (SKL) target in rL313613.
Please expect some performance fluctuations due to code alignment effects.
Reviewers: zvi, RKSimon, craig.topper, chandlerc, aymanmu
Differential Revision: https://reviews.llvm.org/D38443
Change-Id: I5c228fcc09e9e5a99b6116e62b356c4f9b971185
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315175
91177308-0d34-0410-b5e6-
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Ayman Musa [Sun, 8 Oct 2017 09:46:50 +0000 (09:46 +0000)]
[X86] Add missing entries in 'MemoryFoldTable2Addr' to get complete form of the table.
Get the folding table 'MemoryFoldTable2Addr' to a complete state as part of the process explained in https://reviews.llvm.org/D38028
Differential Revision: https://reviews.llvm.org/D38500
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315174
91177308-0d34-0410-b5e6-
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Ayman Musa [Sun, 8 Oct 2017 09:20:32 +0000 (09:20 +0000)]
[X86][TableGen] Recommitting the X86 memory folding tables TableGen backend while disabling it by default.
After the original commit ([[ https://reviews.llvm.org/rL304088 | rL304088 ]]) was reverted, a discussion in llvm-dev was opened on 'how to accomplish this task'.
In the discussion we concluded that the best way to achieve our goal (which is to automate the folding tables and remove the manually maintained tables) is:
# Commit the tablegen backend disabled by default.
# Proceed with an incremental updating of the manual tables - while checking the validity of each added entry.
# Repeat previous step until we reach a state where the generated and the manual tables are identical. Then we can safely remove the manual tables and include the generated tables instead.
# Schedule periodical (1 week/2 weeks/1 month) runs of the pass:
- if changes appear (new entries):
- make sure the entries are legal
- If they are not, mark them as illegal to folding
- Commit the changes (if there are any).
CMake flag added for this purpose is "X86_GEN_FOLD_TABLES". Building with this flags will run the pass and emit the X86GenFoldTables.inc file under build/lib/Target/X86/ directory which is a good reference for any developer who wants to take part in the effort of completing the current folding tables.
Differential Revision: https://reviews.llvm.org/D38028
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315173
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 8 Oct 2017 08:50:59 +0000 (08:50 +0000)]
[X86] Stop LowerSIGN_EXTEND_AVX512 from creating v8i16/v16i16/v16i8 vselects with a v8i1/v16i1 condition when BWI is not available.
Some of the tests in vector-shuffle-v1.ll would get into an infinite loop without this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315172
91177308-0d34-0410-b5e6-
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Ayman Musa [Sun, 8 Oct 2017 08:32:56 +0000 (08:32 +0000)]
[X86] Add new attribute to X86 instructions to enable marking them as "not memory foldable"
This attribute will be used in a tablegen backend that generated the X86 memory folding tables which will be added in a future pass.
Instructions with this attribute unset will be excluded from the full set of X86 instructions available for the pass.
Differential Revision: https://reviews.llvm.org/D38027
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315171
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 8 Oct 2017 01:33:42 +0000 (01:33 +0000)]
[X86] Simplify some code in getInsertVINSERTImmediate and getExtractVEXTRACTImmediate. NFC
Replace one of the divides with a multiply.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315162
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 8 Oct 2017 01:33:41 +0000 (01:33 +0000)]
[X86] If we see an insert of a bitcast into zero vector, canonicalize it to move the bitcast to the other side of the insert.
This improves detection of zeroing of upper bits during isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315161
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 8 Oct 2017 01:33:40 +0000 (01:33 +0000)]
[X86] Remove ISD::INSERT_SUBVECTOR handling from combineBitcastForMaskedOp. Add isel patterns to make up for it.
This will allow for some flexibility in canonicalizing bitcasts around insert_subvector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315160
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 8 Oct 2017 01:33:38 +0000 (01:33 +0000)]
[X86] Use getConstantOperandVal to simplify some code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315159
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sat, 7 Oct 2017 17:57:22 +0000 (17:57 +0000)]
[X86][SSE] Match bitcasted BUILD_VECTOR of constants for v2i64 shifts on 64-bit targets (PR34855)
Extension to rL315155, generate constant shifts on 64-bits as well as 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315156
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sat, 7 Oct 2017 17:42:17 +0000 (17:42 +0000)]
[X86][SSE] Match bitcasted v4i32 BUILD_VECTORS for v2i64 shifts on 64-bit targets (PR34855)
We were already doing this for 32-bit targets, but we can generate these on 64-bits as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315155
91177308-0d34-0410-b5e6-
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Craig Topper [Sat, 7 Oct 2017 17:07:48 +0000 (17:07 +0000)]
[SelectionDAG} Use KnownBits::isUnknown and hasConflict. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315154
91177308-0d34-0410-b5e6-
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Craig Topper [Sat, 7 Oct 2017 16:51:19 +0000 (16:51 +0000)]
[X86] Add X86ISD::CMOV to computeKnownBitsForTargetNode and ComputeNumSignBitsForTargetNode.
Summary: Implementations based on ISD::SELECT.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315153
91177308-0d34-0410-b5e6-
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Sanjay Patel [Sat, 7 Oct 2017 15:39:06 +0000 (15:39 +0000)]
[InstSimplify] add tests to show we can do better at folding poison; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315152
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sat, 7 Oct 2017 14:34:24 +0000 (14:34 +0000)]
[TableGen] Avoid repeated find calls in CodeGenDAGPatterns getters. NFCI.
The assertion tests were using count() instead of testing the find result, resulting in double the number of searches in debug/assert builds.
Instead, call find once (like the release builds do) and assert the result against end().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315151
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sat, 7 Oct 2017 12:42:23 +0000 (12:42 +0000)]
[X86][SSE] Improve shuffling combining with horizontal operations
Recognise cases when we can merge the shuffles with their horizontal (HADD/HSUB/PACK) instruction inputs.
Replaces an older implementation which performed some of this during lowering, expanding an existing target shuffle combine stage instead.
Differential Revision: https://reviews.llvm.org/D38506
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315150
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sat, 7 Oct 2017 12:08:43 +0000 (12:08 +0000)]
[TableGen] Avoid unnecessary std::string creations
Avoid unnecessary std::string creations in the TreePredicateFn getters and in CodeGenDAGPatterns::getSDNodeNamed
Differential Revision: https://reviews.llvm.org/D38624
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315148
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Martin Storsjo [Sat, 7 Oct 2017 06:00:32 +0000 (06:00 +0000)]
[X86] Update an outdated comment about SjLj
The SjLj intrinsics in the X86 backend are intended for use with
SjLj exception handling as well, since SVN r271244.
Differential Revision: https://reviews.llvm.org/D38532
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315146
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Craig Topper [Sat, 7 Oct 2017 05:11:59 +0000 (05:11 +0000)]
[X86] Correct result type for the flag result of RDSEED and RDRAND nodes. Correct the CC type for the CMOV used with RDSEED/RDRAND.
The flag result was MVT::Glue, but should be MVT::i32. The CC type was MVT::i8, but should be MVT::i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315145
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Jessica Paquette [Sat, 7 Oct 2017 00:16:34 +0000 (00:16 +0000)]
[MachineOutliner] Disable outlining from LinkOnceODRs by default
Say you have two identical linkonceodr functions, one in M1 and one in M2.
Say that the outliner outlines A,B,C from one function, and D,E,F from another
function (where letters are instructions). Now those functions are not
identical, and cannot be deduped. Locally to M1 and M2, these outlining
choices would be good-- to the whole program, however, this might not be true!
To mitigate this, this commit makes it so that the outliner sees linkonceodr
functions as unsafe to outline from. It also adds a flag,
-enable-linkonceodr-outlining, which allows the user to specify that they
want to outline from such functions when they know what they're doing.
Changing this handles most code size regressions in the test suite caused by
competing with linker dedupe. It also doesn't have a huge impact on the code
size improvements from the outliner. There are 6 tests that regress > 5% from
outlining WITH linkonceodrs to outlining WITHOUT linkonceodrs. Overall, most
tests either improve or are not impacted.
Not outlined vs outlined without linkonceodrs:
https://hastebin.com/raw/qeguxavuda
Not outlined vs outlined with linkonceodrs:
https://hastebin.com/raw/edepoqoqic
Outlined with linkonceodrs vs outlined without linkonceodrs:
https://hastebin.com/raw/awiqifiheb
Numbers generated using compare.py with -m size.__text. Tests run for AArch64
with -Oz -mllvm -enable-machine-outliner -mno-red-zone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315136
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Sanjay Patel [Fri, 6 Oct 2017 23:43:06 +0000 (23:43 +0000)]
[InstCombine] use correct type when propagating constant condition in simplifyDivRemOfSelectWithZeroOp (PR34856)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315130
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Zachary Turner [Fri, 6 Oct 2017 23:21:43 +0000 (23:21 +0000)]
[llvm-rc] Fix some endianness errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315128
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Sanjay Patel [Fri, 6 Oct 2017 23:20:16 +0000 (23:20 +0000)]
[InstCombine] rename SimplifyDivRemOfSelect to be clearer, add comments, simplify code; NFCI
There's at least one bug here - this code can fail with vector types (PR34856).
It's also being called for FREM; I'm still trying to understand how that is valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315127
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Cameron McInally [Fri, 6 Oct 2017 22:31:29 +0000 (22:31 +0000)]
[AVX512] Fix TERNLOG when folding broadcast
Patch to fix ternlog instructions with a folded
broadcast. The broadcast decorator, e.g. {1toX}, was missing.
Differential Revision: https://reviews.llvm.org/D38649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315122
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Jonas Devlieghere [Fri, 6 Oct 2017 22:27:31 +0000 (22:27 +0000)]
[dwarfdump] Verify that unit type matches root DIE
This patch adds two new verifiers:
- It checks that the root DIE of a CU is actually a valid unit DIE.
(based on its tag)
- For DWARF5 which contains a unit type int he CU header, it checks that
this matches the type of the unit DIE.
Differential revision: https://reviews.llvm.org/D38453
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315121
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