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Dorit Nuzman [Tue, 20 Sep 2016 07:50:49 +0000 (07:50 +0000)]
[SROA] Preserve llvm.mem.parallel_loop_access metadata.
SROA doesn't preserve the llvm.mem.parallel_loop_access metadata when it
transforms loads/stores. This patch fixes a couple occurences of this
issue.
(Partially addresses PR28981).
Differential Revision: https://reviews.llvm.org/D23549
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281960
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Craig Topper [Tue, 20 Sep 2016 06:49:17 +0000 (06:49 +0000)]
[AVX-512] Teach X86InstrInfo::copyPhysReg to use a 512-bit move if XMM16-XMM31 or YMM16-YMM31 are the source or dest of the copy and VLX is not supported.
This can happen with SUBREG_TO_REG of ZMM16-ZMM31. Fixes PR30430.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281959
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Craig Topper [Tue, 20 Sep 2016 05:44:47 +0000 (05:44 +0000)]
[AVX-512] Use 512-bit vcvtps2ph/vcvtph2ps to implement fp_to_f16/f16_to_fp when F16C and VLX are not supported.
Fixes PR23941.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281958
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Matthias Braun [Tue, 20 Sep 2016 01:14:42 +0000 (01:14 +0000)]
BranchFolder: Fix invalid undef flags after merge.
It is legal to merge instructions with different undef flags; However we
must drop the undef flag from the merged instruction if it isn't present
everywhere.
This fixes http://llvm.org/PR30199
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281957
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Matthias Braun [Tue, 20 Sep 2016 01:14:39 +0000 (01:14 +0000)]
Machine{Instr|Operand}: Clarify some isIdenticalTo() subtleties.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281956
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Quentin Colombet [Tue, 20 Sep 2016 00:48:44 +0000 (00:48 +0000)]
[RegisterBankInfo] Avoid heap allocation in InstructionMapping.
Use SmallVector instead of dynamically allocated arrays for the mapping of the
operands in the InstructionMapping. That way we avoid heap allocation for most
of the cases. Ultimately, we should not have to rely on such tricky, the
instances of InstructionMapping would be TableGen'ed.
This improves the compilation time of the RegBankSelect pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281955
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Sanjay Patel [Tue, 20 Sep 2016 00:27:22 +0000 (00:27 +0000)]
[x86] fix variable names; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281953
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Kostya Serebryany [Tue, 20 Sep 2016 00:16:54 +0000 (00:16 +0000)]
[sanitizer-coverage] add comdat to coverage guards if needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281952
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Sanjay Patel [Mon, 19 Sep 2016 23:44:50 +0000 (23:44 +0000)]
[x86] auto-generate checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281950
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Philip Reames [Mon, 19 Sep 2016 23:30:23 +0000 (23:30 +0000)]
[LCSSA] Cache LoopExits to avoid wasted work
When looking at the scribus_1.3 example from https://llvm.org/bugs/show_bug.cgi?id=10584, I noticed that we were spending a large amount of time computing loop exits in LCSSA. This code appears to be written with the assumption that LoopExits are stored in the Loop and thus cheap to query. This is not true, so we should cache the result across the potentially long running loop which tends to visit a small handful of Loops.
On the particular example from 10584, this change drops the time spent in LCSSA computation by about 80%.
Differential Revision: https://reviews.llvm.org/D24509
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281949
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Quentin Colombet [Mon, 19 Sep 2016 23:18:47 +0000 (23:18 +0000)]
[RegisterBankInfo] Adapt call to std::fill due to use of SmallVector.
This was meant to be commited with my previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281948
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David Callahan [Mon, 19 Sep 2016 23:17:58 +0000 (23:17 +0000)]
Merge branch 'ADCE5'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281947
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Lang Hames [Mon, 19 Sep 2016 23:00:27 +0000 (23:00 +0000)]
[Kaleidoscope] Make Chapter 2 use llvm::make_unique, rather than a helper.
This essentially reverts r251936, minimizing the difference between Chapter2
and Chapter 3, and making Chapter 2's code match the tutorial text.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281945
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Sanjay Patel [Mon, 19 Sep 2016 22:07:27 +0000 (22:07 +0000)]
[x86] use getSignBit() to simplify code; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281944
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Eric Christopher [Mon, 19 Sep 2016 21:55:04 +0000 (21:55 +0000)]
Move the armv8.1-a ras test to a negative with noras test as ras is
included in armv8.1-a by default and so we weren't testing anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281941
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Mehdi Amini [Mon, 19 Sep 2016 21:27:04 +0000 (21:27 +0000)]
BitcodeWriter: fix emission of invoke when calling a var-arg function with operand bundles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281940
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Evgeniy Stepanov [Mon, 19 Sep 2016 21:26:05 +0000 (21:26 +0000)]
Misleading comments of SplitBlockAndInsertIfThenElse in BasicBlockUtils.h
The comments of SplitBlockAndInsertIfThenElse say the SplitBefore instruction will stay in the old block.
But according to the implementation(split the block at SplitBefore by using splitBasicBlock), the SplitBefore will be moved to the new block.
This patch fixes the comments.
Patch by Zhe Yu Wu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281939
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Simon Pilgrim [Mon, 19 Sep 2016 20:50:35 +0000 (20:50 +0000)]
[X86][SSE] Updated vector abs tests
Renamed and added v2i64 / v4i64 tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281937
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Kostya Serebryany [Mon, 19 Sep 2016 20:32:34 +0000 (20:32 +0000)]
[libFuzzer] use sleep() instead of std::this_thread::sleep_for to avoid coverage from instrumented libc++
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281933
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Dehao Chen [Mon, 19 Sep 2016 18:38:14 +0000 (18:38 +0000)]
Handle early inline for hot callsites that reside in the same basic block.
Summary: Callsites in the same basic block should share the same hotness. This patch checks for the hottest callsite in the same basic block, and use the hotness for all callsites in that basic block for early inline decisions. It also fixes the test to add "-S" so theat the "CHECK-NOT" is actually checking the content.
Reviewers: dnovillo
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D24734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281927
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Quentin Colombet [Mon, 19 Sep 2016 17:33:55 +0000 (17:33 +0000)]
[RegisterBankInfo] Avoid heap allocation in most cases.
The OperandsMapper class is used heavy in RegBankSelect and each
instantiation triggered a heap allocation for the array of operands.
Instead, use a SmallVector with a big enough size such that most of the
cases do not have to use dynamically allocated memory.
This improves the compile time of the RegBankSelect pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281916
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Matthias Braun [Mon, 19 Sep 2016 16:49:45 +0000 (16:49 +0000)]
LiveRangeCalc: Fix reporting of invalid vreg usage in liveness calculation
Machine programs need a definition of each vreg before reaching a use
(the definition may come from an IMPLICIT_DEF instruction). This class
of errors is not detected by the MachineVerifier because of efficiency
concerns. LiveRangeCalc used to report these problems, make it do that
again (followup to r279625).
Also use report_fatal_error() instead of llvm_unreachable() as the error
reporting is only present in asserts build anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281914
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Dehao Chen [Mon, 19 Sep 2016 16:33:41 +0000 (16:33 +0000)]
Only set branch weight during sample pgo annotation when max_weight of the branch is non-zero. Otherwise use default static profile to set branch probability.
Summary: It does not make sense to set equal weights for all unkown branches as we have static branch prediction available.
Reviewers: dnovillo
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D24732
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281912
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Dehao Chen [Mon, 19 Sep 2016 16:06:37 +0000 (16:06 +0000)]
Use call target count to derive the call instruction weight
Summary: The call target count profile is directly derived from LBR branch->target data. This is more reliable than instruction frequency profiles that could be moved across basic block boundaries. This patches uses call target count profile to annotate call instructions.
Reviewers: davidxl, dnovillo
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D24410
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281911
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Etienne Bergeron [Mon, 19 Sep 2016 15:58:38 +0000 (15:58 +0000)]
[asan] Support dynamic shadow address instrumentation
Summary:
This patch is adding the support for a shadow memory with
dynamically allocated address range.
The compiler-rt needs to export a symbol containing the shadow
memory range.
This is required to support ASAN on windows 64-bits.
Reviewers: kcc, rnk, vitalybuka
Subscribers: kubabrecka, dberris, llvm-commits, chrisha
Differential Revision: https://reviews.llvm.org/D23354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281908
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Zachary Turner [Mon, 19 Sep 2016 15:34:51 +0000 (15:34 +0000)]
[Support] Add StringRef::withNullAsEmpty()
When porting large bodies of code from using const char*
to StringRef, it is helpful to be able to treat nullptr
as an empty string, since that it is often what it is used
to indicate in C-style code.
Differential Revision: https://reviews.llvm.org/D24697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281906
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Nico Weber [Mon, 19 Sep 2016 15:22:04 +0000 (15:22 +0000)]
Revert r281841, it does not work on Windows (PR30443).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281905
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Valery Pykhtin [Mon, 19 Sep 2016 14:39:49 +0000 (14:39 +0000)]
[AMDGPU] Refactor VOPC instruction TD definitions
Differential Revision: https://reviews.llvm.org/D24546
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281903
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Diana Picus [Mon, 19 Sep 2016 11:10:18 +0000 (11:10 +0000)]
[AArch64] Fix encoding for lsl #12 in add/sub immediates
Whenever an add/sub immediate needs a fixup, we set that immediate field to zero,
which is correct, but we also set the shift bits to zero, which is not true for
instructions that use lsl #12. This patch makes sure that if lsl #12 was used,
it will appear in the encoding of the instruction.
Differential Revision: https://reviews.llvm.org/D23930
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281898
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Sam Kolton [Mon, 19 Sep 2016 10:20:55 +0000 (10:20 +0000)]
[AMDGPU] Fix s_branch with -1 offset
Summary:
In case s_branch instruction target is itself backend should emit offset -1 but instead it emit 0.
'''
label:
s_branch label // should emit [0xff,0xff,0x82,0xbf]
'''
Tom, Matt: why are we adjusting fixup values in applyFixup() method instead of processFixup()? processFixup() is calling adjustFixupValue() but does nothing with its result.
Reviewers: vpykhtin, artem.tamazov, tstellarAMD
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl
Differential Revision: https://reviews.llvm.org/D24671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281896
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Keith Walker [Mon, 19 Sep 2016 09:49:30 +0000 (09:49 +0000)]
Add @llvm.dbg.value entries for the phi node created by -mem2reg
When phi nodes are created in the -mem2reg phase, the @llvm.dbg.declare
entries are converted to @llvm.dbg.value entries at the place where the
store instructions existed. However no entry is created to describe
the resulting value of the phi node.
The effect of this is especially noticeable in for loops which have a
constant for the intial value; the loop control variable's location
would be described as the intial constant value in the loop body once
the -mem2reg optimization phase was run.
This change adds the creation of the @llvm.dbg.value entries to describe
variables whose location is the result of a phi node created in -mem2reg.
Also when the phi node is finally lowered to a machine instruction it
is important that the lowered "load" instruction is placed before the
associated DEBUG_VALUE entry describing the value loaded.
Differential Revision: https://reviews.llvm.org/D23715
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281895
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Oliver Stannard [Mon, 19 Sep 2016 09:21:45 +0000 (09:21 +0000)]
[Thumb] Set correct initial mapping symbol for big-endian thumb
The initial mapping symbol state is set from the triple, but we only checked
for the little-endian thumb triple, so could end up with an ARM mapping symbol
for big-endian thumb.
Differential Revision: https://reviews.llvm.org/D24553
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281894
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Tim Northover [Mon, 19 Sep 2016 09:11:09 +0000 (09:11 +0000)]
ARM: check alignment before transforming ldr -> ldm (or similar).
ldm and stm instructions always require 4-byte alignment on the pointer, but we
weren't checking this before trying to reduce code-size by replacing a
post-indexed load/store with them. Unfortunately, we were also dropping this
incormation in DAG ISel too, but that's easy enough to fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281893
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Elena Demikhovsky [Mon, 19 Sep 2016 08:58:43 +0000 (08:58 +0000)]
[X86 Codegen Test] Divided masked_memop into several files. NFC.
The masked_memop.ll became huge. I extracted AVX-512 specific tests into separate files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281892
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James Molloy [Mon, 19 Sep 2016 08:23:08 +0000 (08:23 +0000)]
[SimplifyCFG] Update (AND) IR flags when CSE'ing instructions
We were updating metadata but not IR flags. Because we pick an arbitrary instruction to be the CSE candidate, it comes down to luck (50% or less chance) if this results in broken codegen or not, which is why PR30373 which is actually not the fault of the commit it was bisected down to.
Fixes PR30373.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281889
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Craig Topper [Mon, 19 Sep 2016 02:53:43 +0000 (02:53 +0000)]
[X86,AVX-512] Use INSERT_SUBREG instead of SUBREG_TO_REG when the input is not the output of an instruction.
SUBREG_TO_REG is supposed to indicate that the super register has been zeroed, but we can't prove that if we don't know where it came from.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281885
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Craig Topper [Mon, 19 Sep 2016 02:53:37 +0000 (02:53 +0000)]
[AVX-512] Add support for lowering fp_to_f16 and f16_to_fp when VLX is supported regardless of whether F16C is also supported.
Still need to add support for lowering using AVX512F when neither VLX or F16C is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281884
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Vedant Kumar [Mon, 19 Sep 2016 02:15:59 +0000 (02:15 +0000)]
[llvm-cov] Emit a link to some documentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281883
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Vedant Kumar [Mon, 19 Sep 2016 01:46:01 +0000 (01:46 +0000)]
[llvm-cov] Delete the NonCodeLines field, it was always dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281882
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Dean Michael Berris [Mon, 19 Sep 2016 00:54:35 +0000 (00:54 +0000)]
[XRay] ARM 32-bit no-Thumb support in LLVM
This is a port of XRay to ARM 32-bit, without Thumb support yet. The XRay instrumentation support is moving up to AsmPrinter.
This is one of 3 commits to different repositories of XRay ARM port. The other 2 are:
https://reviews.llvm.org/D23932 (Clang test)
https://reviews.llvm.org/D23933 (compiler-rt)
Differential Revision: https://reviews.llvm.org/D23931
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281878
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Vedant Kumar [Mon, 19 Sep 2016 00:38:29 +0000 (00:38 +0000)]
[llvm-cov] Teach the coverage exporter about instantiation coverage
While we're at it, re-use the logic from CoverageReport to compute
summaries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281877
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Vedant Kumar [Mon, 19 Sep 2016 00:38:25 +0000 (00:38 +0000)]
[llvm-cov] Make a helper method static for re-use (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281876
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Vedant Kumar [Mon, 19 Sep 2016 00:38:23 +0000 (00:38 +0000)]
[llvm-cov] Track function and instantiation coverage separately
These are distinct statistics which are useful to look at separately.
Example: say you have a template function "foo" with 5 instantiations
and only 3 of them are covered. Then this contributes (1/1) to the total
function coverage and (3/5) to the total instantiation coverage. I.e,
the old "Function Coverage" column has been renamed to "Instantiation
Coverage", and the new "Function Coverage" aggregates information from
the various instantiations of a function.
One benefit of making this switch is that the Line and Region coverage
columns will start making sense. Let's continue the example and assume
that the 5 instantiations of "foo" cover {2, 4, 6, 8, 10} out of 10
lines respectively. The new line coverage for "foo" is (10/10), not
(30/50). The old scenario got confusing because we'd report that there
were more lines in a file than what was actually possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281875
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Vedant Kumar [Mon, 19 Sep 2016 00:38:18 +0000 (00:38 +0000)]
[llvm-cov] Don't recompute the 'Covered' field from *CoverageInfo (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281874
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Vedant Kumar [Mon, 19 Sep 2016 00:38:16 +0000 (00:38 +0000)]
[llvm-cov] Make 'adjustColumnWidths' do less work
This drops some redundant calls to get{UniqueSourceFiles,
CoveredFunctions}. We can figure out the right column widths without
re-doing this expensive work.
This isn't NFC, but I don't want to check in another binary *.covmapping
file with long filenames in it. I tested this locally on a project with
some long filenames (FileCheck).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281873
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Vedant Kumar [Mon, 19 Sep 2016 00:38:14 +0000 (00:38 +0000)]
[llvm-cov] Drop another redundant 'No.' suffix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281872
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Vedant Kumar [Mon, 19 Sep 2016 00:38:11 +0000 (00:38 +0000)]
[utils] Delete the 'check-coverage-regressions' script
In practice, it's way too noisy.
It's also a maintenance burden, since we apparently can't add tests for
it without breaking some Windows setups (see: D22692).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281871
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Dehao Chen [Sun, 18 Sep 2016 23:11:37 +0000 (23:11 +0000)]
Handle Invoke during sample profiler annotation: make it inlinable.
Summary: Previously we reline on inst-combine to remove inlinable invoke instructions. This causes trouble because a few extra optimizations are schedule early that could introduce too much CFG change (e.g. simplifycfg removes too much control flow). This patch handles invoke instruction in-place during sample profile annotation, so that we do not rely on instcombine to remove those invoke instructions.
Reviewers: davidxl, dnovillo
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D24409
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281870
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Xinliang David Li [Sun, 18 Sep 2016 22:10:19 +0000 (22:10 +0000)]
Extend title underline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281869
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Craig Topper [Sun, 18 Sep 2016 21:49:32 +0000 (21:49 +0000)]
[AVX-512] Don't lower CVTPD2PS intrinsics to ISD::FP_ROUND with an X86 rounding mode encoding in the second operand. This immediate should only be 0 or 1 and indicates if the truncation loses precision.
Also enhance an assert in SelectionDAG::getNode to flag this sort of problem in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281868
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Craig Topper [Sun, 18 Sep 2016 21:49:28 +0000 (21:49 +0000)]
[AVX-512] Stop lowering avx512_mask_sqrt intrinsics to ISD:FSQRT with a second operand containing an X86 specific rounding mode encoding that doesn't belong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281867
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Kostya Serebryany [Sun, 18 Sep 2016 21:47:08 +0000 (21:47 +0000)]
[libFuzzer] add -print_coverage=1 flag to print coverage directly from libFuzzer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281866
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Simon Pilgrim [Sun, 18 Sep 2016 21:08:35 +0000 (21:08 +0000)]
Fix covered-switch-default warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281865
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Simon Pilgrim [Sun, 18 Sep 2016 21:01:20 +0000 (21:01 +0000)]
[CostModel][X86] Added scalar float op costs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281864
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Simon Pilgrim [Sun, 18 Sep 2016 20:25:41 +0000 (20:25 +0000)]
Rename tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281863
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Craig Topper [Sun, 18 Sep 2016 18:59:38 +0000 (18:59 +0000)]
[X86] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281862
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Craig Topper [Sun, 18 Sep 2016 18:59:36 +0000 (18:59 +0000)]
[AVX-512] Add memory load patterns for the legacy SSE scalar fp to integer conversion intrinsics to be consistent across all intruction sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281861
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Craig Topper [Sun, 18 Sep 2016 18:59:33 +0000 (18:59 +0000)]
[AVX-512] Remove COPY_TO_REGCLASS from a few patterns that already had the correct register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281860
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Xinliang David Li [Sun, 18 Sep 2016 18:52:08 +0000 (18:52 +0000)]
Fix built bot failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281859
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Xinliang David Li [Sun, 18 Sep 2016 18:34:07 +0000 (18:34 +0000)]
[Profile] Implement select instruction instrumentation in IR PGO
Differential Revision: http://reviews.llvm.org/D23727
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281858
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Elena Demikhovsky [Sun, 18 Sep 2016 13:56:08 +0000 (13:56 +0000)]
[Loop Vectorizer] Consecutive memory access - fixed and simplified
Amended consecutive memory access detection in Loop Vectorizer.
Load/Store were not handled properly without preceding GEP instruction.
Differential Revision: https://reviews.llvm.org/D20789
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281853
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Simon Pilgrim [Sun, 18 Sep 2016 12:45:23 +0000 (12:45 +0000)]
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp
With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations.
This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware).
While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions.
Differential Revision: https://reviews.llvm.org/D24343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281852
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Elena Demikhovsky [Sun, 18 Sep 2016 09:22:54 +0000 (09:22 +0000)]
[Loop vectorizer] Simplified GEP cloning. NFC.
Simplified GEP cloning in vectorizeMemoryInstruction().
Added an assertion that checks consecutive GEP, which should have only one loop-variant operand.
Differential Revision: https://reviews.llvm.org/D24557
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281851
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Wei Mi [Sun, 18 Sep 2016 06:10:32 +0000 (06:10 +0000)]
Change the order of the splitted store from high - low to low - high.
It is a trivial change which could make the testcase easier to be reused
for the store splitting in CodeGenPrepare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281846
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Kostya Serebryany [Sun, 18 Sep 2016 04:52:23 +0000 (04:52 +0000)]
[libFuzzer] use 'if guard' instead of 'if guard >= 0' with trace-pc; change the guard type to intptr_t; use separate array for 8-bit counters
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281845
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Davide Italiano [Sun, 18 Sep 2016 04:39:15 +0000 (04:39 +0000)]
[llvm-objump] Simplify the code. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281844
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Davide Italiano [Sat, 17 Sep 2016 22:32:42 +0000 (22:32 +0000)]
[lib/LTO] Try harder to reduce code duplication. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281843
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Simon Pilgrim [Sat, 17 Sep 2016 22:02:23 +0000 (22:02 +0000)]
[X86][SSE] Added vector udiv combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281842
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Simon Pilgrim [Sat, 17 Sep 2016 21:31:34 +0000 (21:31 +0000)]
[X86][SSE] Added vector fcopysign combine tests
Also demonstrating the poor lowering of fcopysign...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281841
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Teresa Johnson [Sat, 17 Sep 2016 20:40:16 +0000 (20:40 +0000)]
[ThinLTO] Ensure anonymous globals renamed even at -O0
Summary:
This fixes an issue when files are compiled with -flto=thin
at default -O0. We need to rename anonymous globals before attempting
to write the module summary because all values need names for
the summary. This was happening at -O1 and above, but not before
the early exit when constructing the pipeline for -O0.
Also add an internal -prepare-for-thinlto option to enable this
to be tested via opt.
Fixes PR30419.
Reviewers: mehdi_amini
Subscribers: probinson, llvm-commits, mehdi_amini
Differential Revision: https://reviews.llvm.org/D24701
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281840
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Simon Pilgrim [Sat, 17 Sep 2016 20:06:16 +0000 (20:06 +0000)]
[X86][SSE] Added vector mul combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281839
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Simon Pilgrim [Sat, 17 Sep 2016 18:50:54 +0000 (18:50 +0000)]
[X86][SSE] Improve target shuffle mask extraction
Add ability to extract vXi64 'vzext_movl' masks on 32-bit targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281834
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Simon Pilgrim [Sat, 17 Sep 2016 18:42:41 +0000 (18:42 +0000)]
[X86][AVX] Test target shuffle combining on 32 and 64-bit targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281833
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Simon Pilgrim [Sat, 17 Sep 2016 17:42:15 +0000 (17:42 +0000)]
[X86][AVX2] Add target shuffle constant folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281830
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Simon Pilgrim [Sat, 17 Sep 2016 17:41:14 +0000 (17:41 +0000)]
[X86][AVX] Add target shuffle constant folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281829
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Simon Pilgrim [Sat, 17 Sep 2016 17:40:40 +0000 (17:40 +0000)]
[X86][XOP] Add target shuffle constant folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281828
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Simon Pilgrim [Sat, 17 Sep 2016 17:40:08 +0000 (17:40 +0000)]
[X86][SSSE3] Add target shuffle constant folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281827
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Ron Lieberman [Sat, 17 Sep 2016 16:21:09 +0000 (16:21 +0000)]
[Hexagon] segv while processing SUnit with nullNodePtr
Added BoundaryNode check to isBestZeroLatency function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281825
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Matt Arsenault [Sat, 17 Sep 2016 16:09:55 +0000 (16:09 +0000)]
AMDGPU: Fix broken FrameIndex handling
We were trying to avoid using a FrameIndex operand in non-pointer
operands in a convoluted way, and would break because of
using TargetFrameIndex. The TargetFrameIndex should only be used
in the case where it makes sense to fold it as part of the addressing
mode, otherwise it requires materialization like a normal constant.
This wasn't working reliably and failed in the added testcase, hitting
the assert when processing the frame index.
The TargetFrameIndex was coming from trying to produce an AssertZext
limiting the maximum stack size. I'm not sure this was correct to begin
with, because it is apparently possible to have a single workitem
dispatch that requires all 4G of private memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281824
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Matt Arsenault [Sat, 17 Sep 2016 15:52:37 +0000 (15:52 +0000)]
AMDGPU: Rename spill operands to match real instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281823
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Matt Arsenault [Sat, 17 Sep 2016 15:44:16 +0000 (15:44 +0000)]
AMDGPU: Push bitcasts through build_vector
This reduces the number of copies and reg_sequences
when using fp constant vectors. This significantly
reduces the code size in local-stack-alloc-bug.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281822
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Kostya Serebryany [Sat, 17 Sep 2016 06:01:55 +0000 (06:01 +0000)]
[libFuzzer] properly reset the guards when reseting the coverage. Also try to fix check-fuzzer on the bot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281814
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Mehdi Amini [Sat, 17 Sep 2016 06:00:02 +0000 (06:00 +0000)]
Don't create a SymbolTable in Function when the LLVMContext discards value names (NFC)
The ValueSymbolTable is used to detect name conflict and rename
instructions automatically. This is not needed when the value
names are automatically discarded by the LLVMContext.
No functional change intended, just saving a little bit of memory.
This is a recommit of r281806 after fixing the accessor to return
a pointer instead of a reference and updating all the call-sites.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281813
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Mehdi Amini [Sat, 17 Sep 2016 05:41:02 +0000 (05:41 +0000)]
[MIR Parser] Fix Build!
Last-second refactoring before push was bad idea...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281812
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Mehdi Amini [Sat, 17 Sep 2016 05:33:58 +0000 (05:33 +0000)]
MIR Parser: issue an error when the Context discard value names.
This is in line with the LLParser behavior
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281811
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Kostya Serebryany [Sat, 17 Sep 2016 05:04:47 +0000 (05:04 +0000)]
[libFuzzer] change trace-pc to use 8-byte guards
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281810
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Kostya Serebryany [Sat, 17 Sep 2016 05:03:05 +0000 (05:03 +0000)]
[sanitizer-coverage] change trace-pc to use 8-byte guards
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281809
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Mehdi Amini [Sat, 17 Sep 2016 04:36:46 +0000 (04:36 +0000)]
Revert "Don't create a SymbolTable in Function when the LLVMContext discards value names (NFC)"
This reverts commit r281806. It introduces undefined behavior as an
API is returning a reference to the Symtab
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281808
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Mehdi Amini [Sat, 17 Sep 2016 03:39:01 +0000 (03:39 +0000)]
Don't create a SymbolTable in Function when the LLVMContext discards value names (NFC)
The ValueSymbolTable is used to detect name conflict and rename
instructions automatically. This is not needed when the value
names are automatically discarded by the LLVMContext.
No functional change intended, just saving a little bit of memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281806
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Matt Arsenault [Sat, 17 Sep 2016 02:02:19 +0000 (02:02 +0000)]
AMDGPU: Use i64 scalar compare instructions
VI added eq/ne for i64, so use them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281800
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Tom Stellard [Fri, 16 Sep 2016 22:20:24 +0000 (22:20 +0000)]
AMDGPU/SI: Fix kernel argument ABI for HSA
Summary: i8, i16, and f16 values are not extended to 32-bit in the HSA kernel ABI.
Reviewers: arsenm
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl
Differential Revision: https://reviews.llvm.org/D24621
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281789
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Chris Bieneman [Fri, 16 Sep 2016 22:19:19 +0000 (22:19 +0000)]
[CMake] Support symlinks with the same name as the binary
This supports creating symlinks to tools in different directories than
the tool is built to. This is useful for the LLDB framework build which
I’m sending patches for shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281788
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Sanjay Patel [Fri, 16 Sep 2016 22:16:18 +0000 (22:16 +0000)]
[InstCombine] canonicalize vector select with constant vector condition to shuffle
As discussed on llvm-dev ( http://lists.llvm.org/pipermail/llvm-dev/2016-August/104210.html ):
turn a vector select with constant condition operand into a shuffle as a canonicalization step.
Shuffles may be easier to reason about in conjunction with other shuffles and insert/extract.
Possible known (minor?) regressions from this change are filed as:
https://llvm.org/bugs/show_bug.cgi?id=28530
https://llvm.org/bugs/show_bug.cgi?id=28531
https://llvm.org/bugs/show_bug.cgi?id=30371
If something terrible happens to perf after this commit, feel free to revert until a backend
fix is in place.
Differential Revision: https://reviews.llvm.org/D24279
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281787
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Matt Arsenault [Fri, 16 Sep 2016 22:11:18 +0000 (22:11 +0000)]
AMDGPU: Allow some control flow intrinsics to be CSEd
These clean up some unnecessary or instructions in
cases with complex loops.
In the original testcase I noticed this, the same
or with exec was repeated 5 or 6 times in a row. With
this only one is emitted or sometimes a copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281786
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Evgeniy Stepanov [Fri, 16 Sep 2016 22:04:10 +0000 (22:04 +0000)]
[safestack] Fix assertion failure in stack coloring.
This is a fix for PR30318.
Clang may generate IR where an alloca is already live when entering a
BB with lifetime.start. In this case, conservatively extend the
alloca lifetime all the way back to the block entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281784
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Quentin Colombet [Fri, 16 Sep 2016 22:00:50 +0000 (22:00 +0000)]
[RegAllocGreedy] Fix the list of NewVRegs for last chance recoloring.
When trying to recolor a register we may split live-ranges in the
process. When we create new live-ranges we will have to process them,
but when we move a register from Assign to Split, the allocation is not
changed until the whole recoloring session is successful.
Therefore, only push the live-ranges that changed from Assign to
Split when the recoloring is successful.
Same as the previous commit, I was not able to produce a test case that
reproduce the problem with in-tree targets.
Note: The bug has been here since the recoloring scheme has been added
back in r200883 (Feb 2014).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281783
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Quentin Colombet [Fri, 16 Sep 2016 22:00:42 +0000 (22:00 +0000)]
[RegAllocGreedy] Fix an assertion and condition when last chance recoloring is used.
When last chance recoloring is used, the list of NewVRegs may not be
empty when calling selectOrSplitImpl. Indeed, another coloring may have
taken place with splitting/spilling in the same recoloring session.
Relax an assertion to take this into account and adapt a condition to
act as if the NewVRegs were local to this selectOrSplitImpl instance.
Unfortunately I am unable to produce a test case for this, I was only
able to reproduce the conditions on an out-of-tree target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281782
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Tom Stellard [Fri, 16 Sep 2016 21:53:00 +0000 (21:53 +0000)]
AMDGPU: Refactor kernel argument lowering
Summary:
The main challenge in lowering kernel arguments for AMDGPU is determing the
memory type of the argument. The generic calling convention code assumes
that only legal register types can be stored in memory, but this is not the
case for AMDGPU.
This consolidates all the logic AMDGPU uses for deducing memory types into a single
function. This will make it much easier to support different ABIs in the future.
Reviewers: arsenm
Subscribers: arsenm, wdng, nhaehnle, llvm-commits, yaxunl
Differential Revision: https://reviews.llvm.org/D24614
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281781
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Matt Arsenault [Fri, 16 Sep 2016 21:41:16 +0000 (21:41 +0000)]
AMDGPU: Use SOPK compare instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281780
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Tom Stellard [Fri, 16 Sep 2016 21:34:26 +0000 (21:34 +0000)]
AMDGPU/SI: Add support for triples with the mesa3d operating system
Summary:
mesa3d will use the same kernel calling convention as amdhsa, but it will
handle everything else like the default 'unknown' OS type.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits, kzhuravl
Differential Revision: https://reviews.llvm.org/D22783
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281779
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