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Marek Olšák [Thu, 5 Oct 2017 23:01:11 +0000 (01:01 +0200)]
radeonsi: disable primitive binning on Vega10 (v2)
Our driver implementation is known to decrease performance for some tests,
but we don't know if any apps and benchmarks (e.g. those tested by Phoronix)
are affected. This disables the feature just to be safe.
Set this to enable partial primitive binning:
R600_DEBUG=dpbb
Set this to enable full primitive binning:
R600_DEBUG=dpbb,dfsm
v2: add new debug options
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 7 Oct 2017 16:10:26 +0000 (18:10 +0200)]
radeonsi: enumerize DBG flags
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Oct 2017 13:42:22 +0000 (15:42 +0200)]
drirc: whitelist glthread for Spec Ops: The Line
On i7 4790k and a 280X, there is a boost of about 10% more FPS.
Nominated by John Ettedgui.
Samuel Pitoiset [Fri, 6 Oct 2017 07:53:21 +0000 (09:53 +0200)]
radv: configure VGT_VERTEX_REUSE at pipeline creation
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 6 Oct 2017 07:53:20 +0000 (09:53 +0200)]
radv: do not need to zero-init ds/raster states
Already done when creating the pipeline.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 6 Oct 2017 07:53:19 +0000 (09:53 +0200)]
radv: remove unused fields in radv_raster_state
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 6 Oct 2017 13:39:01 +0000 (15:39 +0200)]
radv: set ALPHA_TO_MASK_ENABLE at blend state init
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 6 Oct 2017 13:39:00 +0000 (15:39 +0200)]
radv: emit PA_SU_POINT_{SIZE,MINMAX} in si_emit_config()
These registers don't change during the lifetime of the
command buffer, there is no need to re-emit them when
binding a new pipeline.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 6 Oct 2017 14:03:15 +0000 (16:03 +0200)]
radv: allow launching waves out-of-order for compute
Ported from RadeonSI, and -pro seems to enable it as well.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Jason Ekstrand [Sat, 7 Oct 2017 21:37:50 +0000 (14:37 -0700)]
anv/wsi: Allocate enough memory for the entire image
Previously, we allocated memory for image->plane[0].surface.isl.size
which is great if there is no compression. However, on BDW, we can do
CCS_D on X-tiled images so we also have to allocate space for the
auxiliary buffer. This fixes hangs in some of the WSI CTS tests and
should also reduce hangs in real applications. In particular, it fixes
the dEQP-VK.wsi.*.incremental_present.* test group.
When we hand the image off to X11 or Wayland, it will ignore the CCS
entirely which is ok because we do a resolve when it's transitioned to
VK_IMAGE_LAYOUT_PRESENT_SRC_KHR.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Lionel Landwerlin [Sat, 7 Oct 2017 18:29:18 +0000 (19:29 +0100)]
anv: fix nir.h include
All over mesa we include "nir/nir.h", we should probably do the same
here. This fixes the meson build that was broken by the ycbcr series.
Thanks to Dylan for finding the issue.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
f3e91e78a337 ("anv: add nir lowering pass for ycbcr textures")
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Fri, 6 Oct 2017 03:47:29 +0000 (20:47 -0700)]
spirv: Don't warn on the ImageCubeArray capability
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Sat, 7 Oct 2017 18:19:42 +0000 (11:19 -0700)]
mesa: make glFramebuffer* check immutable texture level bounds
When a texture is immutable, we can't tack on extra levels
after-the-fact like we could with glTexImage. So check against that
level limit and return an error if it's surpassed.
This fixes:
KHR-GL45.geometry_shader.layered_fbo.fb_texture_invalid_level_number
(Based on a patch by Ilia Mirkin.)
Reviewed-by: Antia Puentes <apuentes@igalia.com> [imirkin v2]
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 Oct 2017 19:29:35 +0000 (21:29 +0200)]
radeonsi: don't change viewport for blits, use window-space positions
The viewport state was an identity anyway.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 Oct 2017 22:19:22 +0000 (00:19 +0200)]
radeonsi: set correct PA_SC_VPORT_ZMIN/ZMAX when viewport is disabled
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 Oct 2017 22:14:17 +0000 (00:14 +0200)]
radeonsi: minor cleanup of si_update_vs_writes_viewport_index
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 Oct 2017 18:36:34 +0000 (20:36 +0200)]
radeonsi: don't save and restore vertex buffers and elements for u_blitter
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 Oct 2017 18:28:29 +0000 (20:28 +0200)]
radeonsi: use new VS blit shaders (VS inputs in SGPRs)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 Oct 2017 18:05:44 +0000 (20:05 +0200)]
radeonsi: add VS blit shader creation
no users yet
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 Oct 2017 01:12:21 +0000 (03:12 +0200)]
radeonsi: split declare_default_desc_pointers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 Oct 2017 02:02:05 +0000 (04:02 +0200)]
gallium/u_blitter: let drivers decide which VS to use for draw_rectangle
This approach allows drivers to set their own vertex shader and skip
compilation of u_blitter vertex shaders.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 Oct 2017 00:38:35 +0000 (02:38 +0200)]
gallium/u_blitter: let drivers set the vertex elements state
radeonsi won't set it.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 Oct 2017 00:08:05 +0000 (02:08 +0200)]
gallium/u_blitter: remove blitter_context_priv::viewport
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 4 Oct 2017 23:54:30 +0000 (01:54 +0200)]
radeonsi: don't use util_draw_arrays_instanced in si_draw_rectangle
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 4 Oct 2017 23:48:51 +0000 (01:48 +0200)]
radeonsi: move si_draw_rectangle into si_state_draw.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 Oct 2017 00:05:33 +0000 (02:05 +0200)]
radeonsi: remove wrappers si_decompress_xx_textures
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 4 Oct 2017 23:34:36 +0000 (01:34 +0200)]
gallium/radeon: remove r600_atom::num_dw
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 4 Oct 2017 23:24:52 +0000 (01:24 +0200)]
gallium/radeon: remove old r600g code checking chip_class and family
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Mark Thompson [Sun, 1 Oct 2017 17:40:45 +0000 (18:40 +0100)]
st/va: Implement vaExportSurfaceHandle()
This is a new interface in libva2 to support wider use-cases of passing
surfaces to external APIs. In particular, this allows export of NV12 and
P010 surfaces.
v2: Convert surfaces to progressive before exporting them (Christian).
v3: Set destination rectangle to match source when converting (Leo).
Add guards to allow building with libva1.
Signed-off-by: Mark Thompson <sw@jkqxz.net>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-and-Tested-by: Leo Liu <leo.liu@amd.com>
Roland Scheidegger [Fri, 6 Oct 2017 22:52:58 +0000 (00:52 +0200)]
gallivm: don't use pabs intrinsic with llvm version >= 6
The intrinsic is gone, causing shader compilation to crash.
While here, also change the fallback code to match what llvm's auto-updater
of these intrinsics would do (except that there will still be zext/trunc
instructions in there), which should ensure that the sequence gets recognized
and fused back into a pabs in the end (I didn't test this, and it's possible
even the old sequence would get recognized, but I don't see a reason why we
shouldn't use the same sequence in any case).
Tested-by: Vinson Lee <vlee@freedesktop.org>
Tim Rowley [Tue, 3 Oct 2017 20:23:44 +0000 (15:23 -0500)]
swr/rast: use proper alignment for debug transposedPrims
Causing a crash in ParaView waveletcontour.py test when
_DEBUG defined due to vector aligned copy with unaligned
address.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Lionel Landwerlin [Thu, 28 Sep 2017 22:57:45 +0000 (23:57 +0100)]
anv/cmd_buffer: Reset state in cmd_buffer_destroy
This ensures that everything gets cleaned up properly. In particular,
it fixes a memory leak where we were leaking the push constants
structs.
Valgrind stats on
dEQP-VK.pipeline.push_constant.graphics_pipeline.range_size_128 :
Before:
HEAP SUMMARY:
in use at exit: 2,467,513 bytes in 1,305 blocks
total heap usage: 697,853 allocs, 696,530 frees, 138,466,600 bytes allocated
LEAK SUMMARY:
definitely lost: 1,068 bytes in 11 blocks
indirectly lost: 24,669 bytes in 412 blocks
possibly lost: 0 bytes in 0 blocks
still reachable: 2,441,776 bytes in 882 blocks
suppressed: 0 bytes in 0 blocks
After:
HEAP SUMMARY:
in use at exit: 2,467,381 bytes in 1,304 blocks
total heap usage: 697,853 allocs, 696,531 frees, 138,466,600 bytes allocated
LEAK SUMMARY:
definitely lost: 936 bytes in 10 blocks
indirectly lost: 24,669 bytes in 412 blocks
possibly lost: 0 bytes in 0 blocks
still reachable: 2,441,776 bytes in 882 blocks
suppressed: 0 bytes in 0 blocks
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "17.2 17.1" <mesa-stable@lists.freedesktop.org>
Lionel Landwerlin [Wed, 27 Sep 2017 13:16:04 +0000 (14:16 +0100)]
anv/cmd_buffer: fix push descriptors with set > 0
When writing to set > 0, we were just wrongly writing to set 0. This
commit fixes this by lazily allocating each set as we write to them.
We didn't go for having them directly into the command buffer as this
would require an additional ~45Kb per command buffer.
v2: Allocate push descriptors from system memory rather than in BO
streams. (Lionel)
Cc: "17.2 17.1" <mesa-stable@lists.freedesktop.org>
Fixes:
9f60ed98e501 ("anv: add VK_KHR_push_descriptor support")
Reported-by: Daniel Ribeiro Maciel <daniel.maciel@gmail.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Mon, 19 Jun 2017 15:57:00 +0000 (16:57 +0100)]
anv: enable VK_KHR_sampler_ycbcr_conversion
v2: Make GetImageMemoryRequirements2KHR() iterate over all pInfo
structs (Lionel)
Handle VkSamplerYcbcrConversionImageFormatPropertiesKHR (Andrew/Jason)
Iterator over BindImageMemory2KHR's pNext structs correctly (Jason)
v3: Revert GetImageMemoryRequirements2KHR() change from v2 (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Wed, 19 Jul 2017 11:14:19 +0000 (12:14 +0100)]
anv: enable multiple planes per image/imageView
This change introduce the concept of planes for image & views. It
matches the planes available in new formats.
We also refactor depth & stencil support through the usage of planes
for the sake of uniformity. In the backend (genX_cmd_buffer.c) we have
to take some care though with regard to auxilliary surfaces.
Multiplanar color buffers can have multiple auxilliary surfaces but
depth & stencil share the same HiZ one (only store in the depth
plane).
v2: by Jason
Remove unused aspect parameters from anv_blorp.c
Assert when attempting to resolve YUV images
Drop redundant logic for plane offset in make_surface()
Rework anv_foreach_plane_aspect_bit()
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Thu, 5 Oct 2017 19:36:16 +0000 (12:36 -0700)]
anv: Take an image in can_sample_with_hiz
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 5 Oct 2017 19:20:40 +0000 (12:20 -0700)]
anv: Take a single aspect in anv_layout_to_aux_usage
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 5 Oct 2017 18:42:33 +0000 (11:42 -0700)]
anv/cmd_buffer: Make get_fast_clear_state return an address
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 5 Oct 2017 18:22:47 +0000 (11:22 -0700)]
anv/blorp: Add a concept of default aux usage
A good chunk of anv_blorp just wants the aux usage from the image. This
magic aux_usage value means just that.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Lionel Landwerlin [Mon, 19 Jun 2017 15:56:47 +0000 (16:56 +0100)]
anv: add nir lowering pass for ycbcr textures
This pass implements all the implicit conversions required by the
VK_KHR_sampler_ycbcr_conversion specification.
It also inserts plane sources onto sampling instructions that we then
let the pipeline layout pass deal with, when mapping things correctly
to descriptors.
v2: Add new file to meson build (Lionel)
Use nir_frcp() rather than (1.0f / x) (Jason)
Reuse nir_tex_instr_dest_size() rather than handwritten one (Jason)
Return progress (Jason)
Account for array of samplers (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Mon, 25 Sep 2017 17:47:33 +0000 (18:47 +0100)]
anv: prepare sampler emission code for multiplanar images
New settings from the KHR_sampler_ycbcr_conversion specifications
might require different sampler settings for luma and chroma planes.
This change makes the sampler table emission ready to handle multiple
planes.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Mon, 25 Sep 2017 17:46:16 +0000 (18:46 +0100)]
anv/apply_pipeline_layout: Prepare for multi-planar images
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Tue, 14 Mar 2017 17:22:36 +0000 (17:22 +0000)]
anv: add new formats KHR_sampler_ycbcr_conversion
Adding new downsampling factors for each planes.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Tue, 14 Mar 2017 17:20:07 +0000 (17:20 +0000)]
anv: modify the internal concept of format to express multiple planes
A given Vulkan format can now be decomposed into a set of planes. We
now use 'struct anv_format_plane' to represent the format of those
planes.
v2: by Jason
Rename anv_get_plane_format() to anv_get_format_plane()
Don't rename anv_get_isl_format()
Replace ds_fmt() by fmt2()
Introduce fmt_unsupported()
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Mon, 25 Sep 2017 17:10:20 +0000 (18:10 +0100)]
anv: prepare formats to handle disjoints sets
Newer format enums start at offset
1000000000, making it impossible to
have them all in one table. This change splits the formats into sets
that we then access through indirection.
v2: rename format_extract to vk_to_anv_format (Chad/Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Thu, 20 Jul 2017 19:40:41 +0000 (20:40 +0100)]
isl: fill out layout descriptions for yuv formats
Some description was missing.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Tue, 3 Oct 2017 18:10:41 +0000 (19:10 +0100)]
isl: check whether a format is rgb if colorspace is yuv
Suggested by Chad.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Tue, 6 Jun 2017 19:00:46 +0000 (20:00 +0100)]
isl: make format layout channels accessible by index
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Tue, 14 Mar 2017 17:17:12 +0000 (17:17 +0000)]
vulkan: util: add macros to extract extension/offset number from enums
v2: Simplify offset enum computation (Jason)
v3: capitalize macros (Chad)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Samuel Pitoiset [Tue, 3 Oct 2017 13:11:21 +0000 (15:11 +0200)]
radv: convert all COMPUTE operations to the RADV_META_SAVE_XXX flags
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 3 Oct 2017 12:47:32 +0000 (14:47 +0200)]
radv: add RADV_META_SAVE_COMPUTE_PIPELINE flag
This will allow use to merge the compute save/restore helpers.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 3 Oct 2017 12:37:56 +0000 (14:37 +0200)]
radv: add radv_meta_save() helper
And merge radv_meta_save_novertex() with
radv_meta_save_graphics_reset_vport_scissor_novertex().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 3 Oct 2017 12:26:38 +0000 (14:26 +0200)]
radv: merge radv_meta_{save,restore}_pass() with RADV_META_SAVE_PASS
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 3 Oct 2017 12:23:48 +0000 (14:23 +0200)]
radv: convert all GFX operations to the RADV_META_SAVE_XXX flags
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 3 Oct 2017 12:12:05 +0000 (14:12 +0200)]
radv: introduce the concept of meta save flags
This will allow us to save/restore the different states on-demand
based on the meta operation. For now, this saves/restores all
states. Compute will follow once the graphics part is done.
The main idea is to merge all save/restore helpers.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 3 Oct 2017 09:31:57 +0000 (11:31 +0200)]
radv: remove unused RADV_META_VERTEX_BINDING_COUNT
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 3 Oct 2017 09:08:03 +0000 (11:08 +0200)]
radv: select the pipeline outside of the loop when decompressing htile
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 3 Oct 2017 08:48:42 +0000 (10:48 +0200)]
radv: add radv_htile_enabled() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tapani Pälli [Wed, 4 Oct 2017 13:32:05 +0000 (16:32 +0300)]
i965: pass wanted format to intel_miptree_create_for_dri_image
Change
b3a44ae7a4 caused regressions on Android where DRI and renderbuffer
can disagree on the format being used. This patch removes the colorspace
parameter and instead we pass renderbuffer format. For non-winsys images we
still do srgb/linear modification in same manner as change
b3a44ae7a4 wanted
but take format from renderbuffer instead of DRI image.
This patch fixes regressions seen with following test sets:
dEQP-EGL.functional.color_clears*
dEQP-EGL.functional.render*
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102999
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Marek Olšák [Tue, 3 Oct 2017 17:28:48 +0000 (19:28 +0200)]
radeonsi: add a drirc workaround for HTILE corruption in ARK: Survival Evolved
v2: use DB_META | PS_PARTIAL_FLUSH
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102955
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v1)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Marek Olšák [Mon, 2 Oct 2017 15:07:52 +0000 (17:07 +0200)]
radeonsi: inline struct si_sampler_views
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 2 Oct 2017 15:03:01 +0000 (17:03 +0200)]
radeonsi: rename si_textures_info -> si_samplers, si_images_info -> si_images
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 2 Oct 2017 14:58:10 +0000 (16:58 +0200)]
radeonsi: fold needs_*_decompress_mask update into si_set_sampler_view
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 2 Oct 2017 14:49:37 +0000 (16:49 +0200)]
radeonsi: simplify a loop in si_update_fb_dirtiness_after_rendering
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 30 Sep 2017 13:36:18 +0000 (15:36 +0200)]
ac: properly document a buffer.store LLVM workaround
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 29 Sep 2017 14:49:14 +0000 (16:49 +0200)]
radeonsi: use f32_0 and f32_1
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 29 Sep 2017 14:35:26 +0000 (16:35 +0200)]
radeonsi: fold *gallivm
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 29 Sep 2017 14:28:23 +0000 (16:28 +0200)]
radeonsi: lp_type::length is always 1
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 29 Sep 2017 14:27:26 +0000 (16:27 +0200)]
radeonsi: don't use bld.elem_type
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 29 Sep 2017 14:23:45 +0000 (16:23 +0200)]
radeonsi: don't use lp_build_const_*
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 29 Sep 2017 13:11:14 +0000 (15:11 +0200)]
radeonsi: use ctx->ac.context and ctx->types
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 29 Sep 2017 13:02:06 +0000 (15:02 +0200)]
radeonsi: use ctx->ac.builder
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 27 Sep 2017 10:58:43 +0000 (12:58 +0200)]
radeonsi: use ctx->i/f32 types more
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 27 Sep 2017 10:53:41 +0000 (12:53 +0200)]
radeonsi: use i32_0 and i32_1 more
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 27 Sep 2017 10:48:31 +0000 (12:48 +0200)]
radeonsi: use bitcast in a few places
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 27 Sep 2017 10:46:17 +0000 (12:46 +0200)]
radeonsi: use ac helpers for bitcasts
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
Marek Olšák [Tue, 26 Sep 2017 13:32:49 +0000 (15:32 +0200)]
glsl_to_tgsi: skip UARL for 1D registers if the driver doesn't need it
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Sep 2017 13:34:34 +0000 (15:34 +0200)]
glsl_to_tgsi: handle reladdr as TEMP in rename_temp_registers and dead_code
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 29 Sep 2017 00:38:53 +0000 (02:38 +0200)]
glsl_to_tgsi: each reladdr object should have only one parent
required by rename_temp_registers.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 29 Sep 2017 02:52:10 +0000 (04:52 +0200)]
glsl_to_tgsi: fix instruction order for bindless textures
We emitted instructions loading the bindless handle after the memory
instruction.
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Sep 2017 01:32:15 +0000 (03:32 +0200)]
glsl_to_tgsi: enable copy propagation for tessellation shaders
just don't propagate output reads
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Sep 2017 13:58:13 +0000 (15:58 +0200)]
radeonsi: implement PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 28 Sep 2017 20:21:03 +0000 (22:21 +0200)]
radeonsi: use si_get_indirect_index for TEMP indexing
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Sep 2017 13:30:34 +0000 (15:30 +0200)]
radeonsi: use si_get_indirect_index for CONST indexing
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 28 Sep 2017 19:45:51 +0000 (21:45 +0200)]
tgsi/ureg: allow any register file in address operands
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Sep 2017 13:56:15 +0000 (15:56 +0200)]
gallium: add PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Sep 2017 14:17:47 +0000 (16:17 +0200)]
tgsi/scan: scan address operands (v2)
v2: set swizzled usage mask
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 2 Oct 2017 18:35:15 +0000 (20:35 +0200)]
tgsi/scan: set correct usage mask for tex offsets in scan_src_operand
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 2 Oct 2017 17:59:22 +0000 (19:59 +0200)]
tgsi/scan: take advantage of already swizzled usage mask in scan_src_operand
It has always been a usage mask *after* swizzling.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 2 Oct 2017 17:51:16 +0000 (19:51 +0200)]
tgsi/scan: set non-valid src_index for tex offsets in scan_src_operand
tex offsets are not "Src" operands.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 2 Oct 2017 20:30:55 +0000 (22:30 +0200)]
tgsi: implement tgsi_util_get_inst_usage_mask properly
All opcodes are handled.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 2 Oct 2017 20:28:46 +0000 (22:28 +0200)]
tgsi: add docs for some existing pack opcodes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Bas Nieuwenhuizen [Thu, 5 Oct 2017 23:12:48 +0000 (01:12 +0200)]
radv: Enable VK_KHR_maintenance2 extension.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Thu, 5 Oct 2017 23:10:44 +0000 (01:10 +0200)]
radv: Make tess winding order a bit more intuitive.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Thu, 5 Oct 2017 23:10:11 +0000 (01:10 +0200)]
radv: Allow setting the domain origin in tess.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Thu, 5 Oct 2017 22:55:57 +0000 (00:55 +0200)]
radv: Disable usage checks in metadata for images with extended usage data.
The app can extend the usage, so knowing that the usage is limitied
does not help us here.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Thu, 5 Oct 2017 22:50:15 +0000 (00:50 +0200)]
radv: Implement querying the point clipping behavior.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Daniel Stone [Wed, 27 Sep 2017 17:42:22 +0000 (18:42 +0100)]
broadcom: Fix out-of-tree build include path
Reviewed-by: Eric Anholt <eric@anholt.net>
Fixes:
5b102160ae ("broadcom/genxml: Introduce a V3D packet/struct decoder.")
Bas Nieuwenhuizen [Thu, 5 Oct 2017 19:31:29 +0000 (21:31 +0200)]
meson: generate builddir/src/amd/vulkan/dev_icd.json
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Kenneth Graunke [Wed, 4 Oct 2017 08:08:37 +0000 (01:08 -0700)]
mesa: Use a 565 format for GL_RGB and GL_UNSIGNED_SHORT_5_6_5 textures.
Found while trying to optimize an application.
Not observed to help performance on i965, but should at least reduce
the memory usage of such textures a bit.
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>