OSDN Git Service
Dylan Baker [Tue, 15 Jan 2019 19:55:36 +0000 (11:55 -0800)]
meson: allow building dri driver without window system if osmesa is classic
This was already enabled for gallium based osmesa with gallium drivers
in
9d10581897ef7cfa0f6c392e2048cc04357281b9, so do the same for classic
driver with classic osmesa.
Fixes:
cbbd5bb889a2c271a504c379f36a7cb717a85af4
("meson: build classic osmesa")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit
431e9abaaba6386aa7fbc1ec0e2566a3f8999f5d)
Bruce Cherniak [Fri, 4 Jan 2019 20:53:59 +0000 (14:53 -0600)]
gallium/swr: Fix multi-context sync fence deadlock.
Various recreation scenarios lead to API thread getting stuck in
swr_fence_finish(). This is a multi-context issue, whereby one context
overwrites the fence read-value with a previous sync's lesser value.
The fence sync value is supposed to be always increasing.
In swr_fence_cb(), only update the "read" value if the new value is
greater.
(This may seem like we're not waiting on the other context to finish, but
had we needed for it to finish there would have been a wait prior to
submitting a new sync.)
cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
ed7673afd2d1a31bfcec0520743acd2681b462e6)
Pierre Moreau [Wed, 9 Jan 2019 22:03:45 +0000 (23:03 +0100)]
meson: Fix with_gallium_icd to with_opencl_icd
`with_gallium_icd` is never used throughout the different Meson build
files, whereas `with_opencl_icd` tracks whether or not `gallium-opencl`
was set to "icd".
Fixes:
42ea0631f108d82554339530d6c88aa1b448af1e
("meson: build clover")
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
0b736f7fd4852bdea2ac6be9a018a41065252233)
Bas Nieuwenhuizen [Sat, 12 Jan 2019 19:09:23 +0000 (20:09 +0100)]
radv: Set partial_vs_wave for pipelines with just GS, not tess.
Looking at -pro we need to enable it for pipelines with just a
GS too.
This seems to reduce the hangs from
https://bugs.freedesktop.org/show_bug.cgi?id=109242 on a RX 550 to
the point where I can't reproduce, after the false start with the
wd_switch_on_eop patch due to flakiness.
(but people are reporting it does not fix the issue completely for
them on polaris 11)
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
568e7a2998e39263c41ec70ec67bcc5601477781)
Samuel Pitoiset [Thu, 8 Nov 2018 13:00:36 +0000 (14:00 +0100)]
radv: clean up setting partial_es_wave for distributed tess on VI
Only needed when the pipeline actually uses tessellation. I don't
think that changes anything, except improving readability.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
d9d14346c2ba66bfef7ca120ccbcd3201ca32359)
Marek Olšák [Mon, 14 Jan 2019 23:24:08 +0000 (18:24 -0500)]
radeonsi: also apply the GS hang workaround to draws without tessellation
ported from AMDVLK.
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
5183e794affbbbf7dc959332619b0852c21536d6)
Bas Nieuwenhuizen [Mon, 14 Jan 2019 13:44:15 +0000 (14:44 +0100)]
radv: Only use 32 KiB per threadgroup on Stoney.
Causes hangs on some machines.
What works for dEQP-VK.tessellation.shader_input_output.barrier:
- running num_patches = 6 (which limits LDS to 32 KiB)
- running num_patches = 8, and artificially cutting LDS size at 32 KiB.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
76b12fa564a5f48e3f2264718dea0158d0c05b4c)
Andres Gomez [Fri, 11 Jan 2019 14:43:27 +0000 (16:43 +0200)]
bin/get-pick-list.sh: fix redirection in sh
"&>" is bash specific.
Fixes:
e0dbfc99537 ("bin/get-pick-list.sh: warn when commit lists invalid sha")
Cc: Juan A. Suarez <jasuarez@igalia.com>
Cc: Eric Engestrom <eric.engestrom@intel.com>
Cc: Dylan Baker <dylan@pnwbakers.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
(cherry picked from commit
3ec9ab80b870efffb5ba7c7a00b86b2df729ec6d)
Andres Gomez [Fri, 11 Jan 2019 14:42:25 +0000 (16:42 +0200)]
bin/get-pick-list.sh: fix the oneline printing
"--summary" will also print extended header information such as
creations, renames and mode changes.
Let's just use "--no-patch", which suppresses the diff output.
v2: Use "--no-patch" instead of the "-s" abbreviation (Eric).
Fixes:
559c32d2412 ("bin/get-pick-list.sh: simplify git oneline printing")
Cc: Juan A. Suarez <jasuarez@igalia.com>
Cc: Eric Engestrom <eric.engestrom@intel.com>
Cc: Dylan Baker <dylan@pnwbakers.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
(cherry picked from commit
716ed41a36037459ed5bfe0775484ac2cbd90707)
Emil Velikov [Tue, 29 Jan 2019 15:10:34 +0000 (15:10 +0000)]
cherry-ignore: spirv: Handle arbitrary bit sizes for deref array indices
stable The commits aren't suitable in their present form.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Tue, 29 Jan 2019 14:58:15 +0000 (14:58 +0000)]
cherry-ignore: radv: Fix multiview depth clears
fixes: This commit requires commits
aeaf8dbd097 and
7484bc894b9 which
did not land in branch.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 17 Jan 2019 11:30:49 +0000 (11:30 +0000)]
docs: add sha256 checksums for 18.3.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 17 Jan 2019 11:24:36 +0000 (11:24 +0000)]
docs: add release notes for 18.3.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 17 Jan 2019 11:15:36 +0000 (11:15 +0000)]
Update version to 18.3.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Rhys Perry [Mon, 17 Dec 2018 15:37:05 +0000 (15:37 +0000)]
ac: split 16-bit ssbo loads that may not be dword aligned
This ends up refactoring visit_load_buffer() a little.
Fixes:
7e7ee826982 ('ac: add support for 16bit buffer loads')
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108114
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
bde9f482de69528db5ccf5dd6bbfd8359adfbb19)
Note: this is a backport of the above commit provided by Rhys.
Nicolai Hähnle [Wed, 5 Dec 2018 12:28:03 +0000 (13:28 +0100)]
meson: link LLVM 'native' component when LLVM is available
Linking against LLVM built with BUILD_SHARED_LIBS fails otherwise,
as the component is required for the draw module.
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
4275cae95c8cb217d6164dfeeafae7b56484b13d)
Karol Herbst [Fri, 7 Dec 2018 08:44:55 +0000 (09:44 +0100)]
nv50/ir: fix use-after-free in ConstantFolding::visit
opnd() might delete the passed in instruction, but it's used through
i->srcExists() later in visit
v2: use continue instead return
v3: use brackets for the outer if/else chain
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit
77944fb2b7c9b40539084f600b5df4fff18e9640)
Jason Ekstrand [Wed, 17 Oct 2018 16:34:32 +0000 (11:34 -0500)]
intel/peephole_ffma: Fix swizzle propagation
The num_components value passed into get_mul_for_src is used to only
compose the parts of the swizzle that we know will be used so we don't
compose invalid swizzle components. However, we had a bug where we
passed the number of components of the add all the way through. For the
given source, we need the number of components read from that source.
In the case where we have a narrow add, say 2 components, that is
sourced from a chain of wider instructions, we may not compose all the
swizzles. All we really need to do is pass through the right number of
components at each level.
Fixes:
2231cf0ba3a "nir: Fix output swizzle in get_mul_for_src"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit
1ede463b6e66eb0a6df5250261810b6985c35eb9)
Andres Gomez [Mon, 7 Jan 2019 14:11:44 +0000 (16:11 +0200)]
glsl/linker: specify proper direction in location aliasing error
The check for location aliasing was always asuming output variables
but this validation is also called for input variables.
Fixes:
e2abb75b0e4 ("glsl/linker: validate explicit locations for SSO programs")
Cc: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
428164d87f8dc1d378236b4913538803653770c6)
Francisco Jerez [Fri, 7 Dec 2018 22:26:23 +0000 (14:26 -0800)]
intel/fs: Respect CHV/BXT regioning restrictions in copy propagation pass.
Currently the visitor attempts to enforce the regioning restrictions
that apply to double-precision instructions on CHV/BXT at NIR-to-i965
translation time. It is possible though for the copy propagation pass
to violate this restriction if a strided move is propagated into one
of the affected instructions. I've only reproduced this issue on a
future platform but it could affect CHV/BXT too under the right
conditions.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
c301f447ea8449804208e414f189c0571e4339a8)
Francisco Jerez [Fri, 7 Dec 2018 22:05:52 +0000 (14:05 -0800)]
intel/eu/gen7: Fix brw_MOV() with DF destination and strided source.
I triggered this bug while prototyping code for a future platform on
IVB. Could be a problem today though if a strided move is
copy-propagated into a type-converting move with DF destination.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
464e79144f8090eb42b8994a983470628c248be0)
Francisco Jerez [Fri, 7 Dec 2018 22:15:50 +0000 (14:15 -0800)]
intel/fs: Fix bug in lower_simd_width while splitting an instruction which was already split.
This seems to be a problem in combination with the lower_regioning
pass introduced by a future commit, which can modify a SIMD-split
instruction causing its execution size to become illegal again. A
subsequent call to lower_simd_width() would hit this bug on a future
platform.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
bc781a0323d719634e29d82b5f14e22db943536e)
Francisco Jerez [Thu, 6 Dec 2018 22:11:34 +0000 (14:11 -0800)]
intel/fs: Implement quad swizzles on ICL+.
Align16 is no longer a thing, so a new implementation is provided
using Align1 instead. Not all possible swizzles can be represented as
a single Align1 region, but some fast paths are provided for
frequently used swizzles that can be represented efficiently in Align1
mode.
Fixes ~90 subgroup quad swap Vulkan CTS tests.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
812ede088f5f6bea4e6fba991bd59d5cce264212)
Francisco Jerez [Sat, 29 Dec 2018 09:44:00 +0000 (01:44 -0800)]
intel/fs: Handle source modifiers in lower_integer_multiplication().
lower_integer_multiplication() implements 32x32-bit multiplication on
some platforms by bit-casting one of the 32-bit sources into two
16-bit unsigned integer portions. This can give incorrect results if
the original instruction specified a source modifier. Fix it by
emitting an additional MOV instruction implementing the source
modifiers where necessary.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
c5f9c0009d5161e059e54a76fbdb910a6c151f9f)
Marek Olšák [Tue, 8 Jan 2019 16:12:05 +0000 (11:12 -0500)]
st/mesa: don't leak pipe_surface if pipe_context is not current
We have found some pipe_surface leaks internally.
This is the same code as surface_destroy in radeonsi.
Ideally, surface_destroy would be in pipe_screen.
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit
e986c1ca1d61bd7492936f43e45996cd4f8bdb61)
Mario Kleiner [Mon, 7 Jan 2019 18:42:29 +0000 (19:42 +0100)]
radeonsi: Fix use of 1- or 2- component GL_DOUBLE vbo's.
With Mesa 18.1, commit
be973ed21f6e, si_llvm_load_input_vs()
changed the number of source 32-bit wide dword components
used for fetching vertex attributes into the vertex shader
from a constant 4 to a variable num_channels number, depending
on input data format, with some special case handling for
input data formats like 64-Bit doubles.
In the case of a GL_DOUBLE input data format with one
or two components though, e.g, submitted via ...
a) glTexCoordPointer(1, GL_DOUBLE, 0, buffer);
b) glTexCoordPointer(2, GL_DOUBLE, 0, buffer);
... the input format would be SI_FIX_FETCH_RG_64_FLOAT,
but no special case handling was implemented for that
case, so in the default path the number of 32-bit
dwords would be set to the number of float input components
derived from info->input_usage_mask. This ends with corrupted
input to the vertex shader, because fetching a 64-bit double
from the vbo requires fetching two 32-bit dwords instead of 1,
and fetching a two double input requires 4 dword fetches
instead of 2, so in these cases the vertex shader receives
incomplete/truncated input data:
a) float v = gl_MultiTexCoord0.x; -> v.x is corrupted.
b) vec2 v = gl_MultiTexCoord0.xy; -> v.x is assigned
correctly, but v.y is corrupted.
This happens with the standard TGSI IR compiled shaders.
Under NIR with R600_DEBUG=nir, we got correct behavior
because the current radeonsi nir code always assigns
info->input_usage_mask = TGSI_WRITEMASK_XYZW, thereby
always fetches 4 dwords regardless of what the shader
actually needs.
Fix this by properly assigning 2 or 4 dword fetches for
one or two component GL_DOUBLE input.
Fixes:
be973ed21f6e ("radeonsi: load the right number of
components for VS inputs and TBOs")
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Cc: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
5e30e54e057300f65019c927482e633c367963fc)
Rhys Perry [Wed, 9 Jan 2019 11:09:33 +0000 (11:09 +0000)]
ac/nir,radv,radeonsi/nir: use correct indices for interpolation intrinsics
Fixes artifacts in World of Warcraft when Multi-sample Alpha-Test is
enabled with DXVK.
It also fixes artifacts with Fallout 4's god rays with DXVK.
Various piglit interpolateAt*() tests under NIR are also fixed.
v2: formatting fix
update commit message to include Fallout 4 and the Fixes tag
Fixes:
f4e499ec791 ('radv: add initial non-conformant radv vulkan driver')
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106595
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
(cherry picked from commit
ee8488ea3b99ad0632e5eac6defcef0264d8782c)
Dylan Baker [Tue, 18 Dec 2018 22:37:52 +0000 (14:37 -0800)]
autotools: Remove tegra vdpau driver
This has never functioned and probably wont ever function, due to the
way gallium media state trackers are architected and the tegra video
decoder is architected.
Cc: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Fixes:
1755f608f5201e0a23f00cc3ea1b01edd07eb6ef
("tegra: Initial support")
(cherry picked from commit
401dca1c73cad4e6ac3137fdd5513e350d060f25)
Lionel Landwerlin [Sun, 23 Dec 2018 17:49:23 +0000 (17:49 +0000)]
anv: flush fast clear colors into compressed surfaces
In the following scenario :
1. Create image format R8G8B8A8_UNORM
2. Create image view format R8G8B8A8_SRGB
3. Clear the view through a sub pass to a particular color
4. Barrier on the image to from color attachment to source transfer
5. Copy the image into a linear buffer to check the content
The step 4 resolving the clear color is unaware of the SRGB format of
the view, because the blorp resolve operations operate on images the
color associated with the resolve will not operate on SRGB format but
UNORM. Leading to the wrong color being written into surfaces.
This change forces a clear color resolve at the end of the render pass
so following resolves won't have to deal with the clear color with a
format that doesn't match the image's format.
On gfxbench vulkan_5_normal 1280x720, this appear to cost us ~0.5fps,
from 49.316 down to 48.949.
v2: Only fast clear resolve when image & view have different formats
(Lionel)
v3: Update warning (Jason)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108911
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
add5a2ec92f4b3f7ac8353e5986dc04186a7b6da)
Lionel Landwerlin [Mon, 24 Dec 2018 10:11:59 +0000 (10:11 +0000)]
anv: explictly specify format for blorp ccs/mcs op
Resolve operations can happen when dealing with view (begin/end
subpasses) in which case the view's format needs to apply, not the
image's format.
v2: Relayout arguments of a ccs_op() call (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108911
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
366eb656ac6fe677828f20295d8916506552a0e8)
Jason Ekstrand [Sat, 15 Dec 2018 15:57:26 +0000 (09:57 -0600)]
spirv: Sign-extend array indices
The SPIR-V spec was recently updated to clarify that array indices are
treated as signed integers.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
(cherry picked from commit
c59f07684c0c99fad0c246dd4a475f6bef5d3cbc)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/compiler/spirv/vtn_variables.c
Jason Ekstrand [Fri, 14 Dec 2018 00:33:46 +0000 (18:33 -0600)]
anv/apply_pipeline_layout: Set the cursor in lower_res_reindex_intrinsic
The loop through instructions doesn't set the cursor for us so unless we
set it somewhere, we may end up emitting instructions in the wrong
place. The only reason why we haven't been bitten by this in the past
is that it only happens in a few variable pointers cases and the CTS
tests for those don't use much control flow so things were getting
emitted in the correct order by accident.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
(cherry picked from commit
f8992eb5badf91e0d9ad3732d56a4e3d78fd1abf)
Jason Ekstrand [Fri, 14 Dec 2018 16:54:08 +0000 (10:54 -0600)]
spirv: Handle any bit size in vector_insert/extract
This crops up both in the actual SPIR-V VectorInsert/Extract opcodes as
well as various places where we deal with vector derefs.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
(cherry picked from commit
42b2f3e91f6d6c4eead40ef91e5edde68019f23c)
Bas Nieuwenhuizen [Sun, 6 Jan 2019 11:34:24 +0000 (12:34 +0100)]
spirv: Fix matrix parameters in function calls.
They can be handled exactly the same as arrays, we just need to handle
the base type correctly in the switches.
Fixes:
a45b6fb4524 "spirv: Pass SSA values through functions"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109204
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
70ed049cc6a682fba084cf57e06728fa5934881b)
Bas Nieuwenhuizen [Wed, 2 Jan 2019 16:53:41 +0000 (17:53 +0100)]
radv: Fix rasterization precision bits.
Note that these limits are exact, not a "precision is at least x",
as texel coords also get snapped to a multiple of this step size
before filtering.
This fixes CTS tests
dEQP-VK.texture.explicit_lod.2d.sizes.31x55_nearest_linear_mipmap_nearest_repeat
dEQP-VK.texture.explicit_lod.2d.sizes.57x35_nearest_linear_mipmap_nearest_repeat
Fixes:
f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109151
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
3cc940277a45285d9932ed62398d7a54d2afffb8)
Andres Gomez [Mon, 7 Jan 2019 13:50:35 +0000 (15:50 +0200)]
glsl: correct typo in GLSL compilation error message
v2: Add the "fix" tag (Erik).
Fixes:
037f68d81e1 ("glsl: apply align layout qualifier rules to block offsets")
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit
0cc01f45e7294122a2ae171b09ac3375b2a75d83)
Bas Nieuwenhuizen [Wed, 5 Dec 2018 10:28:12 +0000 (11:28 +0100)]
anv/android: Do not reject storage images.
We do the ImageFormatProperties check already, and rejecting an usage
flag when both ImageFormatProperties and the WSI (which is Android)
support it is not allowed.
Intel does support storage for some of the support WSI formats, such
as R8G8B8A8_UNORM, and looking at the ISL_SURF_USAGE_DISABLE_AUX_BIT,
the imported images do not have any form of compression that would
prevent this fix.
v2: Also consider STORAGE bit for Gralloc usage bits.
(From Kevin Strasser <kevin.strasser@intel.com>)
Fixes:
053d4c328fa "anv: Implement VK_ANDROID_native_buffer (v9)"
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit
110564fdecd0948e7aa9b1a607af7631430092ff)
Bas Nieuwenhuizen [Mon, 24 Dec 2018 14:41:56 +0000 (15:41 +0100)]
radv: Implement buffer stores with less than 4 components.
We started using it in the btoi paths for r32g32b32, and the LLVM IR
checker will complain about it because we end up with intrinsics with
the wrong type extension in the name.
Fixes:
593996bc02 ("radv: implement buffer to image operations for R32G32B32")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
9a45a190ad22849a492506389413046948e0b093)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/amd/common/ac_nir_to_llvm.c
Jason Ekstrand [Fri, 4 Jan 2019 17:32:40 +0000 (11:32 -0600)]
intel/blorp: Be more conservative about copying clear colors
In
92eb5bbc68d7324 we attempted to avoid copying clear colors whenever
we weren't doing a resolve. However, this broke MSAA resolves because
we need the clear color in the source. This patch makes blorp much more
conservative such that it only avoids the clear color copy if either
aux_usage == NONE or it's explicitly doing a fast-clear.
Fixes:
92eb5bbc68d7 "intel/blorp: Only copy clear color when doing..."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107728
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
(cherry picked from commit
19c608fe43ae7e1578920326690a361ff1be9d88)
Caio Marcelo de Oliveira Filho [Wed, 19 Dec 2018 23:23:28 +0000 (15:23 -0800)]
nir: remove dead code from copy_prop_vars
When copy_prop_vars also took care of dead write handling, intrin was
used as part of store_to_entry. Now it isn't, so this assignment
isn't used really used. Add a comment clarifying what happens to
intrin.
Fixes:
4dfa7adc100 "nir: Remove handling of dead writes from copy_prop_vars"
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
bbf9ee9b18b5917632e6bb74e5859398e6cea224)
Lionel Landwerlin [Thu, 3 Jan 2019 16:18:48 +0000 (16:18 +0000)]
i965: add CS stall on VF invalidation workaround
Even with the previous commit, hangs are still happening. The problem
there is that the VF cache invalidate do happen immediately without
waiting for previous rendering to complete. What happens is that we
invalidate the cache the moment the PIPE_CONTROL is parsed but we
still have old rendering in the pipe which continues to pull data into
the cache with the old high address bits. The later rendering with the
new high address bits then doesn't have the clean cache that it
expects/needs.
v2: Update commit message/explanation with Jason's
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes:
a363bb2cd0e2a1 ("i965: Allocate VMA in userspace for full-PPGTT systems.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109072
(cherry picked from commit
31e4c9ce400341df9b0136419b3b3c73b8c9eb7e)
Lionel Landwerlin [Thu, 3 Jan 2019 16:17:04 +0000 (16:17 +0000)]
i965: include draw_params/derived_draw_params for VF cache workaround
These buffers are using VB slots and should be included in the
workaround decision.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes:
a363bb2cd0e2a1 ("i965: Allocate VMA in userspace for full-PPGTT systems.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109072
(cherry picked from commit
92b7407090b1f11af49133968b63d583eba9b803)
Dylan Baker [Tue, 1 Jan 2019 03:23:52 +0000 (19:23 -0800)]
meson: Error out if building nouveau and using LLVM without rtti
Nouveau requires rtti. Often LLVM is configured without rtti, and code
with and without cannot be linked safely. Lets just error out if nouveau
is requested and llvm is built without rtti.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109202
Fixes:
c5a97d658ec19cc02719d7f86c1b0715e3d9ffc4
("meson: fix builds against LLVM built without rtti")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
a2596450ac7330c8965c819491038fb1ad454333)
Alexander von Gluck IV [Thu, 27 Dec 2018 20:41:47 +0000 (20:41 +0000)]
egl/haiku: Fix reference to disp vs dpy
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes:
00992700c9a812a54563 "egl: set the EGLDevice when creating a display"
(cherry picked from commit
1b97a72328b7b549aa8d050495f504815444c0dd)
Timothy Arceri [Fri, 14 Dec 2018 04:36:02 +0000 (15:36 +1100)]
tgsi/scan: correctly walk instructions in tgsi_scan_tess_ctrl()
The previous code used a do while loop and continues after walking
a nested loop/if-statement. This means we end up evaluating the
last instruction from the nested block against the while condition
and potentially exit early if it matches the exit condition of the
outer block.
Fixes:
386d165d8d09 ("tgsi/scan: add a new pass that analyzes tess factor writes")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
4dda4457504ee5cafa0388543620d4598b8561cf)
Timothy Arceri [Fri, 14 Dec 2018 04:09:38 +0000 (15:09 +1100)]
tgsi/scan: fix loop exit point in tgsi_scan_tess_ctrl()
This just happened not to crash/assert because all loops have at
least 1 if-statement and due to a second bug we end up matching
the same ENDIF to exit both the iteration over the if-statment
and the loop.
The second bug is fixed in the following patch.
Fixes:
386d165d8d09 ("tgsi/scan: add a new pass that analyzes tess factor writes")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
dd061eb0442a25cad0cc775103ae31d62280fa44)
Bas Nieuwenhuizen [Sun, 30 Dec 2018 22:37:11 +0000 (23:37 +0100)]
radv: Do a cache flush if needed before reading predicates.
This caused random failures for two conditional rendering tests:
dEQP-VK.conditional_rendering.draw_clear.draw.update_with_rendering_discard
dEQP-VK.conditional_rendering.draw_clear.draw.update_with_rendering_no_discard
These wrote the predicate with the vertex shader, did a barrier and then
started the conditional rendering. However the cache flushes for the barrier
only happen on first draw, so after the predicate has been read.
Fixes:
e45ba51ea45 "radv: add support for VK_EXT_conditional_rendering"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit
8c93ef5de98a90a93434d351c769f3c06f206397)
Dylan Baker [Tue, 4 Dec 2018 21:52:19 +0000 (13:52 -0800)]
meson: Override C++ standard to gnu++11 when building with altivec on ppc64
Otherwise there will be symbol collisions for the vector name.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108943
Distro Bug: https://bugs.gentoo.org/673622
Fixes:
42ea0631f108d82554339530d6c88aa1b448af1e
("meson: build clover")
Acked-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit
133a5b838306e25b469cc514ba2ea92b4e6ce4b5)
Dave Airlie [Thu, 27 Dec 2018 06:09:19 +0000 (16:09 +1000)]
virgl/vtest: fix front buffer flush with protocol version 0.
Older versions of virglrenderer before
33da7361aec486290df0aec4ad8dfa8ff6adde2c
in vtest mode, misrender gears.
Fixes:
9d81cd8e7c (virgl: Pass resource size and transfer offsets)
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
(cherry picked from commit
d1ce7eba8b056bfd7d8f29cc0f583777a7ee30e5)
Eric Anholt [Thu, 20 Dec 2018 16:12:50 +0000 (08:12 -0800)]
gallium/ttn: Fix setup of outputs_written.
We need a 64-bit value, otherwise we only handle the low 32, and happen to
sign-extend to claim to write all varying slots if VARYING_SLOT_VAR2 was
used.
Fixes:
4d0b2c7aaac3 ("ttn: Update shader->info as we generate code.")
Reviewed-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit
7d7ecfbcbc2236ba76d9ad9dc7c589ce5a6bfa32)
Lionel Landwerlin [Mon, 3 Dec 2018 18:40:10 +0000 (18:40 +0000)]
anv: don't do partial resolve on layer > 0
We've made the choice not to use fast clears on layer > 0 with
multilayer images. This is partly because we would need to store
multiple clear colors for each layer, making the existing memory
layout, already including aux surfaces, fast clear color, image state,
etc... even more complex.
Partial resolves are the operations transfering the clear colors into
the auxiliary buffers. This operation is currently implemented in
Blorp by loading the clear color from the image's BO, into a shader
that then samples from the auxiliary buffer and writes the color only
if it isn't there already.
The problem here is that because we store only one clear color for all
layers and it is used for partial resolves. If you trigger a partial
clear on a layer > 0, then you're likely to deal with a color that is
not what you actually want. In the particular issues below, we have
multiple layers, each cleared with a different color but the partial
resolve just writes the wrong color into the auxiliary buffers for
layers > 0.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108910
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108911
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
e2ae5f2f0a0dbdae08e026b88e30552728c4abd6)
Axel Davy [Mon, 3 Dec 2018 20:24:54 +0000 (21:24 +0100)]
st/nine: Add src reference to nine_context_range_upload
Just like nine_context_box_upload, nine_context_range_upload
should reference the src, which holds the ram source buffer.
Fixes: https://github.com/iXit/Mesa-3D/issues/327
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
104681c5d528a823a3fdc3f7d9c6f8133c27201c)
Axel Davy [Mon, 3 Dec 2018 20:15:47 +0000 (21:15 +0100)]
st/nine: Bind src not dst in nine_context_box_upload
nine_context_box_upload uploads a ram buffer (from src)
to a pipe_resource (dst).
We already have a refcount on the pipe_resource,
what needs to be protected from release is the ram buffer,
thus a reference to src.
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
42d672fa6a766363e5703f119607f7c7975918aa)
Axel Davy [Sun, 25 Nov 2018 13:37:53 +0000 (14:37 +0100)]
st/nine: Fix volumetexture dtor on ctor failure
The dtor is called on allocation failure,
thus we must check the volumes are allocated
before trying to release them.
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
f91f748fabd7fec8f571124df23296c07102a983)
Alex Deucher [Thu, 20 Dec 2018 15:11:01 +0000 (10:11 -0500)]
pci_ids: add new VegaM pci id
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
516160d717b81141a65a03060ac440a1cad8ae94)
Emil Velikov [Wed, 12 Dec 2018 19:24:14 +0000 (19:24 +0000)]
glx/test: meson: assorted include fixes
Swap '..' with the symbolic inc_glx and add glproto as dependency. That
will pull the correct include, effectively fixing the tests on macOS.
Fixes:
a47c525f328 ("meson: build glx")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
f331419f262d3a0f270376cafbb9517b4627bb7a)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/glx/tests/meson.build
Emil Velikov [Wed, 12 Dec 2018 19:07:52 +0000 (19:07 +0000)]
glx: meson: wire up the dispatch-index-check test
Accidentally dropped with earlier commit.!
Fixes:
4ccb9816737 ("meson: Use consistent style for tests")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
e139d7a8a315502d538b6a753cb42e841c10e57f)
Emil Velikov [Wed, 12 Dec 2018 17:55:08 +0000 (17:55 +0000)]
glx: meson: drop includes from a link-only library
When producing the final libGL.so/libGLX_mesa.so we only link the local
static helper lib (libglx). Thus there's no reason for the includes.
Fixes:
a47c525f328 ("meson: build glx")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
b44875e2dc650c58986480f3360fccfc8d890605)
Emil Velikov [Wed, 12 Dec 2018 17:47:36 +0000 (17:47 +0000)]
TODO: glx: meson: build dri based glx tests, only with -Dglx=dri
The library itself (libGL) is only built when -Dglx=dri, yet it's
accompanying tests are build even with -Dglx=xlib.
Adjust the guards, so we don't build the tests when they are not
applicable
v2:
- Reword commit message (Dylan)
- Drop build_by_default hunk (Dylan)
Fixes:
a47c525f328 ("meson: build glx")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
9527f9ea2611b0793377016c8c16ec58ded7f287)
Emil Velikov [Thu, 13 Dec 2018 04:10:50 +0000 (04:10 +0000)]
pipe-loader: meson: reference correct library
The library is called libgalliumvl_stub - note singular.
Fixes:
42ea0631f10 ("meson: build clover")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
2eedb79e1a2e92648bd245f9db88ecb7b587b7fd)
Emil Velikov [Thu, 13 Dec 2018 03:54:03 +0000 (03:54 +0000)]
meson: don't require glx/egl/gbm with gallium drivers
The gallium drivers do not require a DRI loader. Drop the artificial
and unnecessary restriction.
Fixes:
af9d276134d ("meson: build libmesa_gallium")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
9d10581897ef7cfa0f6c392e2048cc04357281b9)
Caio Marcelo de Oliveira Filho [Sat, 15 Dec 2018 00:10:32 +0000 (16:10 -0800)]
nir: properly find the entry to keep in copy_prop_vars
When copy propagation handles a store/copy, it iterates the current
copy entries to remove aliases, but keeps the "equal" entry (if
exists) to be updated.
The removal step may swap the entries around (to ensure there are no
holes), invalidating previous iteration pointers. The bug was saving
such pointer to use later. Change the code to first perform the
removals and then find the remaining right entry.
This was causing updates to be lost since they were being made to an
entry that was not part of the current copies.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108624
Fixes:
b3c61469255 "nir: Copy propagation between blocks"
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
947f7b452a550c66cfb9a8c9518e35635eb25947)
Caio Marcelo de Oliveira Filho [Sat, 15 Dec 2018 06:19:24 +0000 (22:19 -0800)]
nir: properly clear the entry sources in copy_prop_vars
When updating a copy entry source value from a "non-SSA" (the data
come from a copy instruction) to a "SSA" (the data or parts of it come
from SSA values), it was possible to hold invalid data in ssa[0]
depending on the writemask. Because the union, ssa[0] could contain a
pointer to a nir_deref_instr left-over from previous non-SSA usage.
Change code to clean up the array before use to avoid invalid data
around.
Fixes:
62332d139c8 "nir: Add a local variable-based copy propagation pass"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
0ddc911f4d83a3c698ea02696e1b8706b2cce381)
Vinson Lee [Tue, 18 Dec 2018 17:42:04 +0000 (09:42 -0800)]
meson: Fix libsensors detection.
Fixes:
5e71efef44b9 ("meson: Add lmsensors support")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
0f7ba5758bd8a3e12b8b33ab471336eaa7dd6fbc)
Vinson Lee [Mon, 17 Dec 2018 00:35:00 +0000 (16:35 -0800)]
meson: Fix typo.
Fixes:
6b4c7047d571 ("meson: build gallium nine state_tracker")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
84f39e5971d77549293a1b8abd479cca2ff4b97e)
Ian Romanick [Tue, 18 Dec 2018 02:48:17 +0000 (18:48 -0800)]
Revert "nir/lower_indirect: Bail early if modes == 0"
"There's no point in walking the program if we're never going to
actually lower anything."
Except we might lower compacted local arrays. In that case, modes will
be 0, but there is still lowering to be done.
This reverts commit
7f75cf2a9408b9af562e033ef6c1d1fd15141421.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109081
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Clayton Craft <clayton.a.craft@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
29e4b949b45b468c366b9865298391c89ba6642c)
Dylan Baker [Tue, 4 Dec 2018 18:06:08 +0000 (10:06 -0800)]
meson: Add toggle for glx-direct
GNU Hurd needs to turn off glx-direct, rather than special case it,
we'll just add a toggle.
CC: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit
7a90886921eb1d5d73b40aadd6fd3f340041bd26)
Dylan Baker [Tue, 4 Dec 2018 17:56:30 +0000 (09:56 -0800)]
meson: Add support for gnu hurd
CC: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit
8c77f4c76ddfe0b692b430b012b65f6981a53336)
Dylan Baker [Tue, 4 Dec 2018 17:28:10 +0000 (09:28 -0800)]
meson: Fix ppc64 little endian detection
Old versions of meson returned ppc64le as the cpu_family for little
endian power8 cpus, versions >=0.48 don't do this, so the check wouldn't
work in that case. This generalizes the check to work for both old and
new versions of meson.
Fixes:
34bbb24ce7702658cdc4e9d34a650e169716c39e
("meson: Add support for ppc assembly/optimizations")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit
e430a034b9d2be626557931cd29808a3161889f1)
Ian Romanick [Thu, 21 Jun 2018 00:18:30 +0000 (17:18 -0700)]
i965/vec4/dce: Don't narrow the write mask if the flags are used
In an instruction sequence like
cmp(8).ge.f0.0 vgrf17:D, vgrf2.xxxx:D, vgrf9.xxxx:D
(+f0.0) sel(8) vgrf1:UD, vgrf8.xyzw:UD, vgrf1.xyzw:UD
The other fields of vgrf17 may be unused, but the CMP still needs to
generate the other flag bits.
To my surprise, nothing in shader-db or any test suite appears to hit
this. However, I have a change to brw_vec4_cmod_propagation that
creates cases where this can happen. This fix prevents a couple dozen
regressions in that patch.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
5df88c20 ("i965/vec4: Rewrite dead code elimination to use live in/out.")
(cherry picked from commit
440c051340669e809511c05370d6d703c70f6d0e)
Rhys Perry [Fri, 14 Dec 2018 16:47:09 +0000 (16:47 +0000)]
radv: don't set surf_index for stencil-only images
Fixes:
f8d5b377c8b ('radv: set cb base tile swizzles for MRT speedups (v4)')
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108116
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
bba94a3d85c8799b2441a5d41015091e8903738f)
Jason Ekstrand [Thu, 6 Dec 2018 20:31:20 +0000 (14:31 -0600)]
nir/constant_folding: Fix source bit size logic
Instead of looking at input_sizes[i] which contains the number of
components for each source, we look at the bit size of input_types[i].
This fixes a regression in the 1-bit boolean series though I have no
idea how we haven't seen it before now.
Fixes:
35baee5dce5 "nir/constant_folding: fix incorrect bit-size check"
Fixes:
9076c4e289d "nir: update opcode definitions for different bit sizes"
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
3595a0abf43be3ce27d88f5939b257a74e90035b)
[Emil: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/compiler/nir/nir_opt_constant_folding.c
Jan Vesely [Thu, 13 Dec 2018 20:53:42 +0000 (15:53 -0500)]
clover: Fix build after clang r348827
CodeGenOptions were moved to Basic.
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Aaron Watry <awatry@gmail.com>
Tested-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Kai Wasserbäch <kai@dev.carbon-project.org>
CC: mesa-stable@lists.freedesktop.org
(cherry picked from commit
e4f9a37ace750646fd75fbbdff9b5e77a0b26cfb)
Eric Anholt [Tue, 11 Dec 2018 00:47:13 +0000 (16:47 -0800)]
v3d: Add missing flagging of SYNCB as a TSY op.
Fixes:
f2e41daac577 ("broadcom/vc5: Update QPU instruction pack/unpack for v4.2.")
(cherry picked from commit
ff80e58b38a13c97a4ee598497e3e7b886918087)
Eric Anholt [Wed, 12 Dec 2018 00:14:03 +0000 (16:14 -0800)]
v3d: Make sure that a thrsw doesn't split a multop from its umul24.
The thrsw will invalidate rtop, just like accumulators and flags. Caught
by simulator assertions in CS imulextended/umulextended tests.
Fixes:
90269ba35333 ("broadcom/vc5: Use THRSW to enable multi-threaded shaders.")
(cherry picked from commit
3f9bcf9136af794d44fa4b0802c0d4df6b170175)
Alex Deucher [Fri, 7 Dec 2018 21:10:33 +0000 (16:10 -0500)]
pci_ids: add new vega20 pci id
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
4db4b3447d5258a26a805766e156ea0a338c95b7)
Alex Deucher [Fri, 7 Dec 2018 21:09:16 +0000 (16:09 -0500)]
pci_ids: add new vega10 pci ids
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
56cf25a114436dfc4006296ecef820057f7391b6)
Dave Airlie [Thu, 13 Dec 2018 03:29:04 +0000 (03:29 +0000)]
radv/xfb: fix counter buffer bounds checks.
If we gave this function 0 counter buffers, we'd still try and
access pCounterBuffers[0] as this check was incorrect.
Fixes crash with ext_transform_feedback-pipeline-basic-primgen
on zink on radv.
Fixes:
677b496b6 (radv: fix begin/end transform feedback with 0 counter buffers.)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
b3f2b03ece06327276b183d34fc6f94a2424f094)
Emil Velikov [Tue, 11 Dec 2018 16:20:40 +0000 (16:20 +0000)]
glx: mandate xf86vidmode only for "drm" dri platforms
Currently we have the three dri "platforms" - drm, apple and windows.
Since xf86vidmode is a thing only for the drm one, adjust the
preprocessor guards and correctly check for the dependency.
v2: terminate the GLX_USE_WINDOWSGL hunk
Cc: Jon TURNEY <jon.turney@dronecode.org.uk>
Fixes:
5bc509363b6 ("glx: make xf86vidmode mandatory for direct rendering")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit
a95ec13879d4f04d01fc04a62503578e85c846a8)
Squashed with commit:
glx: Fix compilation with GLX_USE_WINDOWSGL
Sadly, the GLX_USE_APPLEGL and GLX_USE_WINDOWSGL cases are not identical
(because GLX_USE_WINDOWSGL uses vtables rather than a maze of ifdefs)
Include <sys/time.h> again, as functions prototyped by it are used in
the GLX_USE_WINDOWSGL path.
Make the include guard around the __glxGetMscRate() definition match the
one at it's declaration again, as it's referenced from dri_common.c
which is built for GLX_USE_WINDOWSGL.
Fixes:
a95ec138 ("glx: mandate xf86vidmode only for "drm" dri platforms")
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
d512b35b62ff928b880a67887d36f1568aaa5e4b)
Erik Faye-Lund [Tue, 11 Dec 2018 14:02:53 +0000 (14:02 +0000)]
virgl: work around bad assumptions in virglrenderer
Virglrenderer does the wrong thing when given an instance divisor;
it tries to use the element-index rather than the binding-index as
the argument to glVertexBindingDivisor(). This worked fine as long
as there was a 1:1 relationship between elements and bindings,
which was the case util
19a91841c34 "st/mesa: Use Array._DrawVAO in
st_atom_array.c.".
So let's detect instance divisors, and restore a 1:1 relationship in
that case. This will make old versions of virglrenderer behave
correctly. For newer versions, we can consider making a better
interface, where the instance divisor isn't specified per element,
but rather per binding. But let's save that for another day.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes:
19a91841c34 "st/mesa: Use Array._DrawVAO in st_atom_array.c."
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-By: Gert Wollny <gert.wollny@collabora.com>
(cherry picked from commit
e888f28d1fd9f125fc70b2f5d1b3c42d8f25ae53)
Erik Faye-Lund [Tue, 11 Dec 2018 12:34:38 +0000 (12:34 +0000)]
virgl: wrap vertex element state in a struct
This just has one member for now; the handle. But this is about to
change.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-By: Gert Wollny <gert.wollny@collabora.com>
(cherry picked from commit
8447b64238773db0e365802315772d1819c1923f)
Samuel Pitoiset [Tue, 9 Oct 2018 12:15:12 +0000 (14:15 +0200)]
radv: switch on EOP when primitive restart is enabled with triangle strips
Otherwise, Yakuza hangs the GPU with DXVK. We don't know if
linetrip and pointlist are affected, so my point is to do that
only for triangle strips.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
d8325f1f07b67c8a31c6786c71e3fd0910bc3b82)
Emil Velikov [Tue, 18 Dec 2018 16:28:17 +0000 (16:28 +0000)]
cherry-ignore: meson: libfreedreno depends upon libdrm (for fence support)
The commit addresses
b4476138d5ad3f8d30c14ee61f2f375edfdbab2a
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Rob Clark [Sat, 8 Dec 2018 18:21:52 +0000 (13:21 -0500)]
mesa/st/nir: fix missing nir_compact_varyings
LinkedTransformFeedback is normally populated, which had nerf'd varying
packing since the check was introduced.
Fixes:
dbd52585fa9 st/nir: Disable varying packing when doing transform feedback.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit
cfe8220904b79ee45083970c0325bf59a140e163)
Kirill Burtsev [Wed, 5 Dec 2018 15:54:27 +0000 (15:54 +0000)]
loader: free error state, when checking the drawable type
Currently we distinguish if the drawable is a window or pixmap by
checking xcb_present_select_input throws an error or not.
Yet, we don't always free the error state returned by xcb.
Cc: Kirill Burtsev <kirill.burtsev@qt.io>
Cc: Boyan Ding <boyan.j.ding@gmail.com>
Fixes:
6bd9ba7d074 ("loader: Add dri3 helper")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
[Emil: add commit message, fixes tag]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
a539316485ddda074ca1b71aebf4a29b65af87c3)
Eric Anholt [Fri, 7 Dec 2018 18:34:40 +0000 (10:34 -0800)]
v3d: Fix a leak of the disassembled instruction string during debug dumps.
Fixes:
ade416d02369 ("broadcom: Add VC5 NIR compiler.")
(cherry picked from commit
f1d98204c34d36876e05e1d3f2242296ccec19e3)
Eric Anholt [Fri, 7 Dec 2018 18:31:27 +0000 (10:31 -0800)]
vc4: Fix a leak of the transfer helper on screen destroy.
Fixes:
d009463a6549 ("vc4: Switch to using u_transfer_helper for MSAA maps.")
(cherry picked from commit
7f8d8b7d27868037a146f7fca04fef56b29bb85e)
Eric Anholt [Fri, 7 Dec 2018 18:30:09 +0000 (10:30 -0800)]
v3d: Fix a leak of the transfer helper on screen destroy.
Fixes:
7a30517cce8f ("broadcom/vc5: Start adding support for rendering to Z32F_S8X24_UINT.")
(cherry picked from commit
3bd73d31a862fd1e198a7c83ec656a4a376c593a)
Rob Clark [Fri, 7 Dec 2018 19:11:01 +0000 (14:11 -0500)]
freedreno/drm: fix memory leak
Fix an emberrasing memory leak with the non-softpin submit/rb
implementation.
Fixes:
f3cc0d27475 freedreno: import libdrm_freedreno + redesign submit
Signed-off-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit
d014af98b7afc69f4f733c8b8b6f2e3438e68407)
Emil Velikov [Mon, 17 Dec 2018 16:25:40 +0000 (16:25 +0000)]
bin/get-pick-list.sh: warn when commit lists invalid sha
We had cases where people would list old/invalid sha in the commit.
Add a trivial checker to catch those and throw a warning.
CC: Juan A. Suarez <jasuarez@igalia.com>
CC: Dylan Baker <dylan@pnwbakers.com>
CC: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit
e0dbfc995370756355f28ac31495eab96a410384)
Emil Velikov [Mon, 17 Dec 2018 15:44:25 +0000 (15:44 +0000)]
bin/get-pick-list.sh: rework handing of sha nominations
Currently our is_sha_nomination does:
- folds any whitespace, attempting to extract sha-like information
- checks that at least one of the shas has landed
Split it in two and do sha-like validation first.
This way, commits with mesa-stable and sha nominations will feature the
fixes/revert/etc instead of stable (a) or will be omitted if not
applicable for the respective branch (b).
Misc examples from 18.3
(a)
-[ stable ]
5bc509363b6 glx: make xf86vidmode mandatory for direct rendering
+[ fixes ]
5bc509363b6 glx: make xf86vidmode mandatory for direct rendering
(b)
-[ stable ]
9a7b3199037 anv/query: flush render target before copying results
CC: Juan A. Suarez <jasuarez@igalia.com>
CC: Dylan Baker <dylan@pnwbakers.com>
CC: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit
6b296f64af5d69a1d0e4cdcda5f8c6d090dd4449)
Emil Velikov [Tue, 11 Dec 2018 21:19:03 +0000 (21:19 +0000)]
docs: add sha256 checksums for 18.3.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Tue, 11 Dec 2018 21:12:55 +0000 (21:12 +0000)]
docs: add release notes for 18.3.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Tue, 11 Dec 2018 19:14:22 +0000 (19:14 +0000)]
Update version to 18.3.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Jason Ekstrand [Mon, 10 Dec 2018 16:57:35 +0000 (10:57 -0600)]
anv,radv: Disable VK_EXT_pci_bus_info
The Vulkan working group recently discovered that we made a mistake in
assuming that PCI domains are 16-bit even though they can potentially be
32-bit values. To fix this, the next spec update will change the types
in the VK_EXT_pci_bus_info struct to be 32 bits which will be a
backwards-incompatible change. Normally, Khronos tries very hard to
never make backwards incompatible changes to specs. Hopefully, the
extension is new enough (2 months) that there are no shipping apps which
use the extension so this should be safe.
This commit disables the extension for both anv and radv in mesa and
should be back-ported to 18.3 ASAP so we avoid any potential issues with
new apps running on old drivers. I'll send out a commit (which we can
also back-port to 18.3 if we really care) to re-enable the extension in
both drivers once this week's spec update ships. The one known use of
this extension is internal to mesa and will continue working with the
extension disabled and will naturally update when we get a new header.
Cc: "18.3" <mesa-stable@lists.freedesktop.org>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
8f401b0ce6e6650e1a85e9bb2be23d5ff08812b8)
[Emil: resolve trivial conflict]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/intel/vulkan/anv_extensions.py
Emil Velikov [Fri, 7 Dec 2018 11:27:49 +0000 (11:27 +0000)]
docs: add sha256 checksums for 18.3.0
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Fri, 7 Dec 2018 11:20:00 +0000 (11:20 +0000)]
docs: update 18.3.0 release notes
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 6 Dec 2018 18:03:25 +0000 (18:03 +0000)]
Update version to 18.3.0 (final)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Wed, 5 Dec 2018 21:36:54 +0000 (21:36 +0000)]
Update version to 18.3.0-rc6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Gurchetan Singh [Mon, 26 Nov 2018 17:54:05 +0000 (09:54 -0800)]
virgl: don't mark buffers as unclean after a write
We can mark the buffer unclean if it's ever bound as a TBO,
SSBO, ABO, or image.
This improves
dEQP-GLES3.performance.buffer.data_upload.function_call.map_buffer_range.new_specified_buffer.flag_write_full.stream_draw
from 9.58 MB/s to 451.17 MB/s.
v2: Track buffer cleanliness as a function of bindings (Ilia).
v3: virgl_modify_clean --> virgl_dirty_res (Erik)
Tested-By: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit
89b4798c0619a2ba99046d5ad36f0e6851625f7a)
With this and previous two patches, the performance of virgl on top of
a r600 (AMD 6870 HD) host improves as follows:
| FPS avg | Score
--------------------------------
before | 8.2 | 343
after | 21.9 | 916
| FPS avg | Score
--------------------------------
before | 13.2 | 333
after | 32.3 | 790