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Sanjay Patel [Tue, 10 May 2016 21:52:15 +0000 (21:52 +0000)]
remove some comments and other cruft from checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269128
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Tim Northover [Tue, 10 May 2016 21:49:40 +0000 (21:49 +0000)]
Revert "MemCpyOpt: combine local load/store sequences into memcpy."
This reverts commit r269125. It was in my tree when I ran "git svn dcommit".
It's really still under review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269127
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Tim Northover [Tue, 10 May 2016 21:48:48 +0000 (21:48 +0000)]
ARM: report an error when attempting to target a misalgined BLX
The CodeGen problem was fixed in r269101, but we still miscompiled assembly
that tried the same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269126
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Tim Northover [Tue, 10 May 2016 21:48:11 +0000 (21:48 +0000)]
MemCpyOpt: combine local load/store sequences into memcpy.
Sort of the BB-local equivalent to idiom-recognizer: if we have a basic-block
that really implements a memcpy operation, backends can benefit from seeing
this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269125
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Hans Wennborg [Tue, 10 May 2016 21:45:55 +0000 (21:45 +0000)]
Loop unroller: set thresholds for optsize and minsize functions to zero
Before r268509, Clang would disable the loop unroll pass when optimizing
for size. That commit enabled it to be able to support unroll pragmas
in -Os builds. However, this regressed binary size in one of Chromium's
DLLs with ~100 KB.
This restores the original behaviour of no unrolling at -Os, but doing it
in LLVM instead of Clang makes more sense, and also allows the pragmas to
keep working.
Differential revision: http://reviews.llvm.org/D20115
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269124
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Sanjay Patel [Tue, 10 May 2016 21:45:51 +0000 (21:45 +0000)]
update test to use FileCheck for tighter checking
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269123
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Sanjay Patel [Tue, 10 May 2016 21:42:09 +0000 (21:42 +0000)]
update test to use FileCheck for tighter checking
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269122
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Lawrence Hu [Tue, 10 May 2016 21:16:49 +0000 (21:16 +0000)]
Enable loopreroll for sext of loop control only IV
This patch extend loopreroll to allow the instruction chain
of loop control only IV has sext.
Differential Revision: http://reviews.llvm.org/D19820
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269121
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Justin Bogner [Tue, 10 May 2016 21:11:26 +0000 (21:11 +0000)]
SDAG: Avoid relying on the return value of SelectCode in SystemZ. NFC
This is a bit of a spot fix for now. I'll try to fix this up more
comprehensively soon.
This is part of the work to have Select return void instead of an
SDNode *, which is in turn part of llvm.org/pr26808.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269120
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Lawrence Hu [Tue, 10 May 2016 21:11:09 +0000 (21:11 +0000)]
Revert r26084: Enable loopreroll for sext of loop control only IV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269119
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Lawrence Hu [Tue, 10 May 2016 21:04:28 +0000 (21:04 +0000)]
Revert r269093: Enable loopreroll for sext of loop control only IV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269117
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Quentin Colombet [Tue, 10 May 2016 20:49:46 +0000 (20:49 +0000)]
[X86] Properly check that EAX is dead when copying EFLAGS.
This fixes a bug introduced in r267623, where we got smarter and avoided to save
EAX before using it. However, we failed to check if any of the subregister of
EAX were alive and thus, missed cases where we have to save EAX before using it.
The problem may happen on every X86/i386/... platform.
This fixes llvm.org/PR27624
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269115
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Sanjay Patel [Tue, 10 May 2016 20:46:54 +0000 (20:46 +0000)]
[InstSimplify] use computeKnownBits on shift amount operands
Do simplifications common to all shift instructions based on the amount shifted:
1. If the shift amount is known larger than the bitwidth, the result is undefined.
2. If the valid bits of the shift amount are all known to be 0, it's a shift by zero, so the shift operand is the result.
Note that we could generalize the shift-by-zero transform into a shift-by-constant if all of the valid bits in the shift
amount are known, but that would have to be done in InstCombine rather than here because it would mean we need to create
a new shift instruction.
Differential Revision: http://reviews.llvm.org/D19874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269114
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Justin Bogner [Tue, 10 May 2016 20:31:53 +0000 (20:31 +0000)]
SDAG: Avoid relying on the return value of SelectCode in Hexagon. NFC
This is a bit of a spot fix for now. I'll try to fix this up more
comprehensively soon.
This is part of the work to have Select return void instead of an
SDNode *, which is in turn part of llvm.org/pr26808.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269112
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Peter Collingbourne [Tue, 10 May 2016 20:23:24 +0000 (20:23 +0000)]
Cloning: Clean up the interface to the CloneFunction function.
Remove the ModuleLevelChanges argument, and the ability to create new
subprograms for cloned functions. The latter was added without review in
r203662, but it has no in-tree clients (all non-test callers pass false
for ModuleLevelChanges [1], so it isn't reachable outside of tests). It
also isn't clear that adding a duplicate subprogram to the compile unit is
always the right thing to do when cloning a function within a module. If
this functionality comes back it should be accompanied with a more concrete
use case.
Furthermore, all in-tree clients add the returned function to the module.
Since that's pretty much the only sensible thing you can do with the function,
just do that in CloneFunction.
[1] http://llvm-cs.pcc.me.uk/lib/Transforms/Utils/CloneFunction.cpp/rCloneFunction
Differential Revision: http://reviews.llvm.org/D18628
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269110
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Chad Rosier [Tue, 10 May 2016 20:22:09 +0000 (20:22 +0000)]
[InstCombine] Fold icmp ugt/ult (udiv i32 C2, X), C1.
This patch adds support for two optimizations:
icmp ugt (udiv C2, X), C1 -> icmp ule X, C2/(C1+1)
icmp ult (udiv C2, X), C1 -> icmp ugt X, C2/C1
Differential Revision: http://reviews.llvm.org/D20123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269109
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Matthias Braun [Tue, 10 May 2016 20:11:58 +0000 (20:11 +0000)]
ScheduleDAGInstrs: Comment on why subreg defs are not seen as uses; NFC
Usually subregister definitions are consider uses of the remaining
lanes that did not get defined. Add a comment why the code in
ScheduleDAGInstrs does not add use dependencies regardless.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269107
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Kit Barton [Tue, 10 May 2016 20:11:24 +0000 (20:11 +0000)]
[SystemZ] Add support for additional branch extended mnemonics
Added support for extended mnemonics for the following branch instructions and
load/store-on-condition opcodes:
BR, LOCR, LOCGR, LOC, LOCG, STOC, STOCG
Phabricator: http://reviews.llvm.org/D19729
Committing on behalf of Zhan Liau
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269106
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Davide Italiano [Tue, 10 May 2016 19:49:47 +0000 (19:49 +0000)]
[SCCP] Partially propagate informations when the input is not fully defined.
With this patch:
%r1 = lshr i64 -1,
4294967296 -> undef
Before this patch:
%r1 = lshr i64 -1,
4294967296 -> 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269105
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Chris Bieneman [Tue, 10 May 2016 19:45:17 +0000 (19:45 +0000)]
[CMake] Add some extra variables to LLVMConfig.cmake.in
Compiler-RT needs LLVM_LIBRARY_DIR, LLVM_BINARY_DIR.
Setting these in LLVMConfig.cmake will allow Compiler-RT to not need to run llvm-config as long as the LLVMConfig.cmake module is in the CMake module path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269104
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Adrian Prantl [Tue, 10 May 2016 19:38:51 +0000 (19:38 +0000)]
Debug Info: Prevent DW_AT_abstract_origin from being emitted twice
for the same subprogram.
This fixes a bug where DW_AT_abstract_origin is being emitted twice for
the same subprogram if a function is both inlined and emitted in the same
translation unit, by restoring the pre-r266446 behavior.
http://reviews.llvm.org/D20072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269103
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Tim Northover [Tue, 10 May 2016 19:17:47 +0000 (19:17 +0000)]
ARM: stop emitting blx instructions for most calls on MachO.
I'm really not sure why we were in the first place, it's the linker's job to
convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls
that could be locally resolved completely unencodable since all offsets to BLX
are multiples of 4.
rdar://
26182344
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269101
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Konstantin Zhuravlyov [Tue, 10 May 2016 18:33:41 +0000 (18:33 +0000)]
[AMDGPU][NFC] Rename SIInsertNops -> SIDebuggerInsertNops
Differential Revision: http://reviews.llvm.org/D20117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269098
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Justin Bogner [Tue, 10 May 2016 18:28:10 +0000 (18:28 +0000)]
LPM: Drop require<loops> from these tests, it's redundant. NFC
The LoopPassManager needs to calculate the loops analysis in order to
iterate over the loops at all. Requiring it is redundant and just adds
noise to the RUN lines here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269097
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Rafael Espindola [Tue, 10 May 2016 18:22:45 +0000 (18:22 +0000)]
Make "@name =" mandatory for globals in .ll files.
An oddity of the .ll syntax is that the "@var = " in
@var = global i32 42
is optional. Writing just
global i32 42
is equivalent to
@0 = global i32 42
This means that there is a pretty big First set at the top level. The
current implementation maintains it manually. I was trying to refactor
it, but then started wondering why keep it a all. I personally find the
above syntax confusing. It looks like something is missing.
This patch removes the feature and simplifies the parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269096
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Peter Collingbourne [Tue, 10 May 2016 18:07:21 +0000 (18:07 +0000)]
Re-apply r269081 and r269082 with a fix for MSVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269094
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Lawrence Hu [Tue, 10 May 2016 18:00:42 +0000 (18:00 +0000)]
Enable loopreroll for sext of loop control only IV
This patch extend loopreroll to allow the instruction chain
of loop control only IV has sext.
Differential Revision: http://reviews.llvm.org/D19820
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269093
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Mandeep Singh Grang [Tue, 10 May 2016 17:57:27 +0000 (17:57 +0000)]
Fix PR26655: Bail out if all regs of an inst BUNDLE have the correct kill flag
Summary:
While setting kill flags on instructions inside a BUNDLE, we bail out as soon
as we set kill flag on a register. But we are missing a check when all the
registers already have the correct kill flag set. We need to bail out in that
case as well.
This patch refactors the old code and simply makes use of the addRegisterKilled
function in MachineInstr.cpp in order to determine whether to set/remove kill
on an instruction.
Reviewers: apazos, t.p.northover, pete, MatzeB
Subscribers: MatzeB, davide, llvm-commits
Differential Revision: http://reviews.llvm.org/D17356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269092
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Peter Collingbourne [Tue, 10 May 2016 17:54:43 +0000 (17:54 +0000)]
Revert r269081 and r269082 while I try to find the right incantation to fix MSVC build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269091
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Rong Xu [Tue, 10 May 2016 17:45:33 +0000 (17:45 +0000)]
[PGO] resubmit r268969
Put the test into a target specific directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269090
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Lawrence Hu [Tue, 10 May 2016 17:42:27 +0000 (17:42 +0000)]
Enable loopreroll for sext of loop control only IV
This patch extend loopreroll to allow the instruction chain
of loop control only IV has sext.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269084
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Dan Gohman [Tue, 10 May 2016 17:39:48 +0000 (17:39 +0000)]
[WebAssembly] Preliminary fast-isel support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269083
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Peter Collingbourne [Tue, 10 May 2016 17:35:30 +0000 (17:35 +0000)]
Use doxygen style comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269082
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Peter Collingbourne [Tue, 10 May 2016 17:34:21 +0000 (17:34 +0000)]
WholeProgramDevirt: Move logic for finding devirtualizable call sites to Analysis.
The plan is to eventually make this logic simpler, however I expect it to
be a little tricky for the foreseeable future (at least until we're rid of
pointee types), so move it here so that it can be reused to build a summary
index for devirtualization.
Differential Revision: http://reviews.llvm.org/D20005
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269081
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Rafael Espindola [Tue, 10 May 2016 17:16:45 +0000 (17:16 +0000)]
Simplify LLParser::ParseOptionalLinkage. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269080
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Simon Pilgrim [Tue, 10 May 2016 16:55:20 +0000 (16:55 +0000)]
[X86][AVX512] Added another masked shuffle combine from load test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269077
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Krzysztof Parzyszek [Tue, 10 May 2016 16:50:30 +0000 (16:50 +0000)]
[ScheduleDAG] Make sure to process all def operands before any use operands
An example from Hexagon where things went wrong:
%R0<def> = L2_loadrigp <ga:@fp04> ; load function address
J2_callr %R0<kill>, ..., %R0<imp-def> ; call *R0, return value in R0
ScheduleDAGInstrs::buildSchedGraph would visit all instructions going
backwards, and in each instruction it would visit all operands in their
order on the operand list. In the case of this call, it visited the use
of R0 first, then removed it from the set Uses after it visited the def.
This caused the DAG to be missing the data dependence edge on R0 between
the load and the call.
Differential Revision: http://reviews.llvm.org/D20102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269076
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Marcin Koscielnicki [Tue, 10 May 2016 16:49:04 +0000 (16:49 +0000)]
[PR27599] [SystemZ] [SelectionDAG] Fix extension of atomic cmpxchg result.
Currently, SelectionDAG assumes 8/16-bit cmpxchg returns either a sign
extended result, or a zero extended result. SystemZ takes a third
option by returning junk in the high bits (rotated contents of the other
bytes in the memory word). In that case, don't use Assert*ext, and
zero-extend the result ourselves if a comparison is needed.
Differential Revision: http://reviews.llvm.org/D19800
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269075
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Nadav Rotem [Tue, 10 May 2016 16:23:54 +0000 (16:23 +0000)]
Update my email address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269073
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Simon Pilgrim [Tue, 10 May 2016 16:08:24 +0000 (16:08 +0000)]
[X86][AVX] Added some shuffle combine from load tests
As discussed on D19198 - we need to check what happens when we shuffle with different value type to the load
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269068
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Teresa Johnson [Tue, 10 May 2016 15:54:09 +0000 (15:54 +0000)]
[ThinLTO] Add option to emit imports files for distributed backends
Summary:
Add support for emission of plaintext lists of the imported files for
each distributed backend compilation. Used for distributed build file
staging.
Invoked with new gold-plugin thinlto-emit-imports-files option, which is
only valid with thinlto-index-only (i.e. for distributed builds), or
from llvm-lto with new -thinlto-action=emitimports value.
Depends on D19556.
Reviewers: joker.eph
Subscribers: llvm-commits, joker.eph
Differential Revision: http://reviews.llvm.org/D19636
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269067
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Renato Golin [Tue, 10 May 2016 14:02:46 +0000 (14:02 +0000)]
[docs] Fix unexpected indentation in HowToCrossCompileLLVM.rst
Seems like my sphynx version is different than the one in the bot, as it
accepted everything locally. I think this is the right fix...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269062
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Teresa Johnson [Tue, 10 May 2016 13:48:23 +0000 (13:48 +0000)]
Restore "[ThinLTO] Emit individual index files for distributed backends"
This restores commit r268627:
Summary:
When launching ThinLTO backends in a distributed build (currently
supported in gold via the thinlto-index-only plugin option), emit
an individual index file for each backend process as described here:
http://lists.llvm.org/pipermail/llvm-dev/2016-April/098272.html
...
Differential Revision: http://reviews.llvm.org/D19556
Address msan failures by avoiding std::prev on map.end(), the
theory is that this is causing issues due to some known UB problems
in __tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269059
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Renato Golin [Tue, 10 May 2016 12:54:12 +0000 (12:54 +0000)]
[docs] Change CrossCompilation guidde to reflect changes in Clang/GCC
HowToCrossCompile was outdated and generating too much traffic on the mailing
list with similar queries. This change helps offset most of the problems that
were reported recently including:
* Removing the -ccc-gcc-name, adding --sysroot
* Making references to Debian's multiarch for target libraries
* Expanding -DCMAKE_CXX_FLAGS for both GCC and Clang
* Some formatting and clarifications in the text
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269054
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Silviu Baranga [Tue, 10 May 2016 12:28:49 +0000 (12:28 +0000)]
[LAA] Use re-written SCEV expressions when computing distances
This removes a redundant stride versioning step (we already
do it in getPtrStride, so it has no effect) and uses PSE to
get the SCEV expressions for the source and destination
(this might have changed when getPtrStride was called).
I discovered this through code inspection, and couldn't
produce a regression test for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269052
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James Molloy [Tue, 10 May 2016 12:27:23 +0000 (12:27 +0000)]
Revert "[VectorUtils] Query number of sign bits to allow more truncations"
This was a fairly simple patch but on closer inspection was seriously flawed and caused PR27690.
This reverts commit r268921.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269051
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Daniel Sanders [Tue, 10 May 2016 12:17:04 +0000 (12:17 +0000)]
[mips][ias] Make the default path unreachable in needsRelocateWithSymbol() (except for N64).
Following post-commit comments on r268900 from Rafael Espindola:
The missing relocations are now explicitly listed in the switch statement with
appropriate FIXME comments and the default path is now unreachable. The
temporary exception to this is that compound relocations for N64 still have a
default path that returns true. This is because fixing that case ought to be a
separate patch.
Also make R_MIPS_NONE return false since it has no effect on the section data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269047
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Jeroen Ketema [Tue, 10 May 2016 11:19:20 +0000 (11:19 +0000)]
[OCaml] Update core test and re-enable testing
Differential Revision: http://reviews.llvm.org/D19828
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269040
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Simon Pilgrim [Tue, 10 May 2016 10:30:00 +0000 (10:30 +0000)]
[X86][AVX512] Added masked version of MOVDDUP test with 16f32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269038
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Chuang-Yu Cheng [Tue, 10 May 2016 09:45:44 +0000 (09:45 +0000)]
Update Debug Intrinsics in RewriteUsesOfClonedInstructions in LoopRotation
Loop rotation clones instruction from the old header into the preheader. If
there were uses of values produced by these instructions that were outside
the loop, we have to insert PHI nodes to merge the two values. If the values
are used by DbgIntrinsics they will be used as a MetadataAsValue of a
ValueAsMetadata of the original values, and iterating all of the uses of the
original value will not update the DbgIntrinsics. The new code checks if the
values are used by DbgIntrinsics and if so, updates them using essentially
the same logic as the original code.
The attached testcase demonstrates the issue. Without the fix, the
DbgIntrinic outside the loop uses values computed inside the loop, even
though these values do not dominate the DbgIntrinsic.
Author: Thomas Jablin (tjablin)
Reviewers: dblaikie aprantl kbarton hfinkel cycheng
http://reviews.llvm.org/D19564
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269034
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Arnaud A. de Grandmaison [Tue, 10 May 2016 09:24:49 +0000 (09:24 +0000)]
[InstCombine] Remove trivially empty va_start/va_end and va_copy/va_end ranges.
When a va_start or va_copy is immediately followed by a va_end (ignoring
debug information or other start/end in between), then it is safe to
remove the pair. As this code shares some commonalities with the lifetime
markers, this has been factored to helper functions.
This InstCombine pattern kicks-in 3 times when running the LLVM test
suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269033
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Chris Dewhurst [Tue, 10 May 2016 09:09:20 +0000 (09:09 +0000)]
[Sparc][LEON] Itineraries unit test.
Added test to check LeonItineraries are being applied by code checked-in two weeks ago in r267121.
Phabricator Review: http://reviews.llvm.org/D19359
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269032
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Daniel Sanders [Tue, 10 May 2016 09:01:54 +0000 (09:01 +0000)]
Clarify the difference between ISD::BITCAST and the bitcast instruction from LLVM-IR.
Subscribers: llvm-commits, hfinkel
Differential Revision: http://reviews.llvm.org/D16464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269031
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Renato Golin [Tue, 10 May 2016 08:23:57 +0000 (08:23 +0000)]
Revert "[PGO] Fix __llvm_profile_raw_version linkage in MACHO IR instrumentation generates a COMDAT symbol __llvm_profile_raw_version to overwrite the same symbol in profile run-time to distinguish IR profiles from Clang generated profiles. In MACHO, LinkOnceODR linkage is used due to the lack of COMDAT support."
This reverts commits r268969, r268979 and r268984. They had target specific test
in generic directories without the correct specifiers and made it hard for us to
come up with a good solution by rapidly committing untested changes.
This test needs to be in a target specific directory or have the correct REQUIRED
identifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269027
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Jonas Paulsson [Tue, 10 May 2016 08:09:37 +0000 (08:09 +0000)]
[foldMemoryOperand()] Pass LiveIntervals to enable liveness check.
SystemZ (and probably other targets as well) can fold a memory operand
by changing the opcode into a new instruction that as a side-effect
also clobbers the CC-reg.
In order to do this, liveness of that reg must first be checked. When
LIS is passed, getRegUnit() can be called on it and the right
LiveRange is computed on demand.
Reviewed by Matthias Braun.
http://reviews.llvm.org/D19861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269026
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Elena Demikhovsky [Tue, 10 May 2016 07:33:35 +0000 (07:33 +0000)]
[LoopVectorize] Handling induction variable with non-constant step.
Allow vectorization when the step is a loop-invariant variable.
This is the loop example that is getting vectorized after the patch:
int int_inc;
int bar(int init, int *restrict A, int N) {
int x = init;
for (int i=0;i<N;i++){
A[i] = x;
x += int_inc;
}
return x;
}
"x" is an induction variable with *loop-invariant* step.
But it is not a primary induction. Primary induction variable with non-constant step is not handled yet.
Differential Revision: http://reviews.llvm.org/D19258
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269023
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Denis Zobnin [Tue, 10 May 2016 05:55:16 +0000 (05:55 +0000)]
[LAA] Rename "isStridedPtr" with "getPtrStride". NFC.
Changing misleading function name was approved in http://reviews.llvm.org/D17268.
Patch by Roman Shirokiy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269021
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Matthias Braun [Tue, 10 May 2016 05:38:47 +0000 (05:38 +0000)]
liveness.mir requires asserts to use -debug-only
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269020
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Craig Topper [Tue, 10 May 2016 05:28:04 +0000 (05:28 +0000)]
[X86][AVX512] Strengthen the assertions from r269001. We need VLX to use the 128/256-bit move opcodes for extended registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269019
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Craig Topper [Tue, 10 May 2016 05:28:02 +0000 (05:28 +0000)]
[X86] Add ZMM registers to the X86_INTR calling convention preserved mask when AVX512 is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269018
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Craig Topper [Tue, 10 May 2016 05:27:56 +0000 (05:27 +0000)]
[X86] Update X86_INTR calling convention to save ZMM registers instead of YMM registers when AVX512 is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269017
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Matthias Braun [Tue, 10 May 2016 04:51:14 +0000 (04:51 +0000)]
LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()
We now use LiveRangeCalc::extendToUses() instead of a specially designed
algorithm in constructMainRangeFromSubranges():
- The original motivation for constructMainRangeFromSubranges() were
differences between the main liverange and subranges because of hidden
dead definitions. This case however cannot happen anymore with the
DetectDeadLaneMasks pass in place.
- It simplifies the code.
- This fixes a longstanding bug where we did not properly create new SSA
values on merging control flow (the MachineVerifier missed most of
these cases).
- Move constructMainRangeFromSubranges() to LiveIntervalAnalysis and
LiveRangeCalc to better match the implementation/available helper
functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269016
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Matthias Braun [Tue, 10 May 2016 04:51:09 +0000 (04:51 +0000)]
LiveInterval: Avoid unnecessary auto, add const; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269015
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Matthias Braun [Tue, 10 May 2016 04:51:07 +0000 (04:51 +0000)]
llc: Print+Verify machine function after loading it
In -run-pass mode verify/print machine function immediately after
loading the .mir file if -verify-machineinstr/-print-machineinstrs
option is specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269014
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Matthias Braun [Tue, 10 May 2016 04:51:04 +0000 (04:51 +0000)]
TargetPassConfig: Set PrintMachineCode even if addMachinePasses() does not run.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269013
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Dan Gohman [Tue, 10 May 2016 04:24:02 +0000 (04:24 +0000)]
[WebAssembly] Move register stackification and coloring to a late phase.
Move the register stackification and coloring passes to run very late, after
PEI, tail duplication, and most other passes. This means that all code emitted
and expanded by those passes is now exposed to these passes. This also
eliminates the need for prologue/epilogue code to be manually stackified,
which significantly simplifies the code.
This does require running LiveIntervals a second time. It's useful to think
of these late passes not as late optimization passes, but as a domain-specific
compression algorithm based on knowledge of liveness information. It's used to
compress the code after all conventional optimizations are complete, which is
why it uses LiveIntervals at a phase when actual optimization passes don't
typically need it.
Differential Revision: http://reviews.llvm.org/D20075
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269012
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Matthias Braun [Tue, 10 May 2016 03:21:59 +0000 (03:21 +0000)]
CodeGen: Move TargetPassConfig from Passes.h to an own header; NFC
Many files include Passes.h but only a fraction needs to know about the
TargetPassConfig class. Move it into an own header. Also rename
Passes.cpp to TargetPassConfig.cpp while we are at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269011
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Matthias Braun [Tue, 10 May 2016 03:21:47 +0000 (03:21 +0000)]
PrologEpilogInserter: Remove unnecessary dependency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269010
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Matthias Braun [Tue, 10 May 2016 03:03:55 +0000 (03:03 +0000)]
Appease MSVC
Apply a similar fix to the one in r269006 to LiveIntervalTest.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269009
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Sanjoy Das [Tue, 10 May 2016 02:35:44 +0000 (02:35 +0000)]
[ValueTracking] Use guards to prove non-nullness of a value
Reviewers: apilipenko, majnemer, reames
Subscribers: mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D20044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269008
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Sanjoy Das [Tue, 10 May 2016 02:35:41 +0000 (02:35 +0000)]
[BasicAA] Guard intrinsics don't write to memory
Summary:
The idea is very close to what we do for assume intrinsics: we mark the
guard intrinsics as writing to arbitrary memory to maintain control
dependence, but under the covers we teach AA that they do not mod any
particular memory location.
Reviewers: chandlerc, hfinkel, gbiv, reames
Subscribers: george.burgess.iv, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D19575
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269007
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Matthias Braun [Tue, 10 May 2016 02:09:32 +0000 (02:09 +0000)]
Try to appease clang-x64-ninja-win7 bot.
Looks like you need the complete definition of "X" when calling a "X
&func()" declared function even when not using the result further.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269006
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Matthias Braun [Tue, 10 May 2016 01:32:44 +0000 (01:32 +0000)]
llc: Rework -run-pass option
We now construct a custom pass pipeline instead of injecting
start-before/stop-after into the default pipeline construction. This
allows to specify any pass known to the pass registry. Previously
specifying indirectly added analysis passes or passes not added to the
pipeline add all would not be added and we would silently do nothing.
This also restricts the -run-pass option to cases with .mir input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269003
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Matthias Braun [Tue, 10 May 2016 01:32:40 +0000 (01:32 +0000)]
LLVMTargetMachine: Add functions to create MIModuleInfo/MIFunction; NFC
Add convenience function to create MachineModuleInfo and
MachineFunctionAnalysis passes and add them to a pass manager.
Despite factoring out some shared code in
LiveIntervalTest/LLVMTargetMachine this will be used by my upcoming llc
change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269002
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Quentin Colombet [Tue, 10 May 2016 01:09:14 +0000 (01:09 +0000)]
[X86][AVX512] Use the proper load/store for AVX512 registers.
When loading or storing AVX512 registers we were not using the AVX512
variant of the load and store for VR128 and VR256 like registers.
Thus, we ended up with the wrong encoding and actually were dropping the
high bits of the instruction. The result was that we load or store the
wrong register. The effect is visible only when we emit the object file
directly and disassemble it. Then, the output of the disassembler does
not match the assembly input.
This is related to llvm.org/PR27481.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269001
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Evgeniy Stepanov [Tue, 10 May 2016 00:33:07 +0000 (00:33 +0000)]
Don't inline functions with different SafeStack attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268999
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Sanjoy Das [Tue, 10 May 2016 00:32:31 +0000 (00:32 +0000)]
[SCEVExpander] Clang format expressions; NFC
The boolean expressions are somewhat hard to read otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268998
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Sanjoy Das [Tue, 10 May 2016 00:31:49 +0000 (00:31 +0000)]
[SCEV] Use guards to prove predicates
We can use calls to @llvm.experimental.guard to prove predicates,
relying on the fact that in all locations domianted by a call to
@llvm.experimental.guard the predicate it is guarding is known to be
true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268997
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Justin Lebar [Tue, 10 May 2016 00:31:25 +0000 (00:31 +0000)]
[nvvm] Mark ldu and ldg intrinsics as IntrArgMemOnly.
Summary:
Previously these intrinsics were marked as can-read any memory address.
Now they're marked as reading only the pointer they're passed.
Reviewers: rnk
Subscribers: jholewinski, llvm-commits, tra
Differential Revision: http://reviews.llvm.org/D20080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268996
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Justin Lebar [Tue, 10 May 2016 00:31:23 +0000 (00:31 +0000)]
Minor formatting fixes in LoopUnroll.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268995
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Justin Lebar [Tue, 10 May 2016 00:31:22 +0000 (00:31 +0000)]
[NVPTX] Change begin/end inline asm comments to "begin/end inline asm".
Previously it was just "// inline asm", which made it tricky to read
code with lots of inline assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268994
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Justin Lebar [Tue, 10 May 2016 00:31:20 +0000 (00:31 +0000)]
[NVVM] Add comments to NVVM intrinsics listing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268993
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Derek Schuff [Tue, 10 May 2016 00:14:07 +0000 (00:14 +0000)]
[WebAssembly] Disable 128-bit shift libcalls
Currently the signature of the functions
i128(i128, i32) aka void(i32, i64, i64, i32) doesn't match the signature
of the call emitted by the default lowering, void(i32, i64, i64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268991
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Justin Bogner [Mon, 9 May 2016 23:54:23 +0000 (23:54 +0000)]
SDAG: Stop relying on Select's return value in SystemZ's splitLargeImmediate. NFC
The call to Select on Upper here happens in an unusual order in order
to defeat the constant folding that getNode() does. Add a comment
explaining why we can't just move the Select to later to avoid a
Handle, and wrap the call to SelectCode in a handle so we don't need
its return value.
This is part of the work to have Select return void instead of an
SDNode *, which is in turn part of llvm.org/pr26808.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268990
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Eugene Zelenko [Mon, 9 May 2016 23:11:38 +0000 (23:11 +0000)]
Fix some Clang-tidy modernize-deprecated-headers and Include What You Use warnings; other minor fixes.
Differential revision: http://reviews.llvm.org/D20042
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268989
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Adam Nemet [Mon, 9 May 2016 23:03:44 +0000 (23:03 +0000)]
[LV] Hint at the new loop distribution pragma in optimization remark
When we encounter unsafe memory dependencies, loop distribution could
help.
Even though, the diagnostics is in LAA, it's only currently emitted in
the vectorizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268987
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Adam Nemet [Mon, 9 May 2016 23:03:06 +0000 (23:03 +0000)]
[IndirectCallPromotion] Remove duplicate comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268986
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Adrian Prantl [Mon, 9 May 2016 22:59:55 +0000 (22:59 +0000)]
Disable this unit test on MSVC, which crashes while compiling it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268985
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Rong Xu [Mon, 9 May 2016 22:45:47 +0000 (22:45 +0000)]
Fix buildbot failure from r268968.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268984
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Quentin Colombet [Mon, 9 May 2016 22:37:05 +0000 (22:37 +0000)]
[X86] Fix the AllRegs AVX calling convention.
We used to list registers that were not in the AVX space. In other
words, we were pushing registers that the ISA cannot encode
(YMM16-YMM31).
This is part of llvm.org/PR27481.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268983
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Sanjay Patel [Mon, 9 May 2016 21:51:53 +0000 (21:51 +0000)]
[Inliner] don't assume that a Constant alloca size is a ConstantInt (PR27277)
Differential Revision: http://reviews.llvm.org/D20077
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268980
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Rong Xu [Mon, 9 May 2016 21:51:50 +0000 (21:51 +0000)]
Fix buildbot failure from r268968.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268979
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Chad Rosier [Mon, 9 May 2016 21:37:43 +0000 (21:37 +0000)]
Typo. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268975
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Xinliang David Li [Mon, 9 May 2016 21:37:12 +0000 (21:37 +0000)]
Cleanup followup of r268710 - [PM] port IR based PGO prof-gen pass to new pass manager
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268974
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Quentin Colombet [Mon, 9 May 2016 21:24:31 +0000 (21:24 +0000)]
[X86] Strengthen the setting of inline asm constraints for fp regclasses.
This is similar to r268953, but for floating point and vector register
classes.
Explanations:
The setting of the inline asm constraints was implicitly relying on the
order of the register classes in the file generated by tablegen.
Since, we do not have any control on that order, make sure we do not
depend on it anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268973
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Simon Pilgrim [Mon, 9 May 2016 21:14:38 +0000 (21:14 +0000)]
[X86][SSE] Improve cost model for i64 vector comparisons on pre-SSE42 targets
As discussed on PR24888, until SSE42 we don't have access to PCMPGTQ for v2i64 comparisons, but the cost models don't reflect this, resulting in over-optimistic vectorizaton.
This patch adds SSE2 'base level' costs that match what a typical target is capable of and only reduces the v2i64 costs at SSE42.
Technically SSE41 provides a PCMPEQQ v2i64 equality test, but as getCmpSelInstrCost doesn't give us a way to discriminate between comparison test types we can't easily make use of this, otherwise we could split the cost of integer equality and greater-than tests to give better costings of each.
Differential Revision: http://reviews.llvm.org/D20057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268972
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Rong Xu [Mon, 9 May 2016 21:03:06 +0000 (21:03 +0000)]
[PGO] Fix __llvm_profile_raw_version linkage in MACHO
IR instrumentation generates a COMDAT symbol __llvm_profile_raw_version to
overwrite the same symbol in profile run-time to distinguish IR profiles from
Clang generated profiles. In MACHO, LinkOnceODR linkage is used due to the
lack of COMDAT support.
But LinkOnceODR linkage might have .weak_def_can_be_hidden assembly directive,
while the weak variable in run-time has a .weak_definition directive. Linker
will not merge these two symbols even they have the same name. The end result
is IR profiles are not properly flagged in MACHO.
This patch changes the linkage for __llvm_profile_raw_version in each module to
LinkOnceAny so that it has same .weak_definition directive as in the run-time.
Differential Revision: http://reviews.llvm.org/D20078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268969
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Kostya Serebryany [Mon, 9 May 2016 21:02:36 +0000 (21:02 +0000)]
[libFuzzer] add a test for libFuzzer+ubsan, extend the docs on using libFuzzer+ubsan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268968
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Marcin Koscielnicki [Mon, 9 May 2016 20:57:36 +0000 (20:57 +0000)]
[MSan] [AArch64] Fix vararg helper for >1 or non-int fixed arguments.
This fixes http://llvm.org/PR27646 on AArch64.
There are three issues here:
- The GR save area is 7 words in size, instead of 8. This is not enough
if none of the fixed arguments is passed in GRs (they're all floats or
aggregates).
- The first argument is ignored (which counteracts the above if it's passed
in GR).
- Like x86_64, fixed arguments landing in the overflow area are wrongly
counted towards the overflow offset.
Differential Revision: http://reviews.llvm.org/D20023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268967
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Adrian Prantl [Mon, 9 May 2016 19:57:29 +0000 (19:57 +0000)]
Separate the Verifier into an analysis and a transformation pass and
allow the transformation to strip invalid debug info.
This patch separates the Verifier into an analysis and a transformation
pass, with the transformation pass optionally stripping malformed
debug info.
The problem I'm trying to solve with this sequence of patches is that
historically we've done a really bad job at verifying debug info. We want
to be able to make the verifier stricter without having to worry about
breaking bitcode compatibility with existing producers. For example, we
don't necessarily want IR produced by an older version of clang to be
rejected by an LTO link just because of malformed debug info, and rather
provide an option to strip it. Note that merely outdated (but well-formed)
debug info would continue to be auto-upgraded in this scenario.
http://reviews.llvm.org/D19988
rdar://problem/
25818489
This reapplies r268937 without modifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268966
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