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Chad Reese [Thu, 15 Jan 2015 13:11:16 +0000 (16:11 +0300)]
MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits.
CN38XX pass 1 required icache prefetching to be turned off. This chip never
reached production and is long dead. Other processor specific icache settings
are done by the bootloader. Remove these bits from the kernel.
Signed-off-by: Chad Reese <kreese@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/8944/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Thu, 15 Jan 2015 13:11:15 +0000 (16:11 +0300)]
MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8943/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Thu, 15 Jan 2015 13:11:14 +0000 (16:11 +0300)]
MIPS: OCTEON: Update octeon-model.h code for new SoCs.
Add coverage for OCTEON III models.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8942/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Thu, 15 Jan 2015 13:11:13 +0000 (16:11 +0300)]
MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX
Make messages refer to all CN6XXX.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8941/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Thu, 15 Jan 2015 13:11:12 +0000 (16:11 +0300)]
MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h
Also update union octeon_cvmemctl with new OCTEON II fields.
[aleksey.makarov@auriga.com: use __BITFIELD_FIELD]
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8940/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Thu, 15 Jan 2015 13:11:10 +0000 (16:11 +0300)]
MIPS: OCTEON: Implement the core-16057 workaround
Disable ICache prefetch for certian Octeon II processors.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8938/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Aleksey Makarov [Thu, 15 Jan 2015 13:11:09 +0000 (16:11 +0300)]
MIPS: OCTEON: Delete unused COP2 saving code
Commit
2c952e06e4f5 ("MIPS: Move cop2 save/restore to switch_to()")
removes assembler code to store COP2 registers. Commit
a36d8225bceb ("MIPS: OCTEON: Enable use of FPU") mistakenly
restores it
Fixes:
a36d8225bceb ("MIPS: OCTEON: Enable use of FPU")
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/8937/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Chandrakala Chavva [Thu, 15 Jan 2015 13:11:08 +0000 (16:11 +0300)]
MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register
Use dmfc0/dmtc0 instructions for reading CvmMemCtl COP0 register,
its a 64-bit wide.
Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/8936/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Thu, 15 Jan 2015 13:11:07 +0000 (16:11 +0300)]
MIPS: OCTEON: Save and restore CP2 SHA3 state
Allocate new save space, and then save/restore the registers if
OCTEON III.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8935/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Thu, 15 Jan 2015 13:11:06 +0000 (16:11 +0300)]
MIPS: OCTEON: Fix FP context save.
It wasn't being saved on task switch.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8934/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Thu, 15 Jan 2015 13:11:05 +0000 (16:11 +0300)]
MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs
The wide multiplier is twice as wide, so we need to save twice as much
state. Detect the multiplier type (CPU type) at start up and install
model specific handlers.
[aleksey.makarov@auriga.com:
conflict resolution,
support for old compilers]
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Leonid Rosenboim <lrosenboim@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8933/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Markos Chandras [Mon, 16 Feb 2015 15:13:11 +0000 (15:13 +0000)]
MIPS: boot: Provide more uImage options
Allow more compression algorithms as well as uncompressed uImage.bin
to be generated. An uncompressed image might be useful to rule out
problems in the decompression code in the bootloader or even speed
up the boot process at the expense of a bigger uImage file.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9271/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Thu, 18 Dec 2014 10:59:53 +0000 (13:59 +0300)]
MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8737/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Lars-Peter Clausen [Sun, 11 Jan 2015 16:06:56 +0000 (17:06 +0100)]
MIPS: ip22-gio: Remove legacy suspend/resume support
There are currently no gio device drivers that implement suspend/resume
and this patch removes the bus specific legacy suspend and resume callbacks.
This will allow us to eventually remove struct bus_type legacy suspend and
resume support altogether.
gio device drivers wanting to implement suspend and resume can use dev PM
ops which will work out of the box without further modifications necessary.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8920/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Zubair Lutfullah Kakakhel [Fri, 12 Dec 2014 12:45:39 +0000 (12:45 +0000)]
mips: pci: Add ifdef around pci_proc_domain
Without these, there are multiple definitions of pci_proc_domain()
and pci_domain_nr() if linux/pci.h and asm/pci.h are included.
Add #ifdefs around them
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Markos Chandras <Markos.Chandras@imgtec.com>
Cc: Markos.Chandras@imgtec.com
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8670/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Manuel Lauss [Wed, 18 Feb 2015 10:01:56 +0000 (11:01 +0100)]
MIPS: Alchemy: Fix cpu clock calculation
The current code uses bits 0-6 of the sys_cpupll register to calculate
core clock speed. However this is only valid on Au1300, on all earlier
models the hardware only uses bits 0-5 to generate core clock.
This fixes clock calculation on the MTX1 (Au1500), where bit 6 of cpupll
is set as well, which ultimately lead the code to calculate a bogus cpu
core clock and also uart base clock down the line.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Reported-by: John Crispin <blogic@openwrt.org>
Tested-by: Bruno Randolf <br1@einfach.org>
Cc: stable@vger.kernel.org [v3.17+]
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9279/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Manuel Lauss [Thu, 29 Jan 2015 15:06:44 +0000 (16:06 +0100)]
MIPS: Alchemy: remove declaration for set_cpuspec
set_cpuspec() has been dropped with commit
074cf656700ddd1d2bd7f815f78e785418beb898
("MIPS: Alchemy: remove cpu_table.") in late 2008.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9150/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Manuel Lauss [Thu, 29 Jan 2015 15:06:43 +0000 (16:06 +0100)]
MIPS: Alchemy: preset loops_per_jiffy based on CPU clock
This was lost during the rewrite of clock framework support.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9149/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Manuel Lauss [Thu, 29 Jan 2015 15:06:42 +0000 (16:06 +0100)]
MIPS: Alchemy: fix Au1000/Au1500 LRCLK calculation
The Au1000 and Au1500 calculate the LRCLK a bit differently than
newer models: a single bit in MEM_STCFG0 selects if pclk is divided
by 4 or 5.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9148/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Steven J. Hill [Thu, 19 Feb 2015 16:18:52 +0000 (10:18 -0600)]
MIPS: Add set/clear CP0 macros for PageGrain register
Build set and clear macros for the PageGrain register.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9289/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Steven J. Hill [Thu, 19 Feb 2015 16:18:50 +0000 (10:18 -0600)]
MIPS: Usage and cosmetic cleanups of page table bits.
* Clean up white spaces and tabs.
* Get rid of remaining hardcoded values for calculating
shifts and masks.
* Get rid of redundant macro values.
* Do not use page table bits directly in #ifdef's.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9287/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Ralf Baechle [Thu, 19 Feb 2015 15:00:34 +0000 (16:00 +0100)]
Merge branch 'mipsr6-for-3.20' of git://git.linux-mips.org/mchandras/linux into mips-for-linux-next
James Hogan [Tue, 10 Feb 2015 10:03:00 +0000 (10:03 +0000)]
MIPS: Export MSA functions used by lose_fpu(1) for KVM
Export the _save_msa asm function used by the lose_fpu(1) macro to GPL
modules so that KVM can make use of it when it is built as a module.
This fixes the following build error when CONFIG_KVM=m and
CONFIG_CPU_HAS_MSA=y due to commit
f798217dfd03 ("KVM: MIPS: Don't leak
FPU/DSP to guest"):
ERROR: "_save_msa" [arch/mips/kvm/kvm.ko] undefined!
Fixes:
f798217dfd03 (KVM: MIPS: Don't leak FPU/DSP to guest)
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 3.15+
Patchwork: https://patchwork.linux-mips.org/patch/9261/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
James Hogan [Tue, 10 Feb 2015 10:02:59 +0000 (10:02 +0000)]
MIPS: Export FP functions used by lose_fpu(1) for KVM
Export the _save_fp asm function used by the lose_fpu(1) macro to GPL
modules so that KVM can make use of it when it is built as a module.
This fixes the following build error when CONFIG_KVM=m due to commit
f798217dfd03 ("KVM: MIPS: Don't leak FPU/DSP to guest"):
ERROR: "_save_fp" [arch/mips/kvm/kvm.ko] undefined!
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Fixes:
f798217dfd03 (KVM: MIPS: Don't leak FPU/DSP to guest)
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 3.10+
Patchwork: https://patchwork.linux-mips.org/patch/9260/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Kevin Cernekee [Thu, 25 Dec 2014 17:48:56 +0000 (09:48 -0800)]
MIPS: BCM3384: Fix outdated use of mips_cpu_intc_init()
This function was renamed to mips_cpu_irq_of_init(), so fix it to avoid
a compile error.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8834/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Petr Malat [Fri, 12 Dec 2014 14:28:01 +0000 (15:28 +0100)]
MIPS: Provide correct siginfo_t.si_stime
Provide correct siginfo_t.si_stime on MIPS64
Bug description:
MIPS version of copy_siginfo() is not aware of alignment on platforms with
64-bit long integers, which leads to an incorrect si_stime passed to signal
handlers, because the last element (si_stime) of _sifields._sigchld is not
copied. If _MIPS_SZLONG is 64, then the _sifields starts at the offset of
4 * sizeof(int).
Patch description:
Use the generic copy_siginfo, which doesn't have this problem.
Signed-off-by: Petr Malat <oss@malat.biz>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8671/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Markos Chandras [Mon, 2 Feb 2015 15:41:01 +0000 (15:41 +0000)]
MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGS
We need to check the ASEs support against the core's CFLAGS instead
of depending to the default -march option from the toolchain.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9180/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Ralf Baechle [Thu, 19 Feb 2015 12:47:20 +0000 (13:47 +0100)]
MIPS: Makefile: Pass -march option on Loongson3A cores
The loongson 3A cores do not select a suitable -march option so the build
system uses the default one from the toolchain. This may or may not be
suitable for a loongson 3A build. In order to avoid that, we explicitly set
a suitable -march option for that core. Furthermore, some very old
compilers don't support -march= at all and there is the possibility of
toolchain combinations such as GCC 4.9 and binutils 2.24 for which
-march=loongson3a will result in MIPS64 R2 code being generated but then
rejected by GAS. So treat the Longsoon 3A as an R2 CPU.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Markos Chandras [Mon, 24 Nov 2014 13:21:08 +0000 (13:21 +0000)]
MIPS: Add Malta QEMU 32R6 defconfig
Add a Malta defconfig for the 32-bit MIPS R6 core as emulated
by QEMU.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Wed, 19 Nov 2014 11:31:56 +0000 (11:31 +0000)]
MIPS: Malta: Add support for building MIPS R6 kernel
The Malta platform supports MIPS R6 (via QEMU or real bitstreams)
so add support for it.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Thu, 8 Jan 2015 09:32:25 +0000 (09:32 +0000)]
MIPS: kernel: elf: Improve the overall ABI and FPU mode checks
The previous implementation did not cover all possible FPU combinations
and it silently allowed ABI incompatible objects to be loaded with the
wrong ABI. For example, the previous logic would set the FP_64 ABI as
the matching ABI for an FP_XX object combined with an FP_64A object.
This was wrong, and the matching ABI should have been FP_64A.
The previous logic is now replaced with a new one which determines
the appropriate FPU mode to be used rather than the FP ABI. This has
the advantage that the entire logic is much simpler since it is the FPU
mode we are interested in rather than the FP ABI resulting to code
simplifications. This also removes the now obsolete FP32XX_HYBRID_FPRS
option.
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Fri, 30 Jan 2015 10:20:28 +0000 (10:20 +0000)]
MIPS: asm: fpu: Allow 64-bit FPU on MIPS32 R6
MIPS32 R6 has a 64-bit FPU so add the necessary MIPS R6
definition.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Tue, 13 Jan 2015 13:01:49 +0000 (13:01 +0000)]
MIPS: kernel: process: Do not allow FR=0 on MIPS R6
A prctl() call to set FR=0 for MIPS R6 should not be allowed
since FR=1 is the only option for R6 cores.
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Matthew Fortune <matthew.fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Thu, 15 Jan 2015 10:11:17 +0000 (10:11 +0000)]
MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as well
MIPS R2 FPU instructions are also present in MIPS R6 so amend the
preprocessor definitions to take MIPS R6 into consideration.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Wed, 3 Dec 2014 12:37:32 +0000 (12:37 +0000)]
MIPS: Make use of the ERETNC instruction on MIPS R6
The ERETNC instruction, introduced in MIPS R5, is similar to the ERET
one, except it does not clear the LLB bit in the LLADDR register.
This feature is necessary to safely emulate R2 LL/SC instructions.
However, on context switches, we need to clear the LLAddr/LLB bit
in order to make sure that an SC instruction from the new thread
will never succeed if it happens to interrupt an LL operation on the
same address from the previous thread.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Wed, 3 Dec 2014 15:47:03 +0000 (15:47 +0000)]
MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6
MIPS R6 removed quite a few R2 instructions. However, there
is plenty of <R6 userland code so we add an in-kernel emulator
so we can still be able to execute all R2 userland out there.
The emulator comes with a handy debugfs under /mips/ directory
(r2-emul-stats) to provide some basic statistics of the
instructions that are being emulated.
Below are some statistics from booting a minimal buildroot image:
Instruction Total BDslot
------------------------------
movs 236969 0
hilo 56686 0
muls 55279 0
divs 10941 0
dsps 0 0
bops 1 0
traps 0 0
fpus 0 0
loads 214981 17
stores 103364 0
llsc 56898 0
dsemul 150418 0
jr 370158
bltzl 43
bgezl 1594
bltzll 0
bgezll 0
bltzal 39
bgezal 39
beql 14503
bnel 138741
blezl 0
bgtzl 3988
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Wed, 3 Dec 2014 12:31:42 +0000 (12:31 +0000)]
MIPS: asm: mipsregs: Add support for the LLADDR register
If Config5/LLB is set in the core, then software can write the LLB
bit in the LLADDR register.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Tue, 2 Dec 2014 09:46:19 +0000 (09:46 +0000)]
MIPS: Add LLB bit and related feature for the Config 5 CP0 register
The LLBIT (bit 4) in the Config5 CP0 register indicates the software
availability of the Load-Linked bit. This bit is only set by hardware
and it has the following meaning:
0: LLB functionality is not supported
1: LLB functionality is supported. The following feature are also
supported:
- ERETNC instruction. Similar to ERET but it does not clear the LLB
bit in the LLAddr register.
- CP0 LLAddr/LLB bit must be set
- LLbit is software accessible through the LLAddr[0]
This will be used later on to emulate R2 LL/SC instructions.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Thu, 8 Jan 2015 11:55:20 +0000 (11:55 +0000)]
MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions
MIPS R6 uses the <R6 sdc2 opcode for the new BNEZC and JIALC instructions
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Thu, 27 Nov 2014 09:32:25 +0000 (09:32 +0000)]
MIPS: Emulate the new MIPS R6 BEQZC and JIC instructions
MIPS R6 uses the <R6 ldc2 opcode for the new BEQZC and JIC instructions
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Wed, 26 Nov 2014 15:43:11 +0000 (15:43 +0000)]
MIPS: Emulate the new MIPS R6 BALC instruction
MIPS R6 uses the <R6 swc2 opcode for the new BALC instructions.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Wed, 26 Nov 2014 15:03:54 +0000 (15:03 +0000)]
MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructions
MIPS R6 uses the <R6 DADDI opcode for the new BNVC, BNEC and
BNEZLAC instructions.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Wed, 26 Nov 2014 14:08:52 +0000 (14:08 +0000)]
MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructions
MIPS R6 uses the <R6 ADDI opcode for the new BOVC, BEQC and
BEQZALC instructions.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Wed, 26 Nov 2014 13:56:51 +0000 (13:56 +0000)]
MIPS: Emulate the new MIPS R6 branch compact (BC) instruction
MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Wed, 26 Nov 2014 13:05:09 +0000 (13:05 +0000)]
MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions
MIPS R6 added the following four instructions which share the
BGTZ and BGTZL opcode:
BLTZALC: Compact branch-and-link if GPR rt is < to zero
BGTZALC: Compact branch-and-link if GPR rt is > to zero
BLTZL : Compact branch if GPR rt is < to zero
BGTZL : Compact branch if GPR rt is > to zero
BLTC : Compact branch if GPR rs is less than GPR rt
BLTUC : Similar to BLTC but unsigned
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Wed, 26 Nov 2014 12:57:54 +0000 (12:57 +0000)]
MIPS: Emulate the new MIPS R6 B{L,G}Ε{Z,}{AL,}C instructions
MIPS R6 added the following four instructions which share the
BLEZ and BLEZL opcodes:
BLEZALC: Compact branch-and-link if GPR rt is <= to zero
BGEZALC: Compact branch-and-link if GPR rt is >= to zero
BLEZC : Compact branch if GPR rt is <= to zero
BGEZC : Compact branch if GPR rt is >= to zero
BGEC : Compact branch if GPR rs is less than or equal to GPR rt
BGEUC : Similar to BGEC but unsigned.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Wed, 26 Nov 2014 10:10:18 +0000 (10:10 +0000)]
MIPS: Emulate the BC1{EQ,NE}Z FPU instructions
MIPS R6 introduced the following two branch instructions for COP1:
BC1EQZ: Branch if Cop1 (FPR) Register Bit 0 is Equal to Zero
BC1NEZ: Branch if Cop1 (FPR) Register Bit 0 is Not Equal to Zero
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Tue, 25 Nov 2014 16:02:23 +0000 (16:02 +0000)]
MIPS: kernel: branch: Do not emulate the branch likelies on MIPS R6
MIPS R6 removed the BLTZL, BGEZL, BLTZAL, BGEZAL, BEQL, BNEL, BLEZL,
BGTZL branch likely instructions so we must not try to emulate them on
MIPS R6 if the R2-to-R6 emulator is not present.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Tue, 25 Nov 2014 15:54:14 +0000 (15:54 +0000)]
MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6
The MIPS R6 JR instruction is an alias to the JALR one, so it may
need emulation for non-R6 userlands.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Thu, 15 Jan 2015 10:28:29 +0000 (10:28 +0000)]
MIPS: mm: scache: Add secondary cache support for MIPS R6 cores
The secondary cache initialization and configuration code is processor
specific so we need to handle MIPS R6 cores as well.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Tue, 2 Dec 2014 15:30:19 +0000 (15:30 +0000)]
MIPS: mm: c-r4k: Set the correct ISA level
The local_r4k_flush_cache_sigtramp function uses the 'cache'
instruction inside an asm block. However, MIPS R6 changed the
opcode for the cache instruction and as a result of which we
need to set the correct ISA level.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Mon, 24 Nov 2014 15:42:46 +0000 (15:42 +0000)]
MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction
MIPS uses the cpu_has_mips_r2_exec_hazard macro to determine whether the
EHB instruction is available or not. This is necessary for MIPS R6
which also supports the EHB instruction.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Wed, 19 Nov 2014 09:39:56 +0000 (09:39 +0000)]
MIPS: mm: page: Add MIPS R6 support
The MIPS R6 pref instruction only has 9 bits for the immediate
field so skip the micro-assembler PREF instruction if the offset
does not fit in 9 bits. Moreover, bit 30 (Pref_PrepareForStore) is
no longer valid in MIPS R6, so we change the default for all MIPS R6
processors to bit 5 (Pref_StoreStreamed).
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Tue, 18 Nov 2014 09:04:34 +0000 (09:04 +0000)]
MIPS: lib: memset: Add MIPS R6 support
MIPS R6 dropped the unaligned load and store instructions so
we need to re-write this part of the code for R6 to store
one byte at a time.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Fri, 14 Nov 2014 11:55:50 +0000 (11:55 +0000)]
MIPS: lib: memcpy: Add MIPS R6 support
MIPS R6 does not support the unaligned load and store instructions
so we add a special MIPS R6 case to copy one byte at a time if we
need to read/write to unaligned memory addresses.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Thu, 15 Jan 2015 10:34:00 +0000 (10:34 +0000)]
MIPS: kernel: syscall: Set the appropriate ISA level for MIPS R6
MIPS R6 changed the opcodes for LL/SC instructions so we need to set
the appropriate ISA level.
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Tue, 28 Oct 2014 10:42:23 +0000 (10:42 +0000)]
MIPS: kernel: unaligned: Add support for the MIPS R6
The load/store unaligned instructions have been removed in MIPS R6
so we need to re-implement the related macros using the regular
load/store instructions. Moreover, the load/store from coprocessor 2
instructions have been reallocated in Release 6 so we will handle them
in the emulator instead.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Mon, 24 Nov 2014 14:40:11 +0000 (14:40 +0000)]
MIPS: kernel: cps-vec: Replace "addi" with "addiu"
The "addi" instruction will trap on overflows which is not something
we need in this code, so we replace that with "addiu".
Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00430.html
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: <stable@vger.kernel.org> # v3.15+
Cc: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Mon, 24 Nov 2014 13:17:27 +0000 (13:17 +0000)]
MIPS: kernel: genex: Set correct ISA level
The jr instruction opcode has changed in R6 so make sure
the correct ISA level is set prior using that instruction.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Tue, 25 Nov 2014 10:08:45 +0000 (10:08 +0000)]
MIPS: kernel: r4k_fpu: Add support for MIPS R6
Add the MIPS R6 related preprocessor definitions for FPU signal
related functions. MIPS R6 only has FR=1 so avoid checking that
bit on the C0/Status register.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Mon, 24 Nov 2014 11:54:19 +0000 (11:54 +0000)]
MIPS: kernel: r4k_switch: Add support for MIPS R6
Add the MIPS R6 related preprocessor definitions for save/restore
FPU related functions. We also set the appropriate ISA level
so the final return instruction "jr ra" will produce the correct
opcode on R6.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Fri, 14 Nov 2014 11:25:30 +0000 (11:25 +0000)]
MIPS: kernel: traps: Add MIPS R6 related definitions
Add MIPS R6 support to cache and ftlb exceptions, as well as
to the hwrena and ebase register configuration.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Fri, 14 Nov 2014 10:10:02 +0000 (10:10 +0000)]
MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfo
Print 'mips64r6' and/or 'mips32r6' if the kernel is running on
a MIPS R6 core.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Fri, 14 Nov 2014 10:05:41 +0000 (10:05 +0000)]
MIPS: kernel: entry.S: Add MIPS R6 related definitions
The instruction hazard barrier in the form of:
jr.hb ra
nop
is valid on MIPS R6 as well.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Thu, 13 Nov 2014 13:51:51 +0000 (13:51 +0000)]
MIPS: kernel: cpu-probe.c: Add support for MIPS R6
Add MIPS R6 support when decoding the config0 c0 register.
Also add MIPS R6 support when examining the ebase c0 register
to get the core number and when getting the shadow set number
from the srsctl c0 register.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Thu, 13 Nov 2014 13:39:39 +0000 (13:39 +0000)]
MIPS: kernel: cevt-r4k: Add MIPS R6 to the c0_compare_interrupt handler
Just like MIPS R2, in MIPS R6 it is possible to determine if a
timer interrupt has happened or not.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Mon, 24 Nov 2014 09:59:02 +0000 (09:59 +0000)]
MIPS: kernel: cpu-bugs64: Do not check R6 cores for existing 64-bit bugs
The current HW bugs checked in cpu-bugs64, do not apply to R6 cores
and they cause compilation problems due to removed <R6 instructions,
so do not check for them for the time being.
Reviewed-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Thu, 15 Jan 2015 10:31:36 +0000 (10:31 +0000)]
MIPS: asm: local: Set the appropriate ISA level for MIPS R6
MIPS R6 changed the opcodes for LL/SC instructions so we need to set
the appropriate ISA level.
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Mon, 24 Nov 2014 14:11:39 +0000 (14:11 +0000)]
MIPS: asm: spinlock: Replace "sub" instruction with "addiu"
"sub $reg, imm" is not a real MIPS instruction. The assembler can
replace that with "addi $reg, -imm". However, addi has been removed
from R6, so we replace the "sub" instruction with the "addiu" one.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Wed, 19 Nov 2014 11:09:55 +0000 (11:09 +0000)]
MIPS: asm: futex: Set the appropriate ISA level for MIPS R6
MIPS R6 changed the opcodes for LL/SC instructions so we need to set
the appropriate ISA level.
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Thu, 20 Nov 2014 13:58:30 +0000 (13:58 +0000)]
MIPS: asm: bitops: Update ISA constraints for MIPS R6 support
MIPS R6 changed the opcodes for LL/SC instructions so we need to set
the correct ISA level.
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Tue, 6 Jan 2015 11:09:24 +0000 (11:09 +0000)]
MIPS: asm: atomic: Update ISA constraints for MIPS R6 support
MIPS R6 changed the opcodes for LL/SC instructions so we need to
set the correct ISA level.
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Thu, 20 Nov 2014 13:31:48 +0000 (13:31 +0000)]
MIPS: asm: cmpxchg: Update ISA constraints for MIPS R6 support
MIPS R6 changed the opcodes for LL/SC instructions so we need to set
the correct ISA.
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Fri, 19 Dec 2014 12:04:46 +0000 (12:04 +0000)]
MIPS: Use the new "ZC" constraint for MIPS R6
GCC versions supporting MIPS R6 use the ZC constraint to enforce a
9-bit offset for MIPS R6. We will use that for all MIPS R6 LL/SC
instructions.
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Mon, 26 Jan 2015 12:44:11 +0000 (12:44 +0000)]
MIPS: asm: Rename GCC_OFF12_ASM to GCC_OFF_SMALL_ASM
The GCC_OFF12_ASM macro is used for 12-bit immediate constrains
but we will also use it for 9-bit constrains on MIPS R6 so we
rename it to something more appropriate.
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Thu, 13 Nov 2014 13:32:03 +0000 (13:32 +0000)]
MIPS: asm: spram: Add new symbol for MIPS scratch pad storage
MIPS R6, just like MIPS R2, have scratch pad storage, so add a new
symbol which is selected by MIPS R2 and R6.
Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00389.html
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Thu, 13 Nov 2014 13:25:51 +0000 (13:25 +0000)]
MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions
MIPS R6 changed the 'cache' instruction opcode and reduced the
offset field to 8 bits. This means we now have to adjust the
base register every 256 bytes and as a result of which we can
no longer use the previous cache functions.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Thu, 13 Nov 2014 11:54:31 +0000 (11:54 +0000)]
MIPS: asm: irqflags: Add MIPS R6 related definitions
Add the MIPS R6 related definitions to the IRQ related macros
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Thu, 13 Nov 2014 11:52:22 +0000 (11:52 +0000)]
MIPS: asm: hazards: Add MIPSR6 definitions
Add the MIPSR6 related definitions to MIPS hazards
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Thu, 13 Nov 2014 11:49:21 +0000 (11:49 +0000)]
MIPS: asm: cpu: Add MIPSR6 ISA definitions
Add MIPS R6 to the ISA definitions
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Thu, 13 Nov 2014 11:25:27 +0000 (11:25 +0000)]
MIPS: Use generic checksum functions for MIPS R6
The following instructions have been removed from MIPS R6
ulw, ulh, swl, lwr, lwl, swr.
However, all of them are used in the MIPS specific checksum implementation.
As a result of which, we will use the generic checksum on MIPS R6
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Wed, 5 Nov 2014 14:17:52 +0000 (14:17 +0000)]
MIPS: asm: asmmacro: Replace "add" instructions with "addu"
The "add" instruction is actually a macro in binutils and depending on
the size of the immediate it can expand to an "addi" instruction.
However, the "addi" instruction traps on overflows which is not
something we want on address calculation.
Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00121.html
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: <stable@vger.kernel.org> # v3.15+
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Wed, 5 Nov 2014 12:56:40 +0000 (12:56 +0000)]
MIPS: asm: asmmacro: Add MIPS R6 support to the simple EI/DI variants
EI/DI instructions are available in MIPS R6 so add the needed
definitions.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Mon, 27 Oct 2014 11:37:47 +0000 (11:37 +0000)]
MIPS: asm: stackframe: Do not preserve the HI/LO registers on MIPS R6
The HI/LO registers have been removed from MIPS R6. Instructions
such as MULT and DIV have been replaced with a new pair of
instructions for the HI/LO operations for example:
MULT -> MUL, MUH
DIV -> DIV, MOD
So we avoid preserving the pre-R6 HI/LO registers in MIPS R6
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Mon, 27 Oct 2014 11:23:34 +0000 (11:23 +0000)]
MIPS: asm: module: define MODULE_PROC_FAMILY for MIPS R6
Define the MODULE_PROC_FAMILY for the MIPS R6 ISA.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Tue, 18 Nov 2014 15:02:32 +0000 (15:02 +0000)]
MIPS: asm: compiler: Add new macros to set ISA and arch asm annotations
There are certain places where the code uses .set mips32 or .set mips64
or .set arch=r4000. In preparation of MIPS R6 support, and in order to
use as less #ifdefs as possible, we define new macros to set similar
annotations for MIPS R6.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Wed, 19 Nov 2014 09:29:42 +0000 (09:29 +0000)]
MIPS: mm: Add MIPS R6 instruction encodings
MIPS R6 defines new opcodes for ll, sc, cache and pref instructions
so we need to take these into consideration in the micro-assembler.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Tue, 18 Nov 2014 16:24:15 +0000 (16:24 +0000)]
MIPS: mm: uasm: Add signed 9-bit immediate related macros
MIPS R6 redefines several instructions and reduces the immediate
field to 9-bits so add related macros for the microassembler.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Mon, 27 Oct 2014 10:34:11 +0000 (10:34 +0000)]
MIPS: Add build support for the MIPS R6 ISA
Add build support for the latest revision (R6) of the MIPS ISA.
microMIPS is not yet supported.
Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00386.html
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Mon, 24 Nov 2014 12:59:44 +0000 (12:59 +0000)]
MIPS: Add MIPS generic QEMU probe support
Add a case in cpu_probe_mips for the MIPS generic QEMU processor ID.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Mon, 24 Nov 2014 12:59:01 +0000 (12:59 +0000)]
MIPS: Add cases for CPU_QEMU_GENERIC
Add a CPU_QEMU_GENERIC case to various switch statements.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Mon, 27 Oct 2014 10:12:23 +0000 (10:12 +0000)]
MIPS: Add generic QEMU PRid and cpu type identifiers
Latest versions of QEMU added support for mips32r6-generic and
mips64r6-generic cpu types so add related definitions in preparation
of MIPS R6 support. This is also used for QEMU R2 generic cpus.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Mon, 26 Jan 2015 13:04:33 +0000 (13:04 +0000)]
MIPS: HTW: Prevent accidental HTW start due to nested htw_{start, stop}
activate_mm() and switch_mm() call get_new_mmu_context() which in turn
can enable the HTW before the entryhi is changed with the new ASID.
Since the latter will enable the HTW in local_flush_tlb_all(),
then there is a small timing window where the HTW is running with the
new ASID but with an old pgd since the TLBMISS_HANDLER_SETUP_PGD
hasn't assigned a new one yet. In order to prevent that, we introduce a
simple htw counter to avoid starting HTW accidentally due to nested
htw_{start,stop}() sequences. Moreover, since various IPI calls can
enforce TLB flushing operations on a different core, such an operation
may interrupt another htw_{stop,start} in progress leading inconsistent
updates of the htw_seq variable. In order to avoid that, we disable the
interrupts whenever we update that variable.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # 3.17+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9118/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Markos Chandras [Mon, 2 Feb 2015 15:41:01 +0000 (15:41 +0000)]
MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGS
We need to check the ASEs support against the core's CFLAGS instead
of depending to the default -march option from the toolchain.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9180/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Markos Chandras [Mon, 26 Jan 2015 09:40:36 +0000 (09:40 +0000)]
MIPS: asm: pgtable: Prevent HTW race when updating PTEs
Whenever we modify a page table entry, we need to ensure that the HTW
will not fetch a stable entry. And for that to happen we need to ensure
that HTW is stopped before we modify the said entry otherwise the HTW
may already be in the process of reading that entry and fetching the
old information. As a result of which, we replace the htw_reset() calls
with htw_{stop,start} in more appropriate places. This also removes the
remaining users of htw_reset() and as a result we drop that macro
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # 3.17+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9116/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Markos Chandras [Mon, 26 Jan 2015 09:40:34 +0000 (09:40 +0000)]
MIPS: asm: pgtable: Add c0 hazards on HTW start/stop sequences
When we use htw_{start,stop}() outside of htw_reset(), we need
to ensure that c0 changes have been propagated properly before
we attempt to continue with subsequence memory operations.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # 3.17+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9114/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Markos Chandras [Wed, 21 Jan 2015 10:54:46 +0000 (10:54 +0000)]
MIPS: mm: Add debug information for userland SIGSEGV signals.
Commit
41c594ab65fc ("[MIPS] MT: Improved multithreading support.")
removed useful debug information for userland segmentation faults.
This patch bring this back along with the ability to determine the
name of the object file where the EPC and RA registers point at.
Furthermore, we select the SYSCTL_EXCEPTION_TRACE symbol for MIPS
which is the de facto solution to turn userland exception logging
on and off via the /proc/sys/debug/exception-trace file.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9089/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Thu, 8 Jan 2015 12:17:37 +0000 (12:17 +0000)]
MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS
Userland code may be built using an ABI which permits linking to objects
that have more restrictive floating point requirements. For example,
userland code may be built to target the O32 FPXX ABI. Such code may be
linked with other FPXX code, or code built for either one of the more
restrictive FP32 or FP64. When linking with more restrictive code, the
overall requirement of the process becomes that of the more restrictive
code. The kernel has no way to know in advance which mode the process
will need to be executed in, and indeed it may need to change during
execution. The dynamic loader is the only code which will know the
overall required mode, and so it needs to have a means to instruct the
kernel to switch the FP mode of the process.
This patch introduces 2 new options to the prctl syscall which provide
such a capability. The FP mode of the process is represented as a
simple bitmask combining a number of mode bits mirroring those present
in the hardware. Userland can either retrieve the current FP mode of
the process:
mode = prctl(PR_GET_FP_MODE);
or modify the current FP mode of the process:
err = prctl(PR_SET_FP_MODE, new_mode);
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Matthew Fortune <matthew.fortune@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8899/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
James Hogan [Mon, 19 Jan 2015 12:00:55 +0000 (12:00 +0000)]
MIPS: cevt-r4k: Drop GIC special case
The cevt-r4k driver used to call into the GIC driver to find whether the
timer was pending, but only with External Interrupt Controller (EIC)
mode, where the Cause.IP bits can't be used as they encode the interrupt
priority level (Cause.RIPL) instead.
However commit
e9de688dac65 ("irqchip: mips-gic: Support local
interrupts") changed the condition from cpu_has_veic to gic_present.
This fails on cores such as P5600 which have a GIC but the local
interrupts aren't routable by the GIC, causing c0_compare_int_usable()
to consider the interrupt unusable so r4k_clockevent_init() fails.
The previous behaviour, added in commit
98b67c37db33 ("MIPS: Add EIC
support for GIC."), wasn't really correct either as far as I can tell,
since P5600 apparently supports EIC mode too, and in any case the use of
Cause.TI with r2 should have been sufficient anyway since commit
010c108d7af7 ("MIPS: PowerTV: Fix support for timer interrupts with > 64
external IRQs").
Therefore drop the call into the gic driver altogether, and add a
comment in c0_compare_int_pending() to clarify that Cause.TI does get
checked since MIPS r2.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Fixes:
e9de688dac65 ("irqchip: mips-gic: Support local interrupts")
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Steven J. Hill <steven.hill@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9077/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Ralf Baechle [Wed, 4 Feb 2015 12:04:03 +0000 (13:04 +0100)]
MIPS: elf2ecoff: Fix warning due to dead code.
HOSTCC arch/mips/boot/elf2ecoff
arch/mips/boot/elf2ecoff.c: In function ‘main’:
arch/mips/boot/elf2ecoff.c:271:8: warning: variable ‘shstrtab’ set but not used [-Wunused-but-set-variable]
char *shstrtab;
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>