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Tony Tye [Fri, 23 Mar 2018 18:58:47 +0000 (18:58 +0000)]
[AMDGPU] Update OpenCL to use 48 bytes of implicit arguments for AMDGPU
Add two additional implicit arguments for OpenCL for the AMDGPU target using the AMDHSA runtime to support device enqueue.
Differential Revision: https://reviews.llvm.org/D44697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328351
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Tony Tye [Fri, 23 Mar 2018 18:45:18 +0000 (18:45 +0000)]
[AMDGPU] Remove use of OpenCL triple environment and replace with function attribute for AMDGPU
- Remove use of the opencl and amdopencl environment member of the target triple for the AMDGPU target.
- Use function attribute to communicate to the AMDGPU backend to add implicit arguments for OpenCL kernels for the AMDHSA OS.
Differential Revision: https://reviews.llvm.org/D43736
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328349
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Zachary Turner [Fri, 23 Mar 2018 18:43:39 +0000 (18:43 +0000)]
[PDB] Make our PDBs look more like MS PDBs.
When investigating bugs in PDB generation, the first step is
often to do the same link with link.exe and then compare PDBs.
But comparing PDBs is hard because two completely different byte
sequences can both be correct, so it hampers the investigation when
you also have to spend time figuring out not just which bytes are
different, but also if the difference is meaningful.
This patch fixes a couple of cases related to string table emission,
hash table emission, and the order in which we emit strings that
makes more of our bytes the same as the bytes generated by MS PDBs.
Differential Revision: https://reviews.llvm.org/D44810
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328348
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Krzysztof Parzyszek [Fri, 23 Mar 2018 18:43:09 +0000 (18:43 +0000)]
[Hexagon] Always generate mux out of predicated transfers if possible
HexagonGenMux would collapse pairs of predicated transfers if it assumed
that the predicated .new forms cannot be created. Turns out that generating
mux is preferable in almost all cases.
Introduce an option -hexagon-gen-mux-threshold that controls the minimum
distance between the instruction defining the predicate and the later of
the two transfers. If the distance is closer than the threshold, mux will
not be generated. Set the threshold to 0 by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328346
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Jordan Rose [Fri, 23 Mar 2018 18:05:19 +0000 (18:05 +0000)]
Delete the copy constructor for llvm::yaml::Node
The nodes keep a reference back to the original document, but the
document is streamed, not read all into memory at once, and the
position is part of the state. If nodes are ever copied, the document
position can end up being advanced more than once.
This did not reveal any problems in LLVM or Clang but caught a handful
over in Swift!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328345
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Krzysztof Parzyszek [Fri, 23 Mar 2018 18:00:18 +0000 (18:00 +0000)]
[Hexagon] Avoid early if-conversion for one sided branches
Patch by Anand Kodnani.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328344
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Simon Pilgrim [Fri, 23 Mar 2018 17:59:22 +0000 (17:59 +0000)]
[X86][Btver2] Cleanup TEST instructions to use JFPA (+JFPX on ymms) function unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328343
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Alex Shlyapnikov [Fri, 23 Mar 2018 17:57:54 +0000 (17:57 +0000)]
[HWASan] Port HWASan to Linux x86-64 (LLVM)
Summary:
Porting HWASan to Linux x86-64, first of the three patches, LLVM part.
The approach is similar to ARM case, trap signal is used to communicate
memory tag check failure. int3 instruction is used to generate a signal,
access parameters are stored in nop [eax + offset] instruction immediately
following the int3 one.
One notable difference is that x86-64 has to untag the pointer before use
due to the lack of feature comparable to ARM's TBI (Top Byte Ignore).
Reviewers: eugenis
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D44699
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328342
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Ana Pazos [Fri, 23 Mar 2018 17:53:27 +0000 (17:53 +0000)]
[ARM] Fix "Constant pool entry out of range!" in Thumb1 mode
This patch fixes PR36658, "Constant pool entry out of range!" in Thumb1 mode.
In ARMConstantIslands::optimizeThumb2JumpTables() in Thumb1 mode,
adjustBBOffsetsAfter() is not calculating postOffset correctly by
properly accounting for the padding that is required for the constant pool
that immediately follows the jump table branch instruction.
Reviewers: t.p.northover, eli.friedman
Reviewed By: t.p.northover
Subscribers: chrib, tstellar, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D44709
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328341
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Andrea Di Biagio [Fri, 23 Mar 2018 17:53:02 +0000 (17:53 +0000)]
[llvm-mca] update the ResourcePressureView after r328335. NFC.
This should have been part of r328335. I forgot to svn add these files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328340
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Krzysztof Parzyszek [Fri, 23 Mar 2018 17:46:09 +0000 (17:46 +0000)]
[Hexagon] Two fixes in early if-conversion
- Fix checking for vector predicate registers.
- Avoid speculating llvm.lifetime.end intrinsic.
Patch by Harsha Jagasia and Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328339
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Simon Pilgrim [Fri, 23 Mar 2018 17:38:59 +0000 (17:38 +0000)]
[X86][Btver2] Cleanup MOVMSK instructions to use JFPA function unit
Add missing non-VEX and (V)PMOVMSKB instructions to the pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328338
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Andrew Kaylor [Fri, 23 Mar 2018 17:36:18 +0000 (17:36 +0000)]
Fix a block copying problem in LICM
Differential Revision: https://reviews.llvm.org/D44817
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328336
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Andrea Di Biagio [Fri, 23 Mar 2018 17:36:07 +0000 (17:36 +0000)]
[llvm-mca] Make the resource cost a double.
This is done in preparation for the fix for PR36874.
The number of cycles consumed for each pipe is now a double quantity. This
allows reuse of the resource pressure view to print out instruction tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328335
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Fangrui Song [Fri, 23 Mar 2018 17:26:12 +0000 (17:26 +0000)]
[ADT] Simplify getMemory. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328334
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Krzysztof Parzyszek [Fri, 23 Mar 2018 17:22:55 +0000 (17:22 +0000)]
[Hexagon] Copy subregisters in HexagonStoreWiden
When converting an instruction to the wider version, copy any
subregisters if the original operand has a subregister.
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328333
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Simon Pilgrim [Fri, 23 Mar 2018 16:17:56 +0000 (16:17 +0000)]
[X86][Btver2] Vector permutes use a JFPU01 scheduler pipe and JFPX/JVALU function unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328331
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Sanjay Patel [Fri, 23 Mar 2018 15:39:03 +0000 (15:39 +0000)]
[InstCombine] auto-generate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328329
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Simon Pilgrim [Fri, 23 Mar 2018 15:35:13 +0000 (15:35 +0000)]
[X86][Btver2] Vector store instructions use a JFPU1 scheduler pipe and JSAGU/JSTC function units
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328328
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Sanjay Patel [Fri, 23 Mar 2018 15:31:31 +0000 (15:31 +0000)]
[InstSimplify] regenerate checks, move tests; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328327
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Zaara Syeda [Fri, 23 Mar 2018 15:28:15 +0000 (15:28 +0000)]
Re-commit: [MachineLICM] Add functions to MachineLICM to hoist invariant stores
This patch adds functions to allow MachineLICM to hoist invariant stores.
Currently, MachineLICM does not hoist any store instructions, however
when storing the same value to a constant spot on the stack, the store
instruction should be considered invariant and be hoisted. The function
isInvariantStore iterates each operand of the store instruction and checks
that each register operand satisfies isCallerPreservedPhysReg. The store
may be fed by a copy, which is hoisted by isCopyFeedingInvariantStore.
This patch also adds the PowerPC changes needed to consider the stack
register as caller preserved.
Differential Revision: https://reviews.llvm.org/D40196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328326
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Sanjay Patel [Fri, 23 Mar 2018 15:19:35 +0000 (15:19 +0000)]
[InstCombine] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328325
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Simon Pilgrim [Fri, 23 Mar 2018 15:17:50 +0000 (15:17 +0000)]
[X86][Btver2] Cleanup DPPS/DPPD instructions to use JFPA/JFPM function units
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328324
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Sanjay Patel [Fri, 23 Mar 2018 15:07:35 +0000 (15:07 +0000)]
[InstCombine] reduce code duplication; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328323
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Sanjay Patel [Fri, 23 Mar 2018 14:48:31 +0000 (14:48 +0000)]
[InstCombine] improve variable name; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328322
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John Brawn [Fri, 23 Mar 2018 14:47:07 +0000 (14:47 +0000)]
[AArch64] Don't reduce the width of loads if it prevents combining a shift
Loads and stores can only shift the offset register by the size of the value
being loaded, but currently the DAGCombiner will reduce the width of the load
if it's followed by a trunc making it impossible to later combine the shift.
Solve this by implementing shouldReduceLoadWidth for the AArch64 backend and
make it prevent the width reduction if this is what would happen, though do
allow it if reducing the load width will let us eliminate a later sign or zero
extend.
Differential Revision: https://reviews.llvm.org/D44794
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328321
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Simon Pilgrim [Fri, 23 Mar 2018 14:45:03 +0000 (14:45 +0000)]
[X86][Btver2] Fix MicroOps counts for DPPS/YMM memory folded instructions
This was due to a misunderstanding over what llvm calls a micro-op (retirement unit) is actually called a macro-op on the AMD/Jaguar target. Folded loads don't affect num macro ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328320
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Simon Pilgrim [Fri, 23 Mar 2018 14:27:26 +0000 (14:27 +0000)]
[X86][Btver2] Cleanup SSE42 PCMPISTR/PCMPESTR string instructions to correctly use JFPU1 scheduler pipe followed by JLAGU/JSAGU/JFPA/JVALU function units
Fixes throughput to match Agner/Fam16h-SoG as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328318
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Daniel Neilson [Fri, 23 Mar 2018 14:25:35 +0000 (14:25 +0000)]
Remove the deprecated single-alignment IRBuilder API for memcpy/memmove (NFC)
Summary:
This change is part of step six in the series of changes to remove the alignment
argument from memcpy/memmove/memset in favour of alignment attributes. At this
point all users of the IRBuilder APIs for creating a memcpy/memmove call given
a single value for alignment have been updated. We want to discourage usage of
these old APIs in favour of the newer ones that allow for separate source and
destination alignments, so this patch deletes the old API.
Specifically, we remove from IRBuilder:
CallInst *CreateMemCpy(Value *Dst, Value *Src, uint64_t Size, unsigned Align,
bool isVolatile = false, MDNode *TBAATag = nullptr,
MDNode *TBAAStructTag = nullptr,
MDNode *ScopeTag = nullptr,
MDNode *NoAliasTag = nullptr)
CallInst *CreateMemCpy(Value *Dst, Value *Src, Value *Size, unsigned Align,
bool isVolatile = false, MDNode *TBAATag = nullptr,
MDNode *TBAAStructTag = nullptr,
MDNode *ScopeTag = nullptr,
MDNode *NoAliasTag = nullptr)
CallInst *CreateMemMove(Value *Dst, Value *Src, uint64_t Size, unsigned Align,
bool isVolatile = false, MDNode *TBAATag = nullptr,
MDNode *ScopeTag = nullptr,
MDNode *NoAliasTag = nullptr)
CallInst *CreateMemMove(Value *Dst, Value *Src, Value *Size, unsigned Align,
bool isVolatile = false, MDNode *TBAATag = nullptr,
MDNode *ScopeTag = nullptr,
MDNode *NoAliasTag = nullptr)
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654, rL324773, rL324774,
rL324781, rL324784, rL324955, rL324960, rL325816, rL327398, rL327421, rL328097 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328317
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Matthew Simpson [Fri, 23 Mar 2018 14:18:27 +0000 (14:18 +0000)]
[SLP] Stop counting cost of gather sequences with multiple uses
When building the SLP tree, we look for reuse among the vectorized tree
entries. However, each gather sequence is represented by a unique tree entry,
even though the sequence may be identical to another one. This means, for
example, that a gather sequence with two uses will be counted twice when
computing the cost of the tree. We should only count the cost of the definition
of a gather sequence rather than its uses. During code generation, the
redundant gather sequences are emitted, but we optimize them away with CSE. So
it looks like this problem just affects the cost model.
Differential Revision: https://reviews.llvm.org/D44742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328316
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Daniel Neilson [Fri, 23 Mar 2018 14:02:54 +0000 (14:02 +0000)]
Remove deprecated MemIntrinsic methods (NFC)
Summary:
This change is part of step six in the series of changes to remove
the alignment argument from memcpy/memmove/memset in favour of
alignment attributes. At this point all uses of
MemIntrinsicInst::[get|set]Alignment() have been updated, so we now
remove these methods entirely to discourage their use.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654, rL324773, rL324774,
rL324781, rL324784, rL324955, rL324960, rL325816, rL327398, rL327421, rL328097 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328315
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Alexey Bataev [Fri, 23 Mar 2018 13:35:54 +0000 (13:35 +0000)]
[DEBUGINFO] Add flag for DWARF2 to use sections as references.
Summary:
Some targets does not support labels inside debug sections, but support
references in form `section+offset`. Patch adds initial support
for this.
Reviewers: echristo, probinson, jlebar
Subscribers: llvm-commits, JDevlieghere
Differential Revision: https://reviews.llvm.org/D43943
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328314
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Christof Douma [Fri, 23 Mar 2018 13:02:03 +0000 (13:02 +0000)]
[ARM] Support float literals under XO
When targeting execute-only and fp-armv8, float constants in a compare
resulted in instruction selection failures. This is now fixed by using
vmov.f32 where possible, otherwise the floating point constant is
lowered into a integer constant that is moved into a floating point
register.
This patch also restores using fpcmp with immediate 0 under fp-armv8.
Change-Id: Ie87229706f4ed879a0c0cf66631b6047ed6c6443
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328313
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Florian Hahn [Fri, 23 Mar 2018 12:49:39 +0000 (12:49 +0000)]
Revert r328307: [IPSCCP] Use constant range information for comparisons of parameters.
Reverted for now, due to it causing verifier failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328312
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Amara Emerson [Fri, 23 Mar 2018 12:48:57 +0000 (12:48 +0000)]
[GlobalISel] Fix legalizer combine to not use illegal input G_EXTRACT.
This was being masked because GISel is enabled by default for -O0 and
the abort was disabled. Modified test to explicitly enable abort.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328311
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Matthew Simpson [Fri, 23 Mar 2018 12:47:54 +0000 (12:47 +0000)]
[test] Allow for optional No-Op Barrier Pass in O0 pipeline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328310
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Simon Pilgrim [Fri, 23 Mar 2018 12:08:23 +0000 (12:08 +0000)]
[X86][Znver1] Fix instregex entries that don't match any instructions (D44687)
Reviewed by @GGanesh and @craig.topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328309
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Simon Pilgrim [Fri, 23 Mar 2018 11:56:38 +0000 (11:56 +0000)]
[X86][SandyBridge] Fix missing comma that was causing string concatenation of 2 instregex entries
Found while updating D44687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328308
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Florian Hahn [Fri, 23 Mar 2018 11:56:00 +0000 (11:56 +0000)]
[IPSCCP] Use constant range information for comparisons of parameters.
For comparisons with parameters, we can use the ParamState lattice
elements which also provide constant range information. This improves
the code for PR33253 further and gets us closer to use
ValueLatticeElement for all values.
Also, as we are using the range information in the solver directly, we
do not need tryToReplaceWithConstantRange afterwards anymore.
Reviewers: dberlin, mssimpso, davide, efriedma
Reviewed By: mssimpso
Differential Revision: https://reviews.llvm.org/D43762
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328307
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Andrea Di Biagio [Fri, 23 Mar 2018 11:50:43 +0000 (11:50 +0000)]
[llvm-mca] Pass the InstrBuilder to the constructor of Backend.
This is done in preparation for the fix for PR36784.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328306
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Andrea Di Biagio [Fri, 23 Mar 2018 11:33:09 +0000 (11:33 +0000)]
[llvm-mca] Add flag -resource-pressure to enable/disable printing of the resource pressure view.
By default, the tool always enables the resource pressure view.
This flag lets user specify whether they want to add that view or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328305
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Simon Pilgrim [Fri, 23 Mar 2018 11:27:31 +0000 (11:27 +0000)]
[X86][Btver2] Vector move/load/store instructions use a JFPU01 scheduler pipe and JFPX/JVALU function unit as well as the AGUs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328304
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Florian Hahn [Fri, 23 Mar 2018 11:00:42 +0000 (11:00 +0000)]
[AArch64] Clean-up a few over-eager regexps in models.
Patch by Simon Pilgrim <llvm-dev@redking.me.uk>
That is a slightly modified version of the AArch64 changes from
Simon's D44687 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328303
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Florian Hahn [Fri, 23 Mar 2018 10:38:12 +0000 (10:38 +0000)]
[LoopUnroll] Simplify induction variables after peeling too.
Loop peeling also has an impact on the induction variables, so we should
benefit from induction variable simplification after peeling too.
Reviewers: sanjoy, bogner, mzolotukhin, efriedma
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D43878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328301
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Benjamin Kramer [Fri, 23 Mar 2018 10:14:19 +0000 (10:14 +0000)]
[ORC] Join materialization thread in unit test
There's are race between this thread and the destructor of the test ORC
components on the main threads. I saw flaky failures there in about 4%
of the runs of this unit test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328300
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Martin Storsjo [Fri, 23 Mar 2018 09:10:03 +0000 (09:10 +0000)]
[ARM] Error out on .arm assembler directives on windows
Windows on arm is thumb only.
Differential Revision: https://reviews.llvm.org/D43005
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328298
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Martin Storsjo [Fri, 23 Mar 2018 08:36:47 +0000 (08:36 +0000)]
Revert "[DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst))"
This reverts commit r328252. This change broke building a number
of projects when targeting ARM and AArch64, see PR36873.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328297
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Craig Topper [Fri, 23 Mar 2018 06:58:55 +0000 (06:58 +0000)]
[X86] Give VPCMPEQQ the same itinerary as its SSE counterpart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328296
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Craig Topper [Fri, 23 Mar 2018 06:41:43 +0000 (06:41 +0000)]
[X86] Correct the latencies of SNB integer vector multiplies based on Agner's data. Add missing MMX multiplies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328295
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Craig Topper [Fri, 23 Mar 2018 06:41:41 +0000 (06:41 +0000)]
[X86] Match vpblendvb/vblendvps/vblendvpd itineraries to the SSE equivalent. Change pblendvb/blendvps/blendvpd to use WriteFVarBlend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328294
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Craig Topper [Fri, 23 Mar 2018 06:41:40 +0000 (06:41 +0000)]
[X86] Change VPSADBW itinerary to SSE_INTALU_ITINS_P to match the SSE version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328293
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Craig Topper [Fri, 23 Mar 2018 06:41:39 +0000 (06:41 +0000)]
[X86] Give VLDDQUrm and LDDQUrm the same itinerary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328292
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Craig Topper [Fri, 23 Mar 2018 06:41:38 +0000 (06:41 +0000)]
[X86] Merge VMOVMSKBrr and MOVMSKBrr in the SNB sheduler model.
The VMOVMSKBrr was in a separate InstRW with a lower latency, but I assume they should be the same and the higher latency matches Agners table so I'm going with that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328291
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Craig Topper [Fri, 23 Mar 2018 06:41:36 +0000 (06:41 +0000)]
[X86] Add VEXTRB/W/D/Q to Zen scheduler model.
The SSE versions were present, but not the VEX version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328290
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 23 Mar 2018 06:41:35 +0000 (06:41 +0000)]
[X86] Fix the itinerary for vextractps to match extractps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328289
91177308-0d34-0410-b5e6-
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Nirav Dave [Fri, 23 Mar 2018 01:22:39 +0000 (01:22 +0000)]
[DAG] Fix node id invalidation in Instruction Selection.
Invalidation should be bit negation. Add missing negation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328287
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 23 Mar 2018 00:02:45 +0000 (00:02 +0000)]
[TableGen] Don't capture returned std::vectors by const reference.
The full vector is being returned not a reference. So the reference was just a to a temporary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328275
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Kevin Enderby [Thu, 22 Mar 2018 23:59:35 +0000 (23:59 +0000)]
For llvm-nm and Mach-O files also use function starts info in some
cases when printing symbols. As an improvement to:
r305733 - Change llvm-nm for Mach-O files to use dyld info in some cases when printing symbols
it could be made a bit better if it also read the function starts and faked
up nlist entries to those address not already faked up by the other
dyld info. This would help with stripped static functions.
rdar://
38761029
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328274
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Michael Zolotukhin [Thu, 22 Mar 2018 23:44:40 +0000 (23:44 +0000)]
State that CFG is preserved in 'Falkor HW Prefetch Fix Late Phase'.
That removes some redundant recomputations from the passes pipeline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328272
91177308-0d34-0410-b5e6-
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Fangrui Song [Thu, 22 Mar 2018 23:40:02 +0000 (23:40 +0000)]
[Support/Parallel] Use lock_guard which has less overhead than unique_lock.
Summary: unique_lock has the overhead of tracking ownership status and the owner.
Reviewers: grimar, zturner
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44698
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328271
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Michael Zolotukhin [Thu, 22 Mar 2018 23:02:48 +0000 (23:02 +0000)]
Reapply "[test] Add tests for llc passes pipelines." with a fix for bots with expensive checks on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328267
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David Blaikie [Thu, 22 Mar 2018 22:42:44 +0000 (22:42 +0000)]
Move SampleProfile.h into IPO along with the rest of the IPO pass headers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328262
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 22 Mar 2018 22:17:11 +0000 (22:17 +0000)]
[X86] Correct the VROUND regular expressions in Znver1 scheduler model to account for r328254
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328260
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David Blaikie [Thu, 22 Mar 2018 22:07:53 +0000 (22:07 +0000)]
Finish moving the IPSCCP pass from Scalar to IPO - moving the registration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328259
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Evgeny Stupachenko [Thu, 22 Mar 2018 22:04:39 +0000 (22:04 +0000)]
Revert r325687 (workaround for PR36032).
Summary:
Revert r325687 workaround for PR36032 since
a fix was committed in r326154.
Reviewers: sbaranga
Differential Revision: http://reviews.llvm.org/D44768
From: Evgeny Stupachenko <evstupac@gmail.com>
<evgeny.v.stupachenko@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328257
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Rafael Espindola [Thu, 22 Mar 2018 22:04:32 +0000 (22:04 +0000)]
Add test for demangling GNU ABI tags.
Patch by Christopher James Halse Rogers!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328256
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Craig Topper [Thu, 22 Mar 2018 21:55:20 +0000 (21:55 +0000)]
[X86] Rename VROUNDYPS* and VROUNDYPD* instructions to VROUNDPSY* and VROUNDPDY*. Fix itinerary mistake on all memory forms of VROUNDPD
This makes the Y position consistent with other instructions.
This should have been NFC, but while refactoring the multiclass I noticed that VROUNDPD memory forms were using the register itinerary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328254
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Guozhi Wei [Thu, 22 Mar 2018 21:47:25 +0000 (21:47 +0000)]
[DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst))
In our real world application, we found the following optimization is missed in DAGCombiner
(zext (and/or/xor (shl/shr (load x), cst), cst)) -> (and/or/xor (shl/shr (zextload x), (zext cst)), (zext cst))
If the user of original zext is an add, it may enable further lea optimization on x86.
This patch add a new function CombineZExtLogicopShiftLoad to do this optimization.
Differential Revision: https://reviews.llvm.org/D44402
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328252
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David Blaikie [Thu, 22 Mar 2018 21:41:29 +0000 (21:41 +0000)]
Fix layering between SCCP and IPO SCCP
Transforms/Scalar/SCCP.cpp implemented both the Scalar and IPO SCCP, but
this meant Transforms/Scalar including Transfroms/IPO headers, creating
a circular dependency. (IPO depends on Scalar already) - so move the IPO
SCCP shims out into IPO and the basic library implementation accessible
from Scalar/SCCP.h to be used from the IPO/SCCP.cpp implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328250
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Roman Tereshin [Thu, 22 Mar 2018 21:29:07 +0000 (21:29 +0000)]
[MIR] Making MIR Printing, opt -dot-cfg, and -debug printing faster
Value::printAsOperand has been scanning the entire module just to
print a single value as an operand, regardless being asked to print a
type or not at all, and regardless really needing to scan the module
to print a type.
It made some of the users of the method exceptionally slow on large
IR-modules (or large MIR-files with large IR-modules embedded).
This patch defers scanning a module looking for struct types, mostly
numbered struct types, as much as possible, speeding up those users
w/o changing any APIs at all.
See speedup examples below:
Release Build:
# 83 seconds -> 5.5 seconds
time ./bin/llc -start-before=irtranslator -stop-after=irtranslator \
-global-isel -global-isel-abort=2 -simplify-mir sqlite3.O0.ll -o \
sqlite3.O0.ll.regbankselected.mir
# 133 seconds -> 6.2 seconds
time ./bin/opt sqlite3.O0.ll -dot-cfg -disable-output
Release + Asserts Build:
# 95 seconds -> 5.5 seconds
time ./bin/llc -start-before=irtranslator -stop-after=irtranslator \
-global-isel -global-isel-abort=2 -simplify-mir sqlite3.O0.ll -o \
sqlite3.O0.ll.regbankselected.mir
# 146 seconds -> 6.2 seconds
time ./bin/opt sqlite3.O0.ll -dot-cfg -disable-output
# 1096 seconds -> 553 seconds
time ./bin/llc -debug-only=isel -fast-isel=false -stop-after=isel \
sqlite3.O0.ll -o /dev/null 2> err
where sqlite3.O0.ll is non-optimized IR produced from
sqlite-amalgamation (http://sqlite.org/download.html), which is entire
SQLite3 implementation in a single C-file.
Benchmarked on 4-cores / 8 threads PCI-E SSD iMac running macOS
Reviewers: dexonsmith, bkramer, void, chandlerc, aditya_nandakumar, dsanders, qcolombet,
Reviewed By: bogner
Subscribers: thegameg, llvm-commits
Differential Revision: https://reviews.llvm.org/D44132
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328246
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Mircea Trofin [Thu, 22 Mar 2018 21:26:52 +0000 (21:26 +0000)]
Revert "Revert "[InstrProf] Support for external functions in text format.""
Summary:
This reverts commit
364eb09576a7667bc6d3ff80c52a83014ccac976 and separates out
the portion that was fixing binary reader error propagation - turns out, there
are production cases where that causes a regression.
Will re-introduce the error propagation fix separately.
The fix to the text reader error propagation is still "in".
Reviewers: bkramer
Reviewed By: bkramer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44807
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328244
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Craig Topper [Thu, 22 Mar 2018 21:10:07 +0000 (21:10 +0000)]
[X86][SkylakeClient] Fix a bunch of instructions that were incorrectly assigned Port015 instead of Port01.
The VEC ADD and VEC MUL units aren't present on port 5 on SkylakeClient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328241
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Jessica Paquette [Thu, 22 Mar 2018 21:07:09 +0000 (21:07 +0000)]
[MachineOutliner][NFC] Refactoring + comments in runOnModule
Split up some of the if/else branches in runOnModule. Elaborate on some
comments. Replace a call to getOrCreateMachineFunction with getMachineFunction.
This makes it clearer what's happening in runOnModule, and ensures that the
outliner doesn't create any MachineFunctions which will never be used by the
outliner (or anything else, really).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328240
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Jun Bum Lim [Thu, 22 Mar 2018 20:06:47 +0000 (20:06 +0000)]
[CodeGen] Add a new pass for PostRA sink
Summary:
This pass sinks COPY instructions into a successor block, if the COPY is not
used in the current block and the COPY is live-in to a single successor
(i.e., doesn't require the COPY to be duplicated). This avoids executing the
the copy on paths where their results aren't needed. This also exposes
additional opportunites for dead copy elimination and shrink wrapping.
These copies were either not handled by or are inserted after the MachineSink
pass. As an example of the former case, the MachineSink pass cannot sink
COPY instructions with allocatable source registers; for AArch64 these type
of copy instructions are frequently used to move function parameters (PhyReg)
into virtual registers in the entry block..
For the machine IR below, this pass will sink %w19 in the entry into its
successor (%bb.1) because %w19 is only live-in in %bb.1.
```
%bb.0:
%wzr = SUBSWri %w1, 1
%w19 = COPY %w0
Bcc 11, %bb.2
%bb.1:
Live Ins: %w19
BL @fun
%w0 = ADDWrr %w0, %w19
RET %w0
%bb.2:
%w0 = COPY %wzr
RET %w0
```
As we sink %w19 (CSR in AArch64) into %bb.1, the shrink-wrapping pass will be
able to see %bb.0 as a candidate.
With this change I observed 12% more shrink-wrapping candidate and 13% more dead copies deleted in spec2000/2006/2017 on AArch64.
Reviewers: qcolombet, MatzeB, thegameg, mcrosier, gberry, hfinkel, john.brawn, twoh, RKSimon, sebpop, kparzysz
Reviewed By: sebpop
Subscribers: evandro, sebpop, sfertile, aemerson, mgorny, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328237
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Matt Morehouse [Thu, 22 Mar 2018 19:50:10 +0000 (19:50 +0000)]
Document optforfuzzing attribute created in r328214.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328236
91177308-0d34-0410-b5e6-
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Paul Robinson [Thu, 22 Mar 2018 19:37:56 +0000 (19:37 +0000)]
[DWARF] Replace assert with diagnostic. PR36868.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328235
91177308-0d34-0410-b5e6-
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David Blaikie [Thu, 22 Mar 2018 19:36:54 +0000 (19:36 +0000)]
Move the initialization of the Meta Renamer pass over to IPO along with the rest of it that was moved in r328209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328234
91177308-0d34-0410-b5e6-
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Nirav Dave [Thu, 22 Mar 2018 19:32:07 +0000 (19:32 +0000)]
[DAG, X86] Fix ISel-time node insertion ids
As in SystemZ backend, correctly propagate node ids when inserting new
unselected nodes into the DAG during instruction Seleciton for X86
target.
Fixes PR36865.
Reviewers: jyknight, craig.topper
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D44797
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328233
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 22 Mar 2018 19:22:51 +0000 (19:22 +0000)]
[X86] Correct the scheduling data for some of the 32 and 64 bit multiplies to as best as I understand how they are implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328231
91177308-0d34-0410-b5e6-
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Daniel Neilson [Thu, 22 Mar 2018 18:36:15 +0000 (18:36 +0000)]
[InstCombineCalls] Update deprecated API usage (NFC)
Summary:
Just updating a call to MemSetInst::getAlignment() to MemSetInst::getDestAlignment(). The
former has been deprecated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328227
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 22 Mar 2018 18:29:16 +0000 (18:29 +0000)]
[X86][Btver2] Conversion, MaskedLoad/MaskedStore and NTStores all are scheduled through the JFPU1 pipe
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328226
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 22 Mar 2018 17:43:12 +0000 (17:43 +0000)]
[X86][Btver2] FCMP (inc FMAX/FMIN) instructions use the JFPA functional pipe
The ymm instructions are double pumped as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328222
91177308-0d34-0410-b5e6-
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Zachary Turner [Thu, 22 Mar 2018 17:37:28 +0000 (17:37 +0000)]
[Codeview/PDB] Rename some methods for clarity.
NFC, this just renames some methods to better express what they
do, and also adds a few helper methods to add some symmetry to the
API in a few places (for example there was a getStringFromId but not
a getIdFromString method in the string table).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328221
91177308-0d34-0410-b5e6-
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Aditya Nandakumar [Thu, 22 Mar 2018 17:31:38 +0000 (17:31 +0000)]
[GISel]: Fix incorrect IRTranslation while translating null pointer types
https://reviews.llvm.org/D44762
Currently IRTranslator produces
%vreg17<def>(p0) = G_CONSTANT 0;
instead we should build
%vreg16(s64) = G_CONSTANT 0
%vreg17(p0) = G_INTTOPTR %vreg16
reviewed by @aemerson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328218
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 22 Mar 2018 17:25:38 +0000 (17:25 +0000)]
[X86][Btver2] FMUL ymm instructions are double pumped on the JFPM functional pipe
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328217
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 22 Mar 2018 17:17:47 +0000 (17:17 +0000)]
[ARM] Enable the full InstRW overlap check for ARMScheduleR52.td
This fixes a few issues with the R52 instregexs to enable the full overlap checking
Differential Revision: https://reviews.llvm.org/D44767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328216
91177308-0d34-0410-b5e6-
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Matt Morehouse [Thu, 22 Mar 2018 17:07:51 +0000 (17:07 +0000)]
[SimplifyCFG] Create attribute for fuzzing-specific optimizations.
Summary:
When building with libFuzzer, converting control flow to selects or
obscuring the original operands of CMPs reduces the effectiveness of
libFuzzer's heuristics.
This patch provides an attribute to disable or modify certain optimizations
for optimal fuzzing signal.
Provides a less aggressive alternative to https://reviews.llvm.org/D44057.
Reviewers: vitalybuka, davide, arsenm, hfinkel
Reviewed By: vitalybuka
Subscribers: junbuml, mehdi_amini, wdng, javed.absar, hiraditya, llvm-commits, kcc
Differential Revision: https://reviews.llvm.org/D44232
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328214
91177308-0d34-0410-b5e6-
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Alexey Bataev [Thu, 22 Mar 2018 16:43:21 +0000 (16:43 +0000)]
[DWARF] Add EmitDwarfOffset function, NFC.
Added EmitDwarfOffset function after discussion with Eric Christofer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328212
91177308-0d34-0410-b5e6-
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Saleem Abdulrasool [Thu, 22 Mar 2018 16:39:54 +0000 (16:39 +0000)]
vim: rename `singlethread` to `syncscope`
SVN r307722 renamed the keyword from `singlethread` to `syncscope`.
Update the syntax file accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328211
91177308-0d34-0410-b5e6-
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Anna Thomas [Thu, 22 Mar 2018 16:03:59 +0000 (16:03 +0000)]
[LoopPredication] Add profitability check based on BPI
Summary:
LoopPredication is not profitable when the loop is known to always exit
through some block other than the latch block.
A coarse grained latch check can cause loop predication to predicate the
loop, and unconditionally deoptimize.
However, without predicating the loop, the guard may never fail within the
loop during the dynamic execution because the non-latch loop termination
condition exits the loop before the latch condition causes the loop to
exit.
We teach LP about this using BranchProfileInfo pass.
Reviewers: apilipenko, skatkov, mkazantsev, reames
Reviewed by: skatkov
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44667
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328210
91177308-0d34-0410-b5e6-
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David Blaikie [Thu, 22 Mar 2018 15:57:47 +0000 (15:57 +0000)]
Move MetaRenamer from Transforms/UTils to Transforms/IPO since it implements part of IPO.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328209
91177308-0d34-0410-b5e6-
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Paul Robinson [Thu, 22 Mar 2018 15:48:01 +0000 (15:48 +0000)]
[DWARF] Fix mixing assembler -g with DWARF .file directives.
We were effectively overriding an explicit '.file' directive with info
for the assembler source. That shouldn't happen.
Fixes PR36636, really, even for .s files emitted by Clang.
Differential Revision: https://reviews.llvm.org/D44265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328208
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Thu, 22 Mar 2018 15:29:55 +0000 (15:29 +0000)]
Revert "[InstrProf] Support for external functions in text format."
This reverts commit r328132. Breaks FDO selfhost. I'm seeing
error: /tmp/profraw: Invalid instrumentation profile data (bad magic)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328207
91177308-0d34-0410-b5e6-
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Florian Hahn [Thu, 22 Mar 2018 15:23:33 +0000 (15:23 +0000)]
[CallSiteSplitting] Preserve DominatorTreeAnalysis.
The dominator tree analysis can be preserved easily.
Some other kinds of analysis can probably be preserved
too.
Reviewers: junbuml, dberlin
Reviewed By: dberlin
Differential Revision: https://reviews.llvm.org/D43173
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328206
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Sanjay Patel [Thu, 22 Mar 2018 15:23:21 +0000 (15:23 +0000)]
[MC] fix documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328205
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Simon Pilgrim [Thu, 22 Mar 2018 14:56:18 +0000 (14:56 +0000)]
[X86][SSE42] Use the default PCMPEST/PCMPIST scheduler classes directly. NFCI.
Models were completely overriding all SSE42 strins instructions when the default classes could be used for exactly the same coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328203
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Pavel Labath [Thu, 22 Mar 2018 14:50:44 +0000 (14:50 +0000)]
DWARFVerifier: verify debug_names abbreviation table
Summary:
This commit adds checks of the abbreviation table in a DWARF v5 Name
Index. The most interesting/useful check is the one which checks that
each index attributes is encoded using the correct form class, but it
also checks for the more obvious errors like unknown
forms/tags/attributes and duplicated attributes.
Reviewers: JDevlieghere, aprantl, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44736
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328202
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Andrea Di Biagio [Thu, 22 Mar 2018 14:14:49 +0000 (14:14 +0000)]
[llvm-mca] Minor refactoring. NFCI
Also, removed a couple of unused methods from class Instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328198
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Sanjay Patel [Thu, 22 Mar 2018 14:08:16 +0000 (14:08 +0000)]
[InstCombine] add folds for xor-of-icmp signbit tests (PR36682)
This is a retry of r328119 which was reverted at r328145 because
it could crash by trying to combine icmps with different operand
types. This version has a check for that and additional tests.
Original commit message:
This is part of solving:
https://bugs.llvm.org/show_bug.cgi?id=36682
There's also a leftover improvement from the long-ago-closed:
https://bugs.llvm.org/show_bug.cgi?id=5438
https://rise4fun.com/Alive/dC1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328197
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Simon Pilgrim [Thu, 22 Mar 2018 13:37:30 +0000 (13:37 +0000)]
[X86][CLMUL] Use the default CLMUL scheduler classes directly. NFCI.
Models were completely overriding all CLMUL instructions when the WriteCLMUL default classes could be used for exactly the same coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328194
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