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Krzysztof Parzyszek [Mon, 1 Aug 2016 20:31:50 +0000 (20:31 +0000)]
[Hexagon] Tidy up some code, NFC: reapply r277372 with a fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277383
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Xinliang David Li [Mon, 1 Aug 2016 20:25:06 +0000 (20:25 +0000)]
[Profile] IR profiling minor cleanup /nfc
Differential Revision: http://reviews.llvm.org/D22995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277379
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Matthew Simpson [Mon, 1 Aug 2016 20:11:25 +0000 (20:11 +0000)]
[LV] Move isGatherOrScatterLegal into LoopVectorizationLegality (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277376
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Matthew Simpson [Mon, 1 Aug 2016 20:08:09 +0000 (20:08 +0000)]
[LV] Use getPointerOperand helper where appropriate (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277375
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Krzysztof Parzyszek [Mon, 1 Aug 2016 20:00:33 +0000 (20:00 +0000)]
Revert r277372, it is causing buildbot failures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277374
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Krzysztof Parzyszek [Mon, 1 Aug 2016 19:46:21 +0000 (19:46 +0000)]
[Hexagon] Tidy up some code, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277372
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Michael Kuperstein [Mon, 1 Aug 2016 19:39:49 +0000 (19:39 +0000)]
[DAGCombine] Make sext(setcc) combine respect getBooleanContents
We used to combine "sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)"
Instead, we should combine to (select (setcc x, y, cc), T, 0) where the value
of T is 1 or -1, depending on the type of the setcc, and getBooleanContents()
for the type if it is not i1.
This fixes PR28504.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277371
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Ron Lieberman [Mon, 1 Aug 2016 19:36:39 +0000 (19:36 +0000)]
[Hexagon] Generate vector printing instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277370
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George Burgess IV [Mon, 1 Aug 2016 18:47:28 +0000 (18:47 +0000)]
[CFLAA] Remove modref queries from CFLAA.
As it turns out, modref queries are broken with CFLAA. Specifically,
the data source we were using for determining modref behaviors
explicitly ignores operations on non-pointer values. So, it wouldn't
note e.g. storing an i32 to an i32* (or loading an i64 from an i64*).
It also ignores external function calls, rather than acting
conservatively for them.
(N.B. These operations, where necessary, *are* tracked by CFLAA; we just
use a different mechanism to do so. Said mechanism is relatively
imprecise, so it's unlikely that we can provide reasonably good modref
answers with it as implemented.)
Patch by Jia Chen.
Differential Revision: https://reviews.llvm.org/D22978
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277366
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Evandro Menezes [Mon, 1 Aug 2016 18:39:45 +0000 (18:39 +0000)]
[AArch64] Add support for Samsung Exynos M2 (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277364
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George Burgess IV [Mon, 1 Aug 2016 18:27:33 +0000 (18:27 +0000)]
[CFLAA] Make CFLAnders more conservative with new Values.
Currently, CFLAnders assumes that values it hasn't seen don't alias
anything. This patch fixes that. Given that the only way for this to
happen is to query AA, rely on specific transformations happening, then
query AA again (looking for a specific set of queries), lit testing is a
bit difficult. If someone really wants a test, I'm happy to add one.
Patch by Jia Chen.
Differential Revision: https://reviews.llvm.org/D22981
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277362
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David Majnemer [Mon, 1 Aug 2016 18:07:19 +0000 (18:07 +0000)]
Included test for r277360.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277361
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David Majnemer [Mon, 1 Aug 2016 18:06:34 +0000 (18:06 +0000)]
[Verifier] Resume instructions can only be in functions w/ a personality
This fixes PR28799.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277360
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Krzysztof Parzyszek [Mon, 1 Aug 2016 17:55:48 +0000 (17:55 +0000)]
Replace MachineInstr* with MachineInstr& in TargetInstrInfo, NFC
There were a few cases introduced with the modulo scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277358
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Krzysztof Parzyszek [Mon, 1 Aug 2016 17:15:30 +0000 (17:15 +0000)]
[Hexagon] Check for offset overflow when reserving scavenging slots
Scavenging slots were only reserved when pseudo-instruction expansion in
frame lowering created new virtual registers. It is possible to still
need a scavenging slot even if no virtual registers were created, in cases
where the stack is large enough to overflow instruction offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277355
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Nirav Dave [Mon, 1 Aug 2016 15:36:10 +0000 (15:36 +0000)]
Add removed inline-assembly-comment test from r277146
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277349
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Daniel Sanders [Mon, 1 Aug 2016 15:32:51 +0000 (15:32 +0000)]
[mips][fastisel] Correct argument lowering for (f64, f64, i32) and similar.
Summary:
Allocating an AFGR64 shadows two GPR32's instead of just one.
This fixes an LNT regression detected by our internal buildbots.
Reviewers: sdardis
Subscribers: dsanders, sdardis, llvm-commits
Differential Revision: https://reviews.llvm.org/D23012
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277348
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Valery Pykhtin [Mon, 1 Aug 2016 14:21:30 +0000 (14:21 +0000)]
[AMDGPU] refactor DS instruction definitions. NFC.
Differential revision: https://reviews.llvm.org/D22522
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277344
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Simon Pilgrim [Mon, 1 Aug 2016 12:11:43 +0000 (12:11 +0000)]
[X86] Use implicit masking of SHLD/SHRD shift double instructions
Similar to the regular shift instructions, SHLD/SHRD only use the bottom bits of the shift value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277341
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Simon Pilgrim [Mon, 1 Aug 2016 10:40:15 +0000 (10:40 +0000)]
Fixed test check ordering issue on windows buildbots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277337
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Simon Pilgrim [Mon, 1 Aug 2016 09:40:38 +0000 (09:40 +0000)]
Fixed MSVC out of range shift warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277333
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James Molloy [Mon, 1 Aug 2016 09:34:48 +0000 (09:34 +0000)]
[SimplifyCFG] Fix nasty RAUW bug from r277325
Using RAUW was wrong here; if we have a switch transform such as:
18 -> 6 then
6 -> 0
If we use RAUW, while performing the second transform the *transformed* 6
from the first will be also replaced, so we end up with:
18 -> 0
6 -> 0
Found by clang stage2 bootstrap; testcase added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277332
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Diana Picus [Mon, 1 Aug 2016 08:38:49 +0000 (08:38 +0000)]
[AArch64] Return the correct size for TLSDESC_CALLSEQ
The branch relaxation pass is computing the wrong offsets because it assumes
TLSDESC_CALLSEQ eats up 4 bytes, when in fact it is lowered to an instruction
sequence taking up 16 bytes. This can become a problem in huge files with lots
of TLS accesses, as it may slowly move branch targets out of the range computed
by the branch relaxation pass.
Fixes PR24234 https://llvm.org/bugs/show_bug.cgi?id=24234
Differential Revision: https://reviews.llvm.org/D22870
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277331
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Craig Topper [Mon, 1 Aug 2016 08:15:30 +0000 (08:15 +0000)]
[AVX-512] Fix a test missed in r277327.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277330
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James Molloy [Mon, 1 Aug 2016 08:09:55 +0000 (08:09 +0000)]
[SimplifyCFG] Try and pacify buildbots after r277325
It looks like the two independent parts of the rotate operation (a lshr and shl) are being reordered on some bots. Add CHECK-DAGs to account for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277329
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Craig Topper [Mon, 1 Aug 2016 07:55:33 +0000 (07:55 +0000)]
[AVX-512] Fix duplicate column in AVX512 execution dependency table that was preventing VMOVDQU32/VMOVDQA32 from being recognized. Fix a bug in the code that stops execution dependency fix from turning operations on 32-bit integer element types into operations on 64-bit integer element types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277327
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Craig Topper [Mon, 1 Aug 2016 07:55:24 +0000 (07:55 +0000)]
[X86] Regenerate a test to pick up shuffle comments that were added at some point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277326
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James Molloy [Mon, 1 Aug 2016 07:45:11 +0000 (07:45 +0000)]
[SimplifyCFG] Range reduce switches
If a switch is sparse and all the cases (once sorted) are in arithmetic progression, we can extract the common factor out of the switch and create a dense switch. For example:
switch (i) {
case 5: ...
case 9: ...
case 13: ...
case 17: ...
}
can become:
if ( (i - 5) % 4 ) goto default;
switch ((i - 5) / 4) {
case 0: ...
case 1: ...
case 2: ...
case 3: ...
}
or even better:
switch ( ROTR(i - 5, 2) {
case 0: ...
case 1: ...
case 2: ...
case 3: ...
}
The division and remainder operations could be costly so we only do this if the factor is a power of two, and emit a right-rotate instead of a divide/remainder sequence. Dense switches can be lowered significantly better than sparse switches and can even be transformed into lookup tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277325
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Hrvoje Varga [Mon, 1 Aug 2016 06:46:20 +0000 (06:46 +0000)]
[mips] Clang generates unaligned offset for MSA instruction st.d
Differential Revision: https://reviews.llvm.org/D19475
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277323
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Diana Picus [Mon, 1 Aug 2016 05:56:57 +0000 (05:56 +0000)]
[AArch64] Register passes so they can be run by llc
Initialize all AArch64-specific passes in the TargetMachine so they can be run
by llc. This can lead to conflicts in opt with some command line options that
share the same name as the pass, so I took this opportunity to do some cleanups:
* rename all relevant command line options from "aarch64-blah" to
"aarch64-enable-blah" and update the tests accordingly
* run clang-format on their declarations
* move all these declarations to a common place (the TargetMachine) as opposed
to having them scattered around (AArch64BranchRelaxation and
AArch64AddressTypePromotion were the only offenders)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277322
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Craig Topper [Mon, 1 Aug 2016 05:31:50 +0000 (05:31 +0000)]
[AVX-512] Teach X86InstrInfo::getLargestLegalSuperClass to inflate to FR32X/FR64X if AVX512 is supported and VR128X/VR256X if VLX is supported.
Had to update a stack folding test to clobber the other 16 registers since this now made them get used instead of spilling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277321
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Craig Topper [Mon, 1 Aug 2016 04:29:16 +0000 (04:29 +0000)]
[AVX512] Replace scalar fp arithmetic intrinsics with native IR in an AVX512 test. The intrinsics aren't lowered to AVX512 instructions.
The intrinsics really should be removed and autoupgraded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277320
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Craig Topper [Mon, 1 Aug 2016 04:29:13 +0000 (04:29 +0000)]
[AVX-512] Use FR32X/FR64X/VR128X/VR256X register classes in addRegisterClass if AVX512(for FR32X/FR64) or VLX(for VR128X/VR256) is supported. This is a minimal requirement to be able to allocate all 32 registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277319
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Craig Topper [Mon, 1 Aug 2016 04:29:11 +0000 (04:29 +0000)]
[X86] Move mask register handling into the main switch of getLoadStoreRegOpcode. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277318
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Sean Silva [Mon, 1 Aug 2016 04:16:09 +0000 (04:16 +0000)]
Revert r277313 and r277314.
They seem to trigger an LSan failure:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/15140/steps/check-llvm%20asan/logs/stdio
Revert "Add the tests for r277313"
This reverts commit r277314.
Revert "CodeExtractor : Add ability to preserve profile data."
This reverts commit r277313.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277317
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Sean Silva [Mon, 1 Aug 2016 03:22:05 +0000 (03:22 +0000)]
Move this test to x86-specific directory.
No bots have yelled yet, but this test references an x86 intrinsic.
Also, it invokes llc on x86 IR.
Fixup to r277315.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277316
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Sean Silva [Mon, 1 Aug 2016 03:15:32 +0000 (03:15 +0000)]
Fix - CodeExtractor : Inherit Target Dependent Attributes from the parent function.
When extracting a set of blocks make sure to inherit all of the target
dependent attributes to make sure that the function will be valid for
lowering. One example is the "target-features" attribute for x86, if the
extracted region has functionality that relies on a specific feature it
will fail to be lowered.
This also allows for extracted functions to be valid for inlining, at
least back into the parent function, as the target attributes are tested
when inlining for compatibility.
Patch by River Riddle!
Differential Revision: https://reviews.llvm.org/D22713
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277315
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Sean Silva [Mon, 1 Aug 2016 03:04:34 +0000 (03:04 +0000)]
Add the tests for r277313
Forgot to `git add` them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277314
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Sean Silva [Mon, 1 Aug 2016 02:59:26 +0000 (02:59 +0000)]
CodeExtractor : Add ability to preserve profile data.
Added ability to estimate the entry count of the extracted function and
the branch probabilities of the exit branches.
Patch by River Riddle!
Differential Revision: https://reviews.llvm.org/D22744
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277313
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Simon Pilgrim [Sun, 31 Jul 2016 21:59:23 +0000 (21:59 +0000)]
[X86][SSE] Regenerate frem tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277311
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Simon Pilgrim [Sun, 31 Jul 2016 21:55:33 +0000 (21:55 +0000)]
[X86][SSE] Regenerate fpext tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277310
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Daniel Berlin [Sun, 31 Jul 2016 21:08:20 +0000 (21:08 +0000)]
Fix the MemorySSA updating API to enable people to create memory accesses before removing old ones
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277309
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Daniel Berlin [Sun, 31 Jul 2016 21:08:10 +0000 (21:08 +0000)]
Comment fixes to MemorySSA.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277308
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Craig Topper [Sun, 31 Jul 2016 20:20:08 +0000 (20:20 +0000)]
[X86] Simplify code for determing GR or FR reg classes by querying for super classes instead of manually listing individual classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277306
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Craig Topper [Sun, 31 Jul 2016 20:20:05 +0000 (20:20 +0000)]
[AVX512] Always use EVEX encodings for 128/256-bit move instructions in getLoadStoreRegOpcode if VLX is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277305
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Craig Topper [Sun, 31 Jul 2016 20:20:01 +0000 (20:20 +0000)]
[AVX512] Add VLX packed move instructions to the execution dependency fix pass and update tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277304
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Craig Topper [Sun, 31 Jul 2016 20:19:55 +0000 (20:19 +0000)]
[AVX512] Move FR32X/FR64X handling in getLoadStoreRegOpcode into the main switch. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277303
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Craig Topper [Sun, 31 Jul 2016 20:19:53 +0000 (20:19 +0000)]
[AVX512] Stop treating VR512 specially in getLoadStoreRegOpcode and use the regular switch which already tried to handle it, but was unreachable. This has the added benefit of enabling aligned loads/stores if the stack is aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277302
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Craig Topper [Sun, 31 Jul 2016 20:19:50 +0000 (20:19 +0000)]
[AVX512] Add X86::VR512RegClassID to X86RegisterInfo::getLargestLegalSuperClass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277301
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Simon Pilgrim [Sun, 31 Jul 2016 19:50:45 +0000 (19:50 +0000)]
[X86] Improve 64-bit shifts on 32-bit targets (PR14593)
As discussed on PR14593, this patch adds support for lowering to SHLD/SHRD from the patterns generated by DAGTypeLegalizer::ExpandShiftWithKnownAmountBit.
Differential Revision: https://reviews.llvm.org/D23000
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277299
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David Majnemer [Sun, 31 Jul 2016 19:40:02 +0000 (19:40 +0000)]
[COFF] Expose iterators for ImportAddressTableRVA
Patch by Bandzi Michal!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277298
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David Majnemer [Sun, 31 Jul 2016 19:25:21 +0000 (19:25 +0000)]
[COFF] Remove a duplicate import_directory_table_entry definition
We had import_directory_table_entry and
coff_import_directory_table_entry, remove one. Also, factor out the
logic which determins if a descriptor is a terminator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277296
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David Majnemer [Sun, 31 Jul 2016 19:25:16 +0000 (19:25 +0000)]
[bugpoint] Add a -Os option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277295
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Simon Pilgrim [Sun, 31 Jul 2016 17:51:37 +0000 (17:51 +0000)]
[X86] Add tests for the lowering SHLD/SHRD from manual pattern similar to those generated by ExpandShiftWithKnownAmountBit
Test for add(v,v) as well as shl(v,1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277293
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Craig Topper [Sun, 31 Jul 2016 17:15:07 +0000 (17:15 +0000)]
[AVX-512] Don't let ExeDependencyFix pass convert VPANDD/Q to VPANDPS/PD unless DQI instructions are supported. Same for ANDN, OR, and XOR.
Thanks to Igor Breger for pointing out my mistake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277292
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Simon Pilgrim [Sun, 31 Jul 2016 17:11:49 +0000 (17:11 +0000)]
[X86] Add tests for the lowering SHLD/SHRD from manual patterns
As discussed on D23000
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277291
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Amjad Aboud [Sun, 31 Jul 2016 14:41:50 +0000 (14:41 +0000)]
Fixed "copy-paste" mistake from revision 255245.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277290
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Elena Demikhovsky [Sun, 31 Jul 2016 06:48:01 +0000 (06:48 +0000)]
AVX-512: Removed AssertZext node before TRUNCATE
Removed AssertZext node, which was inserted between X86ISD::SETCC and "truncate to i1".
Differential Revision: https://reviews.llvm.org/D22850
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277289
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Chandler Carruth [Sun, 31 Jul 2016 02:19:13 +0000 (02:19 +0000)]
[ADT] Add 'consume_front' and 'consume_back' methods to StringRef which
are very handy when parsing text.
They are essentially a combination of startswith and a self-modifying
drop_front, or endswith and drop_back respectively.
Differential Revision: https://reviews.llvm.org/D22723
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277288
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Davide Italiano [Sat, 30 Jul 2016 22:07:21 +0000 (22:07 +0000)]
[HexagonConstPropagation] Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277285
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Davide Italiano [Sat, 30 Jul 2016 22:07:18 +0000 (22:07 +0000)]
[HexagonBitSimplify] Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277284
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Davide Italiano [Sat, 30 Jul 2016 22:07:15 +0000 (22:07 +0000)]
[ARMConstantIslandPass] Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277283
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Lang Hames [Sat, 30 Jul 2016 21:34:04 +0000 (21:34 +0000)]
[Support] Add doxygen @code tags to example code in Error comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277282
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Simon Pilgrim [Sat, 30 Jul 2016 21:01:34 +0000 (21:01 +0000)]
[SLPVectorizer][X86] Added vXi8/vXi16 sitofp/uitofp tests
Dropped useless 2i32-2f32 test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277281
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Simon Pilgrim [Sat, 30 Jul 2016 20:53:21 +0000 (20:53 +0000)]
Strip trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277280
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Simon Pilgrim [Sat, 30 Jul 2016 20:51:26 +0000 (20:51 +0000)]
[X86] Use peekThroughOneUseBitcasts helper function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277279
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Simon Pilgrim [Sat, 30 Jul 2016 20:28:02 +0000 (20:28 +0000)]
[X86][SSE] Regenerate vshift tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277278
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Simon Pilgrim [Sat, 30 Jul 2016 18:43:30 +0000 (18:43 +0000)]
[SLPVectorizer][X86] Added SITOFP/UITOFP vectorization tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277275
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Simon Pilgrim [Sat, 30 Jul 2016 16:29:19 +0000 (16:29 +0000)]
[X86][AVX] Added signum example test functions from PR13248
These are good examples of missed combine opportunities with zero/all bit vector compare results
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277274
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Simon Pilgrim [Sat, 30 Jul 2016 16:01:30 +0000 (16:01 +0000)]
[X86][X87] Add vector arithmetic tests for targets with sse disabled
To make sure the X86_64 target isn't doing anything stupid
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277272
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Simon Pilgrim [Sat, 30 Jul 2016 14:06:59 +0000 (14:06 +0000)]
[X86][SSE] Let 64-bit targets use the fast 2i32-2f32 UINT_TO_FP conversion as well as 32-bit
The 2i32-2i64 legalization means that we can use the slightly quicker double bits + fptrunc approach for the same results
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277271
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Hubert Tong [Sat, 30 Jul 2016 14:01:00 +0000 (14:01 +0000)]
TrailingObjects::FixedSizeStorage constexpr fixes + tests
Summary:
This change fixes issues with `LLVM_CONSTEXPR` functions and
`TrailingObjects::FixedSizeStorage`. In particular, some of the
functions marked `LLVM_CONSTEXPR` used by `FixedSizeStorage` were not
implemented such that they evaluate successfully as part of a constant
expression despite constant arguments.
This change also implements a more traditional template-meta path to
accommodate MSVC, and adds unit tests for `FixedSizeStorage`.
Drive-by fix: the access control for members of `TrailingObjectsImpl` is
tightened.
Reviewers: faisalv, rsmith, aaron.ballman
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D22668
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277270
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Hubert Tong [Sat, 30 Jul 2016 13:38:51 +0000 (13:38 +0000)]
MathExtras.h: add LLVM_CONSTEXPR where simple
Summary:
This change adds `LLVM_CONSTEXPR` to functions selected as follows:
- the body is already valid under C++11 for a `constexpr` function,
- the evaluation of the function, given constant arguments, will not
fail during the evaluation of a constant expression, and
- the above properties are easily verifiable at a glance.
Note: the evaluation of the function cannot fail if the instantiation
triggers a static assertion failure.
Reviewers: faisalv, rsmith, aaron.ballman
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D22824
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277269
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Benjamin Kramer [Sat, 30 Jul 2016 13:25:37 +0000 (13:25 +0000)]
[Hexagon] Perform bit arithmetic on unsigned to avoid accidentally shifting negative values.
Found by ubsan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277268
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Benjamin Kramer [Sat, 30 Jul 2016 12:05:17 +0000 (12:05 +0000)]
Update modulemap for Msf -> MSF rename.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277267
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Benjamin Kramer [Sat, 30 Jul 2016 11:31:24 +0000 (11:31 +0000)]
[X86] Fix lifetime of SMRange temporaries.
Found by asan -fsanitize-address-use-after-scope.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277266
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Benjamin Kramer [Sat, 30 Jul 2016 11:31:16 +0000 (11:31 +0000)]
[AMDGPU] Fix lifetime of SmallVector temporaries.
Found by asan -fsanitize-address-use-after-scope.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277265
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Matt Arsenault [Sat, 30 Jul 2016 01:40:36 +0000 (01:40 +0000)]
AMDGPU: Fix shouldConvertConstantLoadToIntImm behavior
This should really be true for any immediate, not just
inline ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277260
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Matt Arsenault [Sat, 30 Jul 2016 01:40:34 +0000 (01:40 +0000)]
AMDGPU: Set s_setpc_b64 as a terminator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277259
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Matt Arsenault [Sat, 30 Jul 2016 01:40:30 +0000 (01:40 +0000)]
AMDGPU: Remove unused pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277258
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Lang Hames [Sat, 30 Jul 2016 00:57:54 +0000 (00:57 +0000)]
[Orc] Add support for updating stub targets to CompileOnDemandLayer.
This makes it possible to implement re-optimization on top of the
CompileOnDemandLayer.
Test case to come in a future patch: This will need an execution test, and
execution tests require a full working stack. The best option is to plumb this
API up to the C Bindings stack and add a C bindings test for this.
Patch by Sean Ogden. Thanks Sean!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277257
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Hans Wennborg [Sat, 30 Jul 2016 00:08:45 +0000 (00:08 +0000)]
Remove empty DebugInfo/Msf dirs. It seems these were left over from
the renaming from 'Msf' to 'MSF' in r277213.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277254
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Weiming Zhao [Fri, 29 Jul 2016 23:33:48 +0000 (23:33 +0000)]
DAG: avoid duplicated truncating for sign extended operand
Summary:
When performing cmp for EQ/NE and the operand is sign extended, we can
avoid the truncaton if the bits to be tested are no less than origianl
bits.
Reviewers: eli.friedman
Subscribers: eli.friedman, aemerson, nemanjai, t.p.northover, llvm-commits
Differential Revision: https://reviews.llvm.org/D22933
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277252
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Lang Hames [Fri, 29 Jul 2016 23:17:53 +0000 (23:17 +0000)]
[Support] Add storage specifier for MachO::NListType.
This should fix UB warnings from the sanitizer bots: LLD performs bit
manipulations on enums of this type, and these are UB if the underlying
storage type isn't specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277251
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Tim Northover [Fri, 29 Jul 2016 22:41:55 +0000 (22:41 +0000)]
GlobalISel: translate "unreachable" (into nothing)
Easiest instruction ever!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277225
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Tim Northover [Fri, 29 Jul 2016 22:32:36 +0000 (22:32 +0000)]
GlobalISel: support translation of intrinsic calls.
These come in two variants for now: G_INTRINSIC and G_INTRINSIC_W_SIDE_EFFECTS.
We may decide to split the latter up with finer-grained restrictions later, if
necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277224
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Kevin Enderby [Fri, 29 Jul 2016 22:32:02 +0000 (22:32 +0000)]
Think this will fix issues with the error messages generated for malformed-archives.test
in r277177 and added back this test which was deleted in r277196 while
I tracked down these problems.
Changed from constructing Twine's to std::string's as Twine's don't work
across statements. Also removed a few unneeded Twine() constructions.
Fix the write_escaped() calls to not pass the unintended second argument
fixing the warning on the ld-x86_64-win7 bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277223
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Krzysztof Parzyszek [Fri, 29 Jul 2016 21:49:42 +0000 (21:49 +0000)]
[Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277220
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Michael Kuperstein [Fri, 29 Jul 2016 21:45:51 +0000 (21:45 +0000)]
[X86] Match PSADBW in straight-line code
Up until now, we only had code to match PSADBW patterns that look like what
comes out of the loop vectorizer - a partial reduction inside the loop body
that gets fed into a horizontal operation in a different basic block.
This adds support for straight-line patterns, like those generated by the
SLP vectorizer.
Differential Revision: https://reviews.llvm.org/D22889
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277219
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Michael Kuperstein [Fri, 29 Jul 2016 21:44:33 +0000 (21:44 +0000)]
[Hexagon] Fix test that uses -debug-only to require asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277218
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Rui Ueyama [Fri, 29 Jul 2016 21:38:00 +0000 (21:38 +0000)]
pdbdump: Dump Free Page Map contents.
Differential Revision: https://reviews.llvm.org/D22974
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277216
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Simon Pilgrim [Fri, 29 Jul 2016 21:05:10 +0000 (21:05 +0000)]
[X86][AVX] Fix VBROADCASTF128 selection bug (PR28770)
Support for lowering to VBROADCASTF128 etc. in D22460 was not correctly ensuring that the only users of the 128-bit vector load were the insertions of the vector into the lower/upper subvectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277214
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Zachary Turner [Fri, 29 Jul 2016 20:56:36 +0000 (20:56 +0000)]
[msf] Resubmit "Rename Msf -> MSF".
Previously this change was submitted from a Windows machine, so
changes made to the case of filenames and directory names did
not survive the commit, and as a result the CMake source file
names and the on-disk file names did not match on case-sensitive
file systems.
I'm resubmitting this patch from a Linux system, which hopefully
allows the case changes to make it through unfettered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277213
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Tim Northover [Fri, 29 Jul 2016 20:32:59 +0000 (20:32 +0000)]
CodeGen: add new "intrinsic" MachineOperand kind.
This will be used during GlobalISel, where we need a more robust and readable
way to write tests than a simple immediate ID.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277209
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Eli Bendersky [Fri, 29 Jul 2016 19:35:22 +0000 (19:35 +0000)]
Add a REQUIRES: assert on a Lanai test that uses a -debug-only flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277204
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Adam Nemet [Fri, 29 Jul 2016 19:29:47 +0000 (19:29 +0000)]
[LoopUnroll] Include hotness of region in opt remark
LoopUnroll is a loop pass, so the analysis of OptimizationRemarkEmitter
is added to the common function analysis passes that loop passes
depend on.
The BFI and indirectly BPI used in this pass is computed lazily so no
overhead should be observed unless -pass-remarks-with-hotness is used.
This is how the patch affects the O3 pipeline:
Dominator Tree Construction
Natural Loop Information
Canonicalize natural loops
Loop-Closed SSA Form Pass
Basic Alias Analysis (stateless AA impl)
Function Alias Analysis Results
Scalar Evolution Analysis
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
Loop Pass Manager
Rotate Loops
Loop Invariant Code Motion
Unswitch loops
Simplify the CFG
Dominator Tree Construction
Basic Alias Analysis (stateless AA impl)
Function Alias Analysis Results
Combine redundant instructions
Natural Loop Information
Canonicalize natural loops
Loop-Closed SSA Form Pass
Scalar Evolution Analysis
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
Loop Pass Manager
Induction Variable Simplification
Recognize loop idioms
Delete dead loops
Unroll loops
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277203
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Ahmed Bougacha [Fri, 29 Jul 2016 19:19:32 +0000 (19:19 +0000)]
[GlobalISel] Add missing link components to r277160 unittest. NFC.
It broke a shared builder:
http://lab.llvm.org:8011/builders/llvm-mips-linux/builds/17320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277201
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Simon Pilgrim [Fri, 29 Jul 2016 18:58:57 +0000 (18:58 +0000)]
Fixed line endings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277199
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Simon Pilgrim [Fri, 29 Jul 2016 18:57:32 +0000 (18:57 +0000)]
Fixed (incorrectly firing) MSVC unused variable warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277198
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David Majnemer [Fri, 29 Jul 2016 18:48:27 +0000 (18:48 +0000)]
[ConstantFolding] Handle bitcasts of undef fp vector elements
We used the wrong type for constructing a zero vector element which led
to type mismatches.
This fixes PR28771.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277197
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