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Craig Topper [Mon, 30 Sep 2013 02:46:36 +0000 (02:46 +0000)]
Various x86 disassembler fixes.
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191649
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Benjamin Kramer [Sun, 29 Sep 2013 19:39:13 +0000 (19:39 +0000)]
ObjectSizeOffsetEvaluator: Don't run into infinite recursion if we have a cyclic GEP.
Those can occur in dead code. PR17402.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191644
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Benjamin Kramer [Sun, 29 Sep 2013 19:39:02 +0000 (19:39 +0000)]
Remove an old workaround for a compiler that EOL'd years ago.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191643
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Benjamin Kramer [Sun, 29 Sep 2013 11:29:20 +0000 (11:29 +0000)]
Plug a memory leak in a unit test. Stack allocation is sufficient here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191638
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Benjamin Kramer [Sun, 29 Sep 2013 11:24:02 +0000 (11:24 +0000)]
Deallocate type units when destroying a DWARFContext.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191637
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Benjamin Kramer [Sun, 29 Sep 2013 11:18:56 +0000 (11:18 +0000)]
Allocate AtomicSDNode operands in SelectionDAG's allocator to stop leakage.
SDNode destructors are never called. As an optimization use AtomicSDNode's
internal storage if we have a small number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191636
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Craig Topper [Sun, 29 Sep 2013 08:35:51 +0000 (08:35 +0000)]
Revert accidental commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191633
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Craig Topper [Sun, 29 Sep 2013 08:33:34 +0000 (08:33 +0000)]
Change type of XOP flag in code emitters to a bool. Remove a some unneeded cases from switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191632
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Craig Topper [Sun, 29 Sep 2013 06:31:18 +0000 (06:31 +0000)]
Add comments for XOPA map introduced with TBM instructions.a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191630
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Benjamin Kramer [Sat, 28 Sep 2013 21:27:49 +0000 (21:27 +0000)]
Add a test that large offsets on GEPs on 32 bits targets are handled correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191628
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Chandler Carruth [Sat, 28 Sep 2013 18:17:10 +0000 (18:17 +0000)]
Enable libcxx as part of the top level CMake build when it is checked
out in projects. This appears to be working on my system, and I will be
watching build bots to see if there are any issues on other platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191624
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Robert Wilhelm [Sat, 28 Sep 2013 13:42:22 +0000 (13:42 +0000)]
Even more spelling fixes for "instruction".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191611
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Robert Wilhelm [Sat, 28 Sep 2013 11:46:15 +0000 (11:46 +0000)]
Fix spelling intruction -> instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191610
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Tom Stellard [Sat, 28 Sep 2013 03:10:17 +0000 (03:10 +0000)]
SelectionDAG: Silence unused variable warning on release builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191604
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Tom Stellard [Sat, 28 Sep 2013 02:50:50 +0000 (02:50 +0000)]
R600: Fix handling of NAN in comparison instructions
We were completely ignoring the unorder/ordered attributes of condition
codes and also incorrectly lowering seto and setuo.
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191603
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Tom Stellard [Sat, 28 Sep 2013 02:50:43 +0000 (02:50 +0000)]
SelectionDAG: Improve legalization of SELECT_CC with illegal condition codes
SelectionDAG will now attempt to inverse an illegal conditon in order to
find a legal one and if that doesn't work, it will attempt to swap the
operands using the inverted condition.
There are no new test cases for this, but a nubmer of the existing R600
tests hit this path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191602
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Tom Stellard [Sat, 28 Sep 2013 02:50:38 +0000 (02:50 +0000)]
SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()
This is useful for targets like R600, which only support GT, GE, NE, and EQ
condition codes as it removes the need to handle unsupported condition
codes in target specific code.
There are no tests with this commit, but R600 has been updated to take
advantage of this new feature, so its existing selectcc tests are now
testing the swapped operands path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191601
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Tom Stellard [Sat, 28 Sep 2013 02:50:32 +0000 (02:50 +0000)]
SelectionDAG: Clean up LegalizeSetCCCondCode() function
Interpreting the results of this function is not very intuitive, so I
cleaned it up to make it more clear whether or not a SETCC op was
legalized and how it was legalized (either by swapping LHS and RHS or
replacing with AND/OR).
This patch does change functionality in the LHS and RHS swapping case,
but unfortunately there are no in-tree tests for this. However, this
patch is a prerequisite for R600 to take advantage of the LHS and RHS
swapping, so tests will be added in subsequent commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191600
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NAKAMURA Takumi [Sat, 28 Sep 2013 01:35:07 +0000 (01:35 +0000)]
MipsMachineFunction.cpp: Add missing #include <raw_ostream.h>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191597
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Matt Arsenault [Sat, 28 Sep 2013 01:08:00 +0000 (01:08 +0000)]
Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191595
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Manman Ren [Sat, 28 Sep 2013 00:22:27 +0000 (00:22 +0000)]
AutoUpgrade: upgrade from scalar TBAA format to struct-path aware TBAA format.
We treat TBAA tags as struct-path aware TBAA format when the first operand
is a MDNode and the tag has 3 or more operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191593
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Akira Hatanaka [Sat, 28 Sep 2013 00:12:32 +0000 (00:12 +0000)]
[mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out
of loops.
Previously, two consecutive calls to function "func" would result in the
following sequence of instructions:
1. load $16, %got(func)($gp) // load address of lazy-binding stub.
2. move $25, $16
3. jalr $25 // jump to lazy-binding stub.
4. nop
5. move $25, $16
6. jalr $25 // jump to lazy-binding stub again.
With this patch, the second call directly jumps to func's address, bypassing
the lazy-binding resolution routine:
1. load $25, %got(func)($gp) // load address of lazy-binding stub.
2. jalr $25 // jump to lazy-binding stub.
3. nop
4. load $25, %got(func)($gp) // load resolved address of func.
5. jalr $25 // directly jump to func.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191591
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Manman Ren [Fri, 27 Sep 2013 22:59:21 +0000 (22:59 +0000)]
TBAA: try to fix the dragonegg bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191585
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Eric Christopher [Fri, 27 Sep 2013 22:50:48 +0000 (22:50 +0000)]
Unify conditionals and reformat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191582
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Matt Arsenault [Fri, 27 Sep 2013 22:38:23 +0000 (22:38 +0000)]
Minor code simplification
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191579
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Akira Hatanaka [Fri, 27 Sep 2013 22:30:36 +0000 (22:30 +0000)]
[mips] Define a derived class of PseudoSourceValue that represents a GOT entry
resolved by lazy-binding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191578
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Matt Arsenault [Fri, 27 Sep 2013 22:26:25 +0000 (22:26 +0000)]
Use right pointer type in DebugIR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191576
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Matt Arsenault [Fri, 27 Sep 2013 22:18:51 +0000 (22:18 +0000)]
Use type helper functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191574
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Eric Christopher [Fri, 27 Sep 2013 22:10:10 +0000 (22:10 +0000)]
Rework conditional for printing out pub sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191571
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Josh Magee [Fri, 27 Sep 2013 21:58:43 +0000 (21:58 +0000)]
[stackprotector] Refactor the StackProtector pass from a single .cpp file into StackProtector.h and StackProtector.cpp.
No functionality change. Future patches will add analysis which will be used
in other passes (PEI, StackSlot). The end goal is to support ssp-strong stack
layout rules.
WIP.
Differential Revision: http://llvm-reviews.chandlerc.com/D1521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191570
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Rui Ueyama [Fri, 27 Sep 2013 21:47:05 +0000 (21:47 +0000)]
Object/COFF: Rename getXXX{Begin,End} -> xxx_{begin,end}.
It is mentioned in the LLVM coding standard that _begin() and _end() suffixes
should be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191569
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Rui Ueyama [Fri, 27 Sep 2013 21:26:38 +0000 (21:26 +0000)]
Resurrect lit.local.cfg to un-break hexagon buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191565
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Matt Arsenault [Fri, 27 Sep 2013 21:24:57 +0000 (21:24 +0000)]
Fix SLPVectorizer using wrong address space for load/store
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191564
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Dmitri Gribenko [Fri, 27 Sep 2013 21:24:36 +0000 (21:24 +0000)]
SourceMgr diagnotics printing: fix a bug where printing a fixit for a source
range that includes a tab character will cause out-of-bounds access to the
fixit string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191563
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Renato Golin [Fri, 27 Sep 2013 21:14:54 +0000 (21:14 +0000)]
Clarifying doc about cross-compiling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191561
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Dmitri Gribenko [Fri, 27 Sep 2013 21:09:25 +0000 (21:09 +0000)]
Make SourceMgr::PrintMessage() testable and add unit tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191558
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Rui Ueyama [Fri, 27 Sep 2013 21:04:00 +0000 (21:04 +0000)]
Re-submit r191472 with a fix for big endian.
llvm-objdump: Dump COFF import table if -private-headers option is given.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191557
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Bill Wendling [Fri, 27 Sep 2013 20:40:40 +0000 (20:40 +0000)]
Update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191553
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Justin Bogner [Fri, 27 Sep 2013 20:35:39 +0000 (20:35 +0000)]
InstCombine: Only foldSelectICmpAndOr for integer types
Currently foldSelectICmpAndOr asserts if the "or" involves a vector
containing several of the same power of two. We can easily avoid this by
only performing the fold on integer types, like foldSelectICmpAnd does.
Fixes <rdar://problem/
15012516>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191552
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Akira Hatanaka [Fri, 27 Sep 2013 19:51:35 +0000 (19:51 +0000)]
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191546
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Yunzhong Gao [Fri, 27 Sep 2013 18:38:42 +0000 (18:38 +0000)]
Adding intrinsics to the llvm backend for TBM instruction set.
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539
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Manman Ren [Fri, 27 Sep 2013 18:34:27 +0000 (18:34 +0000)]
TBAA: handle scalar TBAA format and struct-path aware TBAA format.
Remove the command line argument "struct-path-tbaa" since we should not depend
on command line argument to decide which format the IR file is using. Instead,
we check the first operand of the tbaa tag node, if it is a MDNode, we treat
it as struct-path aware TBAA format, otherwise, we treat it as scalar TBAA
format.
When clang starts to use struct-path aware TBAA format no matter whether
struct-path-tbaa is no, and we can auto-upgrade existing bc files, the support
for scalar TBAA format can be dropped.
Existing testing cases are updated to use the struct-path aware TBAA format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191538
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Justin Bogner [Fri, 27 Sep 2013 15:30:25 +0000 (15:30 +0000)]
Transforms: Use getFirstNonPHI to set the insertion point for PHIs
We were previously using getFirstInsertionPt to insert PHI
instructions when vectorizing, but getFirstInsertionPt also skips past
landingpads, causing this to generate invalid IR.
We can avoid this issue by using getFirstNonPHI instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191526
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Richard Sandiford [Fri, 27 Sep 2013 15:29:20 +0000 (15:29 +0000)]
[SystemZ] Rein back the use of block operations
The backend tries to use block operations like MVC, NC, OC and XC for
simple scalar operations. For correctness reasons, it rejects any case
in which the regions might partially overlap. However, for performance
reasons, it should also reject cases where the regions might be equal,
since the instruction might then not use the fast path.
This fixes a performance regression seen in bzip2. We may want to limit
the optimisation even more in future, or even remove it entirely, but I'll
try with this for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191525
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Richard Sandiford [Fri, 27 Sep 2013 15:14:04 +0000 (15:14 +0000)]
[SystemZ] Improve handling of PC-relative addresses
The backend previously folded offsets into PC-relative addresses
whereever possible. That's the right thing to do when the address
can be used directly in a PC-relative memory reference (using things
like LRL). But if we have a register-based memory reference and need
to load the PC-relative address separately, it's better to use an anchor
point that could be shared with other accesses to the same area of the
variable.
Fixes a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191524
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Daniel Sanders [Fri, 27 Sep 2013 13:36:54 +0000 (13:36 +0000)]
[mips][msa] Implemented insert.d intrinsic.
This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is
further lowered into a sequence of insert.w's on MIPS32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191521
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Tilmann Scheller [Fri, 27 Sep 2013 13:28:17 +0000 (13:28 +0000)]
ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands.
As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints:
LDRD<c> <Rt>, <Rt2>, ...
(a) Rt must be even-numbered and not r14
(b) Rt2 must be R(t+1)
If those two constraints are not met the result of executing the instruction will be unpredictable.
Constraint (b) was already enforced, this commit adds support for constraint (a).
Fixes rdar://
14479793.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191520
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Daniel Sanders [Fri, 27 Sep 2013 13:20:41 +0000 (13:20 +0000)]
[mips][msa] Implemented fill.d intrinsic.
This intrinsic is lowered into an equivalent BUILD_VECTOR which is further
lowered into a sequence of insert.w's on MIPS32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191519
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Daniel Sanders [Fri, 27 Sep 2013 13:04:21 +0000 (13:04 +0000)]
[mips][msa] Implemented copy_[us].d intrinsic.
This intrinsic is lowered into equivalent copy_s.w instructions during
legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191518
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Daniel Sanders [Fri, 27 Sep 2013 12:45:08 +0000 (12:45 +0000)]
[mips][msa] Rename arguments to MSA_INSERT_DESC_BASE to better match their expected values.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191517
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Daniel Sanders [Fri, 27 Sep 2013 12:31:32 +0000 (12:31 +0000)]
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.
For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is
later expanded to appropriate insve.[wd] insns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191515
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Daniel Sanders [Fri, 27 Sep 2013 12:17:32 +0000 (12:17 +0000)]
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64
For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may
be expanded to subregister copies and/or instructions as appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514
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Andrea Di Biagio [Fri, 27 Sep 2013 12:13:58 +0000 (12:13 +0000)]
Remove superfluous comment accidentally checked-in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191513
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Daniel Sanders [Fri, 27 Sep 2013 12:03:51 +0000 (12:03 +0000)]
[mips][msa] Added support for MSA registers to copyPhysReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191512
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Daniel Sanders [Fri, 27 Sep 2013 11:48:57 +0000 (11:48 +0000)]
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics)
Updated some of the vshf since they (correctly) emit splati's now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191511
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Andrea Di Biagio [Fri, 27 Sep 2013 11:37:05 +0000 (11:37 +0000)]
Re-apply the change from r191393 with fix for pr17380.
This change fixes the problem reported in pr17380 and re-add the dagcombine
transformation ensuring that the value types are always legal if the
transformation is triggered after Legalization took place.
Added the test case from pr17380.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191509
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Daniel Sanders [Fri, 27 Sep 2013 10:42:22 +0000 (10:42 +0000)]
[mips][msa] Added MSA.txt to describe instruction selection quirks.
This file contains notes about the instruction selection for MSA. For example,
it notes that ilvl.d is cannot be selected because ilvev.d covers the same
cases and is selected instead of ilvl.d.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191507
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Tilmann Scheller [Fri, 27 Sep 2013 10:38:11 +0000 (10:38 +0000)]
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191505
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Tilmann Scheller [Fri, 27 Sep 2013 10:30:18 +0000 (10:30 +0000)]
ARM: Teach assembler to enforce constraint for Thumb2 LDRD (literal/immediate) destination register operands.
LDRD<c> <Rt>, <Rt2>, <label>
LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}]
LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm>
LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!
As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2.
If this constraint is not met the result of executing the instruction will be unpredictable.
Fixes rdar://
14479780.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191504
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Daniel Sanders [Fri, 27 Sep 2013 10:25:41 +0000 (10:25 +0000)]
[mips][msa] Tidy up
lowerMSABinaryIntr, lowerMSABinaryImmIntr, lowerMSABranchIntr,
and lowerMSAUnaryIntr were trivially small functions. Inlined them into
their callers.
lowerMSASplat now takes its callers SDLoc instead of making a new one.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191503
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Daniel Sanders [Fri, 27 Sep 2013 10:08:31 +0000 (10:08 +0000)]
[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498
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Daniel Sanders [Fri, 27 Sep 2013 09:44:59 +0000 (09:44 +0000)]
[mips][msa] Expand all truncstores and loadexts for MSA as well as DSP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191496
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Daniel Sanders [Fri, 27 Sep 2013 09:25:29 +0000 (09:25 +0000)]
[mips][msa] Added missing check in performSRACombine
Reviewers: jacksprat, dsanders
Reviewed By: dsanders
Differential Revision: http://llvm-reviews.chandlerc.com/D1755
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191495
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Puyan Lotfi [Fri, 27 Sep 2013 07:36:10 +0000 (07:36 +0000)]
First check in. Modified a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191491
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Craig Topper [Fri, 27 Sep 2013 07:20:47 +0000 (07:20 +0000)]
Put HasAVX512 predicate on some patterns to properly disable them when AVX512 isn't enabled. Currently it works simply because the SSE and AVX version of the same patterns are checked first in the DAG isel table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191490
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Craig Topper [Fri, 27 Sep 2013 07:16:24 +0000 (07:16 +0000)]
Switch HasAVX to UseAVX in one spot to ensure that AVX512 form of VINSERTPS is used in AVX512 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191489
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Craig Topper [Fri, 27 Sep 2013 07:11:17 +0000 (07:11 +0000)]
Removal some duplicate patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191488
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Yunzhong Gao [Fri, 27 Sep 2013 01:44:23 +0000 (01:44 +0000)]
Fixing Intel format of the vshufpd instruction.
Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191481
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Rui Ueyama [Fri, 27 Sep 2013 01:29:36 +0000 (01:29 +0000)]
Revert "llvm-objdump: Dump COFF import table if -private-headers option is given."
This reverts commit r191472 because it's failing on BE machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191480
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Rui Ueyama [Fri, 27 Sep 2013 00:53:07 +0000 (00:53 +0000)]
Fix another -Wnon-pod-varargs error in r191472.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191474
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Rui Ueyama [Fri, 27 Sep 2013 00:20:53 +0000 (00:20 +0000)]
Fix -Wnon-pod-varargs error in r191472.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191473
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Rui Ueyama [Fri, 27 Sep 2013 00:07:01 +0000 (00:07 +0000)]
llvm-objdump: Dump COFF import table if -private-headers option is given.
This is a patch to add capability to llvm-objdump to dump COFF Import Table
entries, so that we can write tests for LLD checking Import Table contents.
llvm-objdump did not print anything but just file name if the format is COFF
and -private-headers option is given. This is a patch adds capability for
dumping DLL Import Table, which is specific to the COFF format.
In this patch I defined a new iterator to iterate over import table entries.
Also added a few functions to COFFObjectFile.cpp to access fields of the entry.
Differential Revision: http://llvm-reviews.chandlerc.com/D1719
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191472
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Adrian Prantl [Thu, 26 Sep 2013 23:37:11 +0000 (23:37 +0000)]
MCParser/Debug info: Accept line number 0 as a legitimate value, since
CFE produces it to indicate artificial locations.
c.f.: DWARF standard, Table 6.2:
line -- An unsigned integer indicating a source line number. Lines are numbered beginning at 1. The compiler may emit the value 0 in cases where an instruction cannot be attributed to any source line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191471
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Jack Carter [Thu, 26 Sep 2013 21:31:43 +0000 (21:31 +0000)]
[mips][msa] Direct Object Emission for 3RF instructions.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191461
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Jack Carter [Thu, 26 Sep 2013 21:18:57 +0000 (21:18 +0000)]
[mips][msa] Updates encoding of 3RF instructions to match the latest revision of the MSA spec (1.06).
This does not affect any of the existing output.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191460
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Weiming Zhao [Thu, 26 Sep 2013 17:25:10 +0000 (17:25 +0000)]
Fix PR 17372: Emitting PLD for stack address for ARM Thumb2
t2PLDi12, t2PLDi8, t2PLDs was omitted in Thumb2InstrInfo.
This patch fixes it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191441
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Bill Schmidt [Thu, 26 Sep 2013 17:09:28 +0000 (17:09 +0000)]
[PowerPC] Fix PR17354: Generate nop after local calls for PIC code.
When generating code for shared libraries, even local calls may be
intercepted, so we need a nop after the call for the linker to fix up the
TOC. Test case adapted from the one provided in PR17354.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191440
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Andrea Di Biagio [Thu, 26 Sep 2013 16:54:01 +0000 (16:54 +0000)]
Revert r191393 since it caused pr17380.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191438
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Venkatraman Govindaraju [Thu, 26 Sep 2013 15:11:00 +0000 (15:11 +0000)]
[Sparc] Implements exception handling in SPARC with DwarfCFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191432
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Venkatraman Govindaraju [Thu, 26 Sep 2013 14:49:40 +0000 (14:49 +0000)]
Implements parsing and emitting of .cfi_window_save in MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191431
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Amara Emerson [Thu, 26 Sep 2013 12:22:36 +0000 (12:22 +0000)]
[ARM] Use the load-acquire/store-release instructions optimally in AArch32.
Patch by Artyom Skrobov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191428
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David Majnemer [Thu, 26 Sep 2013 09:18:48 +0000 (09:18 +0000)]
PPC: Allow partial fills in writeNopData()
When asked to pad an irregular number of bytes, we should fill with
zeros. This is consistent with the behavior specified in the AIX
Assembler Language Reference as well as other LLVM and binutils
assemblers.
N.B. There is a small deviation from binutils' PPC assembler:
when handling pads which are greater than 4 bytes but not mod 4,
binutils will not emit any NOP sequences at all and only use zeros.
This may or may not be a bug but there is no excellent rationale as to
why that behavior is important to emulate. If that behavior is needed,
we can change writeNopData() to behave in the same way.
This fixes PR17352.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191426
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Renato Golin [Thu, 26 Sep 2013 08:57:07 +0000 (08:57 +0000)]
Add links to cross-compilation docs from getting started
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191425
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Andrew Trick [Thu, 26 Sep 2013 05:53:35 +0000 (05:53 +0000)]
Added temp flag -misched-bench for staging in default changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191423
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Andrew Trick [Thu, 26 Sep 2013 05:53:31 +0000 (05:53 +0000)]
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191422
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David Majnemer [Thu, 26 Sep 2013 05:22:11 +0000 (05:22 +0000)]
PPC: Do not introduce ISD nodes for fctid and fctiw
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191421
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David Majnemer [Thu, 26 Sep 2013 04:11:24 +0000 (04:11 +0000)]
PPC: Add support for fctid and fctiw
Encodings were checked against the Power ISA documents and double
checked against binutils.
This fixes PR17350.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191419
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Jack Carter [Thu, 26 Sep 2013 00:09:46 +0000 (00:09 +0000)]
[mips][msa] Direct Object Emission for 3R instructions.
This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191415
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Jack Carter [Thu, 26 Sep 2013 00:02:44 +0000 (00:02 +0000)]
[mips][msa] Updates encoding of 3R instructions to match the latest revision of the MSA spec (1.06).
Internal changes only.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191414
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Jack Carter [Wed, 25 Sep 2013 23:56:25 +0000 (23:56 +0000)]
[mips][msa] Direct Object Emission for 2RF instructions.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191413
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Jack Carter [Wed, 25 Sep 2013 23:50:44 +0000 (23:50 +0000)]
[mips][msa] Direct Object Emission support for the MSA instruction set.
In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions.
Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function).
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191412
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Jack Carter [Wed, 25 Sep 2013 23:42:03 +0000 (23:42 +0000)]
[mips][msa] Updates encoding of 2RF instructions to match the latest revision of the MSA spec (1.06).
This only changes internal encodings and doesn't affect output.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191411
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Weiming Zhao [Wed, 25 Sep 2013 23:12:06 +0000 (23:12 +0000)]
Fix PR 17368: disable vector mul distribution for square of add/sub for ARM
Generally, it is desirable to distribute (a + b) * c to a*c + b*c for
ARM with VMLx forwarding, where a, b and c are vectors.
However, for (a + b)*(a + b), distribution will result in one extra
instruction.
With distribution:
x = a + b (add)
y = a * x (mul)
z = y + b * y (mla)
Without distribution:
x = a + b (add)
z = x * x (mul)
This patch checks if a mul is a square of add/sub. If yes, skip
distribution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191410
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Eric Christopher [Wed, 25 Sep 2013 23:02:44 +0000 (23:02 +0000)]
Add gnu pubsections as options to llvm-dwarfdump.
Argument spelling feedback welcome.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191409
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Eric Christopher [Wed, 25 Sep 2013 23:02:41 +0000 (23:02 +0000)]
Dump the normal dwarf pubtypes section as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191408
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Eric Christopher [Wed, 25 Sep 2013 23:02:36 +0000 (23:02 +0000)]
Unify pubsection/gnu pubsection printing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191407
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Josh Magee [Wed, 25 Sep 2013 22:07:48 +0000 (22:07 +0000)]
Test commit. Removed trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191402
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Eric Christopher [Wed, 25 Sep 2013 21:17:37 +0000 (21:17 +0000)]
Slight formatting change for pubnames/pubtypes output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191401
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Reed Kotler [Wed, 25 Sep 2013 20:58:50 +0000 (20:58 +0000)]
Fix a bad typo in the inline assembly code for mips16 pic fp stubs
and make one cosmetic cleanup to make it look the same as gcc
in this area; adjusting test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191400
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Andrea Di Biagio [Wed, 25 Sep 2013 19:01:01 +0000 (19:01 +0000)]
Teach DAGCombiner how to canonicalize dags according to the rule
(shl (zext (shr A, X)), X) => (zext (shl (shr A, X), X)).
The rule only triggers when there are no other uses of the
zext to avoid materializing more instructions.
This helps the DAGCombiner understand that the shl/shr
sequence can then be converted into an and instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191393
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