OSDN Git Service
Matthias Braun [Fri, 17 Feb 2017 23:15:03 +0000 (23:15 +0000)]
AArch64LoadStoreOptimizer: Correctly clear kill flags
When promoting the Load of a Store-Load pair to a COPY all kill flags
between the store and the load need to be cleared.
rdar://
30402435
Differential Revision: https://reviews.llvm.org/D30110
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295512
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Simon Pilgrim [Fri, 17 Feb 2017 23:00:21 +0000 (23:00 +0000)]
[X86] Add MOVBE targets to load combine tests
Test folded endian swap tests with MOVBE instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295508
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Guozhi Wei [Fri, 17 Feb 2017 22:29:39 +0000 (22:29 +0000)]
[PPC] Give unaligned memory access lower cost on processor that supports it
Newer ppc supports unaligned memory access, it reduces the cost of unaligned memory access significantly. This patch handles this case in PPCTTIImpl::getMemoryOpCost.
This patch fixes pr31492.
Differential Revision: https://reviews.llvm.org/D28630
This is resubmit of r292680, which was reverted by r293092. The internal application failures were actually caused by a source code bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295506
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Eugene Zelenko [Fri, 17 Feb 2017 22:23:34 +0000 (22:23 +0000)]
[CodeGen] Revert changes in LowLevelType to pre-r295499 to fix broken buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295505
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Krzysztof Parzyszek [Fri, 17 Feb 2017 22:14:51 +0000 (22:14 +0000)]
[Hexagon] Start using regmasks on calls
Reapply r295371 with a fix for the Windows bot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295504
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Davide Italiano [Fri, 17 Feb 2017 22:12:30 +0000 (22:12 +0000)]
[NewGVN] isOnlyReachableViaThisEdge() is dead now. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295503
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Simon Pilgrim [Fri, 17 Feb 2017 22:10:10 +0000 (22:10 +0000)]
[X86] Simplify by pulling out valuetype. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295502
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Eugene Zelenko [Fri, 17 Feb 2017 22:07:26 +0000 (22:07 +0000)]
[CodeGen] Attempt to fix buildbots broken in r295499.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295501
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Davide Italiano [Fri, 17 Feb 2017 21:55:47 +0000 (21:55 +0000)]
[NewGVN] createVariableOrConstant is not required anymore. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295500
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Eugene Zelenko [Fri, 17 Feb 2017 21:43:25 +0000 (21:43 +0000)]
[CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295499
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Simon Pilgrim [Fri, 17 Feb 2017 21:16:24 +0000 (21:16 +0000)]
[X86] Add subborrow stack folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295496
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Sanjay Patel [Fri, 17 Feb 2017 21:10:40 +0000 (21:10 +0000)]
[x86] add tests for sext (not bool); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295495
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Matthew Simpson [Fri, 17 Feb 2017 20:46:52 +0000 (20:46 +0000)]
[LAA] Remove unused code (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295493
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Simon Pilgrim [Fri, 17 Feb 2017 20:43:32 +0000 (20:43 +0000)]
[X86][SSE] Add (V)MOVD folding pattern with zextloadi64i32 load node.
Fixes PRPR31309
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295492
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Adrian Prantl [Fri, 17 Feb 2017 20:02:26 +0000 (20:02 +0000)]
Fix windows bots by locking down the target triple on this testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295490
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Matt Arsenault [Fri, 17 Feb 2017 19:49:10 +0000 (19:49 +0000)]
AMDGPU: Fix crashes on invalid icmp/fcmp intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295489
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Peter Collingbourne [Fri, 17 Feb 2017 19:43:45 +0000 (19:43 +0000)]
WholeProgramDevirt: For VCP use a 32-bit ConstantInt for the byte offset.
A future change will cause this byte offset to be inttoptr'd and then exported
via an absolute symbol. On the importing end we will expect the symbol to be
in range [0,2^32) so that it will fit into a 32-bit relocation. The problem
is that on 64-bit architectures if the offset is negative it will not be in
the correct range once we inttoptr it.
This change causes us to use a 32-bit integer so that it can be inttoptr'd
(which zero extends) into the correct range.
Differential Revision: https://reviews.llvm.org/D30016
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295487
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Adrian Prantl [Fri, 17 Feb 2017 19:42:32 +0000 (19:42 +0000)]
Debug Info: Sort frame index expressions before emitting them.
This fixes PR31381, which caused an assertion and/or invalid debug info.
This affects debug variables that have multiple fragments in the MMI
side (i.e.: in the stack frame) table.
rdar://problem/
30571676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295486
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Petr Hosek [Fri, 17 Feb 2017 19:29:12 +0000 (19:29 +0000)]
[CMake] Support externalizing debug info on non-Darwin platforms
On other platorms, we use objcopy to export the debug info.
Differential Revision: https://reviews.llvm.org/D28575
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295481
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Simon Pilgrim [Fri, 17 Feb 2017 19:24:55 +0000 (19:24 +0000)]
[X86][SHA] Add SHA stack folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295479
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Artyom Skrobov [Fri, 17 Feb 2017 18:59:16 +0000 (18:59 +0000)]
In Thumb1 mode, the custom lowering for ARMISD::CMPZ could never emit tADDi3
Reviewers: jmolloy, t.p.northover
Reviewed By: t.p.northover
Subscribers: t.p.northover, aemerson, rengolin, llvm-commits
Differential Revision: https://reviews.llvm.org/D30097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295478
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Simon Pilgrim [Fri, 17 Feb 2017 18:51:53 +0000 (18:51 +0000)]
[X86][TBM] Add TBM stack folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295477
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Tim Northover [Fri, 17 Feb 2017 18:50:15 +0000 (18:50 +0000)]
GlobalISel: verify that generic loads & stores have a mem operand.
The mem operand is used by GlobalISel to convey atomic constraints so dropping
it is invalid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295476
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Joel Jones [Fri, 17 Feb 2017 18:34:24 +0000 (18:34 +0000)]
[AArch64] Add Cavium ThunderX support
This set of patches adds support for Cavium ThunderX ARM64 processors:
* ThunderX
* ThunderX T81
* ThunderX T83
* ThunderX T88
Patch by Stefan Teleman
Differential Revision: https://reviews.llvm.org/D28891
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295475
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Peter Collingbourne [Fri, 17 Feb 2017 18:17:04 +0000 (18:17 +0000)]
WholeProgramDevirt: Examine the function body when deciding whether functions are readnone.
The goal is to get an analysis result even for de-refineable functions.
Differential Revision: https://reviews.llvm.org/D29803
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295472
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Simon Pilgrim [Fri, 17 Feb 2017 18:00:43 +0000 (18:00 +0000)]
[X86][BMI] Add BMI2 stack folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295470
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Peter Collingbourne [Fri, 17 Feb 2017 17:36:52 +0000 (17:36 +0000)]
opt: Rename -default-data-layout flag to -data-layout and make it always override the layout.
There isn't much point in a flag that only works if the data layout is empty.
Differential Revision: https://reviews.llvm.org/D30014
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295468
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Justin Bogner [Fri, 17 Feb 2017 17:34:37 +0000 (17:34 +0000)]
OptDiag: Rename DiagnosticInfoWithDebugLoc to WithLocation. NFC
This generalizes the name in preparation for decoupling the concept
from DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295465
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Rui Ueyama [Fri, 17 Feb 2017 17:32:54 +0000 (17:32 +0000)]
MC/COFF: Do not emit forward associative section referenceds.
MSVC link.exe cannot handle associative sections that refer later
sections in the section header. Technically, such COFF object doesn't
violate the Microsoft COFF spec, as the spec doesn't say anything
about that, but still we should avoid doing that to make it compatible
with MS tools.
This patch assigns smaller section numbers to non-associative sections
and larger numbers to associative sections. This should resolve the
compatibility issue.
Differential Revision: https://reviews.llvm.org/D30080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295464
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Sanjay Patel [Fri, 17 Feb 2017 17:13:27 +0000 (17:13 +0000)]
[DAGCombiner] split i1 select-of-constants from non-i1 case; NFCI
I can't find any tests of the non-i1 code path, so it may be unnecessary at this point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295463
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Simon Pilgrim [Fri, 17 Feb 2017 17:11:00 +0000 (17:11 +0000)]
[X86][BMI] Add BMI stack folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295462
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Sanjay Patel [Fri, 17 Feb 2017 16:43:43 +0000 (16:43 +0000)]
[PowerPC] add tests for select-of-constants; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295460
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Sanjay Patel [Fri, 17 Feb 2017 16:34:13 +0000 (16:34 +0000)]
[ARM] add tests for select-of-constants; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295459
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Matthew Simpson [Fri, 17 Feb 2017 16:09:07 +0000 (16:09 +0000)]
[LV] Remove constant restriction for vector phi creation
We previously only created a vector phi node for an induction variable if its
step had a constant integer type. However, the step actually only needs to be
loop-invariant. We only handle inductions having loop-invariant steps, so this
patch should enable vector phi node creation for all integer induction
variables that will be vectorized.
Differential Revision: https://reviews.llvm.org/D29956
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295456
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Simon Pilgrim [Fri, 17 Feb 2017 16:01:16 +0000 (16:01 +0000)]
Fix signed/unsigned comparison warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295453
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Sam Parker [Fri, 17 Feb 2017 15:42:44 +0000 (15:42 +0000)]
[ARM] Replace HasT2ExtractPack with HasDSP
Removed the HasT2ExtractPack feature and replaced its references
with HasDSP. This then allows the Thumb2 extend instructions to be
selected for ARMv8M +dsp. These instruction descriptions have also
been refactored and more target tests have been added for their isel.
Differential Revision: https://reviews.llvm.org/D29623
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295452
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Simon Pilgrim [Fri, 17 Feb 2017 15:14:48 +0000 (15:14 +0000)]
[DAGCombine] Recognise any_extend_vector_inreg and truncation style shuffle masks
During legalization we are often creating shuffles (via a build_vector scalarization stage) that are "any_extend_vector_inreg" style masks, and also other masks that are the equivalent of "truncate_vector_inreg" (if we had such a thing).
This patch is an attempt to match these cases to help undo the effects of just leaving shuffle lowering to handle it - which typically means we lose track of the undefined elements of the shuffles resulting in an unnecessary extension+truncation stage for widened illegal types.
The 2011-10-21-widen-cmp.ll regression will be fixed by making SIGN_EXTEND_VECTOR_IN_REG legal in SSE instead of lowering them to X86ISD::VSEXT (PR31712).
Differential Revision: https://reviews.llvm.org/D29454
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295451
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Sanjay Patel [Fri, 17 Feb 2017 14:21:59 +0000 (14:21 +0000)]
[DAGCombiner] improve readability; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295447
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Diana Picus [Fri, 17 Feb 2017 13:44:19 +0000 (13:44 +0000)]
[ARM] GlobalISel: Clean up some helpers
Return invalid opcodes when some of the helpers in the instruction selection
pass can't handle a given combination.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295446
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Diana Picus [Fri, 17 Feb 2017 13:14:25 +0000 (13:14 +0000)]
[ARM] GlobalISel: Check mappings used by reg bank select
Add some asserts to make sure we're using the mappings that we think we're
using. This is to keep us from accidentally breaking functionality while moving
to TableGen'erated mappings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295441
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Diana Picus [Fri, 17 Feb 2017 11:25:17 +0000 (11:25 +0000)]
[ARM] GlobalISel: Use Subtarget in Legalizer
Start using the Subtarget to make decisions about what's legal. In particular,
we only mark floating point operations as legal if we have VFP2, which is
something we should've done from the very start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295439
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Diana Picus [Fri, 17 Feb 2017 11:25:11 +0000 (11:25 +0000)]
[ARM] GlobalISel: Add end-to-end tests for double
Test some really basic functionality through the whole GlobalISel pipeline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295438
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Ismail Donmez [Fri, 17 Feb 2017 08:26:11 +0000 (08:26 +0000)]
Update Bugzilla URLs in docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295432
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Eugene Leviant [Fri, 17 Feb 2017 07:36:03 +0000 (07:36 +0000)]
InstCombine: fix extraction when performing vector/array punning
Differential revision: https://reviews.llvm.org/D29491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295429
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Craig Topper [Fri, 17 Feb 2017 07:07:24 +0000 (07:07 +0000)]
[IR][X86] Simplify some AutoUpgrade code slightly. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295426
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Craig Topper [Fri, 17 Feb 2017 07:07:21 +0000 (07:07 +0000)]
[IR][X86] Rename an AutoUpgrade helper function to more accurately match what intrinsics it handles. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295425
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Craig Topper [Fri, 17 Feb 2017 07:07:19 +0000 (07:07 +0000)]
[IR][X86] Move X86 specific portions of UpgradeIntrinsicFunction1 to a couple helper functions. NFC
This enables some early outs to avoid repeatedly using IsX86 check to qualify. I hope to continue to improve this to shorten the lengths of some of the string comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295424
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Andrew Wilkins [Fri, 17 Feb 2017 05:41:05 +0000 (05:41 +0000)]
Go binding: Add methods for missing PassManagerBuilder C APIs
Patch by Ryuichi Hayashida!
Differential Revision: http://reviews.llvm.org/D30042
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295420
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Sanjoy Das [Fri, 17 Feb 2017 04:21:14 +0000 (04:21 +0000)]
[JumpThreading] Re-enable JumpThreading for guards
Summary:
JumpThreading for guards feature has been reverted at https://reviews.llvm.org/rL295200
due to the following problem: the feature used the following algorithm for detection of
diamond patters:
1. Find a block with 2 predecessors;
2. Check that these blocks have a common single parent;
3. Check that the parent's terminator is a branch instruction.
The problem is that these checks are insufficient. They may pass for a non-diamond
construction in case if those two predecessors are actually the same block. This may
happen if parent's terminator is a br (either conditional or unconditional) to a block
that ends with "switch" instruction with exactly two branches going to one block.
This patch re-enables the JumpThreading for guards and fixes this issue by adding the
check that those found predecessors are actually different blocks. This guarantees that
parent's terminator is a conditional branch with exactly 2 different successors, which
is now ensured by assertions. It also adds two more tests for this situation (with parent's
terminator being a conditional and an unconditional branch).
Patch by Max Kazantsev!
Reviewers: anna, sanjoy, reames
Reviewed By: sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30036
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295410
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Rafael Espindola [Fri, 17 Feb 2017 02:08:58 +0000 (02:08 +0000)]
Revert "[Hexagon] Start using regmasks on calls"
This reverts commit r295371.
It broke windows bots:
http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295402
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Dean Michael Berris [Fri, 17 Feb 2017 01:47:16 +0000 (01:47 +0000)]
[XRAY] [x86_64] Adding a Flight Data filetype reader to the llvm-xray Trace implementation.
Summary:
The file type packs function trace data onto disk from potentially multiple
threads that are aggregated and flushed during the course of an instrumented
program's runtime.
It is named FDR mode or Flight Data recorder as an analogy to plane
blackboxes, which instrument a running system without access to IO.
The writer code is defined in compiler-rt in xray_fdr_logging.h/cc
Reviewers: rSerge, kcc, dberris
Reviewed By: dberris
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D29697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295397
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Teresa Johnson [Fri, 17 Feb 2017 01:23:28 +0000 (01:23 +0000)]
Move test to X86 subdirectory for bot failures
Second attempt at fixing bot failures from r295384.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295395
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Chandler Carruth [Fri, 17 Feb 2017 01:18:38 +0000 (01:18 +0000)]
[x86] Give this test a triple so that we don't have to cope with two
different asm comment syntaxes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295394
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Chris Bieneman [Fri, 17 Feb 2017 01:11:41 +0000 (01:11 +0000)]
[CMake] Add variable IOS to iOS toolchain
This is useful for some edge cases where detecting things gets tricky. Specifically LLDB needs this to support iOS because CMake doesn't support running tests using obj-c code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295392
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Teresa Johnson [Fri, 17 Feb 2017 00:52:09 +0000 (00:52 +0000)]
Attempt to fix bot failures by adding -mtriple to llc invocation
Failures on hexagon from test added with r295384, e.g.:
http://lab.llvm.org:8011/builders/llvm-hexagon-elf/builds/3793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295389
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Matt Arsenault [Fri, 17 Feb 2017 00:32:19 +0000 (00:32 +0000)]
Bug 31948: Fix assertion when bitcasting constantexpr pointers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295387
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Chandler Carruth [Fri, 17 Feb 2017 00:29:59 +0000 (00:29 +0000)]
FileCheck-ize some tests in test/CodeGen/X86/
Patch by Jorge Gorbe!
Differential Revision: https://reviews.llvm.org/D29807
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295386
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Teresa Johnson [Fri, 17 Feb 2017 00:21:19 +0000 (00:21 +0000)]
Handle link of NoDebug CU with a CU that has debug emission enabled
Summary:
This is an issue both with regular and Thin LTO. When we link together
a DICompileUnit that is marked NoDebug (e.g when compiling with -g0
but applying an AutoFDO profile, which requires location tracking
in the compiler) and a DICompileUnit with debug emission enabled,
we can have failures during dwarf debug generation. Specifically,
when we have inlined from the NoDebug compile unit into the debug
compile unit, we can fail during construction of the abstract and
inlined scope DIEs. This is because the SPMap does not include NoDebug
CUs (they are skipped in the debug_compile_units_iterator).
This patch fixes the failures by skipping locations from NoDebug CUs
when extracting lexical scopes.
Reviewers: dblaikie, aprantl
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D29765
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295384
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Eugene Zelenko [Fri, 17 Feb 2017 00:00:09 +0000 (00:00 +0000)]
[IR] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295383
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Zachary Turner [Thu, 16 Feb 2017 23:35:45 +0000 (23:35 +0000)]
[pdb] Add the ability to resolve TypeServer PDBs.
Some PDBs or object files can contain references to other PDBs
where the real type information lives. When this happens,
all type indices in the original PDB are meaningless because
their records are not there.
With this patch we add the ability to pull type info from those
secondary PDBs.
Differential Revision: https://reviews.llvm.org/D29973
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295382
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Wei Mi [Thu, 16 Feb 2017 21:27:31 +0000 (21:27 +0000)]
[LSR] Prevent formula with SCEVAddRecExpr type of Reg from Sibling loops
In rL294814, we allow formula with SCEVAddRecExpr type of Reg from loops
other than current loop. This is good for the case when induction variable
of outerloop being used in expr in innerloop. But it is very bad to allow
such Reg from sibling loop because we may need to add lsr.iv in other sibling
loops when scev expanding those SCEVAddRecExpr type exprs. For the testcase
below, one loop can be inserted with a bunch of lsr.iv because of LSR for
other loops.
// The induction variable j from a loop in the middle will have initial
// value generated from previous sibling loop and exit value used by its
// next sibling loop.
void goo(long i, long j);
long cond;
void foo(long N) {
long i = 0;
long j = 0;
i = 0; do { goo(i, j); i++; j++; } while (cond);
i = 0; do { goo(i, j); i++; j++; } while (cond);
i = 0; do { goo(i, j); i++; j++; } while (cond);
i = 0; do { goo(i, j); i++; j++; } while (cond);
i = 0; do { goo(i, j); i++; j++; } while (cond);
i = 0; do { goo(i, j); i++; j++; } while (cond);
}
The fix is to only allow formula with SCEVAddRecExpr type of Reg from current
loop or its parents.
Differential Revision: https://reviews.llvm.org/D30021
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295378
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David Blaikie [Thu, 16 Feb 2017 20:55:48 +0000 (20:55 +0000)]
Fix -Wunused-lambda-capture by removing some unused lambda captures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295373
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Benjamin Kramer [Thu, 16 Feb 2017 20:26:51 +0000 (20:26 +0000)]
[MachinePipeliner] Remove redundant destructor. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295372
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Krzysztof Parzyszek [Thu, 16 Feb 2017 20:25:23 +0000 (20:25 +0000)]
[Hexagon] Start using regmasks on calls
All the cool targets are doing it...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295371
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Erich Keane [Thu, 16 Feb 2017 20:19:49 +0000 (20:19 +0000)]
Change default TimerGroup singleton to use magic statics
TimerGroup was showing up on a leak in valigrind, and
used some pretty complex code to implement a singleton.
This patch replaces the implementation with a vastly simpler
one.
Differential Revision: https://reviews.llvm.org/D28367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295370
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Krzysztof Parzyszek [Thu, 16 Feb 2017 19:28:06 +0000 (19:28 +0000)]
[RDF] Aggregate shadow phi uses into one cluster when propagating live info
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295366
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Simon Pilgrim [Thu, 16 Feb 2017 19:17:36 +0000 (19:17 +0000)]
[X86][SSE] Add PR31309 test case (load-extend i32 to i128).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295363
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Matt Arsenault [Thu, 16 Feb 2017 19:09:04 +0000 (19:09 +0000)]
AMDGPU: Remove llvm.AMDGPU.cube intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295359
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Matt Arsenault [Thu, 16 Feb 2017 19:08:58 +0000 (19:08 +0000)]
AMDGPU: Remove llvm.AMDGPU.rsq intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295358
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Hans Wennborg [Thu, 16 Feb 2017 19:04:42 +0000 (19:04 +0000)]
Re-apply r282920 "X86: Allow conditional tail calls in Win64 "leaf" functions (PR26302)"
The original commit was reverted in r283329 due to a miscompile in
Chromium. That turned out to be the same issue as PR31257, which was
fixed in r295262.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295357
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Krzysztof Parzyszek [Thu, 16 Feb 2017 18:53:04 +0000 (18:53 +0000)]
[RDF] Differentiate between defining and clobbering nodes
Defining nodes should not alias with one another, while clobbering
nodes can. When pushing defs on stacks, push clobbers first, link
non-clobbering defs, then push the defs.
The data flow in a statement is now: uses -> clobbers -> defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295356
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David Blaikie [Thu, 16 Feb 2017 18:48:33 +0000 (18:48 +0000)]
Refactor DebugHandlerBase a bit to common non-debug-having-function filtering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295354
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Matt Arsenault [Thu, 16 Feb 2017 18:46:24 +0000 (18:46 +0000)]
InstCombine: Canonicalize fast fmuladd to fmul + fadd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295353
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Krzysztof Parzyszek [Thu, 16 Feb 2017 18:45:23 +0000 (18:45 +0000)]
[RDF] Move normalize(RegisterRef) to PhysicalRegisterInfo
Remove the duplicate from DFG and make some members of PRI private.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295351
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Andrea Di Biagio [Thu, 16 Feb 2017 18:25:37 +0000 (18:25 +0000)]
x86 interrupt calling convention: only save xmm registers if the target supports SSE
The existing code always saves the xmm registers for 64-bit targets even if the
target doesn't support SSE (which is common for kernels). Thus, the compiler
inserts movaps instructions which lead to CPU exceptions when an interrupt
handler is invoked.
This commit fixes this bug by returning a register set without xmm registers
from getCalleeSavedRegs and getCallPreservedMask for such targets.
Patch by Philipp Oppermann.
Differential Revision: https://reviews.llvm.org/D29959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295347
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Sanjay Patel [Thu, 16 Feb 2017 18:15:16 +0000 (18:15 +0000)]
[x86] add more tests of select of constants; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295346
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Artur Pilipenko [Thu, 16 Feb 2017 17:07:27 +0000 (17:07 +0000)]
[DAGCombiner] Support {a|s}ext, {a|z|s}ext load nodes in load combine
Resubmit -r295314 with PowerPC and AMDGPU tests updated.
Support {a|s}ext, {a|z|s}ext load nodes as a part of load combine patters.
Reviewed By: filcab
Differential Revision: https://reviews.llvm.org/D29591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295336
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Sjoerd Meijer [Thu, 16 Feb 2017 15:52:22 +0000 (15:52 +0000)]
[AArch64] AArch64AsmParser clean up of isImmediate functions. NFC
Regression test neon-diagnostics.s needed changing because it now
produces a more specific diagnostic about the immediate ranges. One
change in the expected error message is not obvious, but there multiple
candidate and it happens to pick the immediate diagnostic.
Differential Revision: https://reviews.llvm.org/D29939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295331
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Dan Gohman [Thu, 16 Feb 2017 15:21:37 +0000 (15:21 +0000)]
[WebAssembly] Add a cast to void to fix an unused private member warning, for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295327
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Simon Pilgrim [Thu, 16 Feb 2017 15:11:49 +0000 (15:11 +0000)]
[X86] Remove local areOnlyUsersOf helper and use SDNode::areOnlyUsersOf instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295326
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Marshall Clow [Thu, 16 Feb 2017 14:37:03 +0000 (14:37 +0000)]
Remove uses of deprecated std::random_shuffle in the LLVM code base. Reviewed as https://reviews.llvm.org/D29780.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295325
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Diana Picus [Thu, 16 Feb 2017 14:10:50 +0000 (14:10 +0000)]
[ARM] GlobalISel: Select floating point loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295321
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Artur Pilipenko [Thu, 16 Feb 2017 13:04:46 +0000 (13:04 +0000)]
Rever -r295314 "[DAGCombiner] Support {a|s}ext, {a|z|s}ext load nodes in load combine"
This change causes some of AMDGPU and PowerPC tests to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295316
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Artur Pilipenko [Thu, 16 Feb 2017 12:53:26 +0000 (12:53 +0000)]
[DAGCombiner] Support {a|s}ext, {a|z|s}ext load nodes in load combine
Support {a|s}ext, {a|z|s}ext load nodes as a part of load combine patters.
Reviewed By: filcab
Differential Revision: https://reviews.llvm.org/D29591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295314
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Diana Picus [Thu, 16 Feb 2017 12:19:57 +0000 (12:19 +0000)]
[ARM] GlobalISel: Select G_SEQUENCE and G_EXTRACT
Since they're only used for passing around double precision floating point
values into the general purpose registers, we'll lower them to VMOVDRR and
VMOVRRD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295310
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Diana Picus [Thu, 16 Feb 2017 12:19:52 +0000 (12:19 +0000)]
[ARM] GlobalISel: Select double G_FADD and copies
Just use VADDD if available, bail out if not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295309
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Diana Picus [Thu, 16 Feb 2017 11:25:09 +0000 (11:25 +0000)]
[ARM] GlobalISel: Assert that we don't use the FPR bank if we don't have VFP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295308
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Diana Picus [Thu, 16 Feb 2017 11:00:31 +0000 (11:00 +0000)]
[ARM] GlobalISel: Add reg bank mappings for G_SEQUENCE and G_EXTRACT
Support G_SEQUENCE and G_EXTRACT as needed for passing double precision floating
point values in the soft-fp float mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295306
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Diana Picus [Thu, 16 Feb 2017 10:12:49 +0000 (10:12 +0000)]
[ARM] GlobalISel: Make the FPR bank 64-bit wide
Also add mappings for single and double precision FP, and use them for G_FADD
and G_LOAD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295302
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Diana Picus [Thu, 16 Feb 2017 09:09:49 +0000 (09:09 +0000)]
[ARM] GlobalISel: Legalize 64-bit G_FADD and G_LOAD
For now we just mark them as legal all the time and let the other passes bail
out if they can't handle it. In the future, we'll want to move more of the
brains into the legalizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295300
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NAKAMURA Takumi [Thu, 16 Feb 2017 08:22:08 +0000 (08:22 +0000)]
RWMutex.h: Use llvm-config.h instead of config.h in installed headers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295297
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Diana Picus [Thu, 16 Feb 2017 07:53:07 +0000 (07:53 +0000)]
[ARM] GlobalISel: Lower double precision FP args
For the hard float calling convention, we just use the D registers.
For the soft-fp calling convention, we use the R registers and move values
to/from the D registers by means of G_SEQUENCE/G_EXTRACT. While doing so, we
make sure to honor the endianness of the target, since the CCAssignFn doesn't do
that for us.
For pure soft float targets, we still bail out because we don't support the
libcalls yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295295
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Craig Topper [Thu, 16 Feb 2017 07:35:23 +0000 (07:35 +0000)]
[AVX-512][InstCombine] Teach InstCombine to optimize 512-bit packss/packus intrinsics like it does 128/256-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295294
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Craig Topper [Thu, 16 Feb 2017 06:31:54 +0000 (06:31 +0000)]
[AVX-512] Remove masked packss/packus intrinsics and autoupgrade to unmasked intrinsics with select instructions. For 512-bit add new unmasked intrinsics.
The new 512-bit unmasked intrinsics will make it easy to handle these with the SSE/AVX intrinsics in InstCombine where we currently have a TODO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295290
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Rui Ueyama [Thu, 16 Feb 2017 02:56:06 +0000 (02:56 +0000)]
Split WinCOFFObjectWriter::writeSection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295276
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Rui Ueyama [Thu, 16 Feb 2017 02:35:48 +0000 (02:35 +0000)]
Split WinCOFFObjectWriter::writeObject function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295273
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Matt Arsenault [Thu, 16 Feb 2017 02:01:17 +0000 (02:01 +0000)]
AMDGPU: Remove llvm.SI.sendmsg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295270
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Matt Arsenault [Thu, 16 Feb 2017 02:01:13 +0000 (02:01 +0000)]
AMDGPU: Remove SI_fs_constant and SI_fs_interp intrinsics
Update test uses with expansion in terms of new intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295269
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Rui Ueyama [Thu, 16 Feb 2017 01:41:04 +0000 (01:41 +0000)]
Remove useless local variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295268
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Rui Ueyama [Thu, 16 Feb 2017 01:06:45 +0000 (01:06 +0000)]
Rename variables to match the LLVM style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295265
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