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David Bolvansky [Thu, 4 Jul 2019 13:48:32 +0000 (13:48 +0000)]
[NFC] Added tests for D64099
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365141
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Simon Pilgrim [Thu, 4 Jul 2019 13:31:49 +0000 (13:31 +0000)]
[X86][SSE] Add some partial dereferenceable vector load tests inspired by PR16739
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365138
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Michael Liao [Thu, 4 Jul 2019 13:29:45 +0000 (13:29 +0000)]
[AMDGPU] Correct the setting of `FlatScratchInit`.
Summary: - That flag setting should skip spilling stack slot.
Reviewers: arsenm, rampitec
Subscribers: qcolombet, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64143
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365137
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Simon Pilgrim [Thu, 4 Jul 2019 12:33:37 +0000 (12:33 +0000)]
[X86] Regenerate load fold peephole test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365136
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Simon Pilgrim [Thu, 4 Jul 2019 10:35:31 +0000 (10:35 +0000)]
Fix -Wdocumentation param warning.
Don't put the full stop at the end of a param name - it confuses the doxygen parser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365128
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Simon Pilgrim [Thu, 4 Jul 2019 10:33:21 +0000 (10:33 +0000)]
Fix -Wdocumentation warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365127
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Simon Pilgrim [Thu, 4 Jul 2019 10:17:10 +0000 (10:17 +0000)]
[X86][AVX1] Combine concat_vectors(pshufd(x,c),pshufd(y,c)) -> vpermilps(concat_vectors(x,y),c)
Bitcast v4i32 to v8f32 and back again - it might be worth adding isel patterns for X86PShufd v8i32 on AVX1 targets like we did for X86Blendi to avoid the bitcasts?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365125
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Simon Pilgrim [Thu, 4 Jul 2019 09:46:06 +0000 (09:46 +0000)]
Fix MSVC "not all control paths return a value" warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365119
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Mikael Holmen [Thu, 4 Jul 2019 09:29:18 +0000 (09:29 +0000)]
[Remarks] Silence gcc warning by catching unhandled values in switches
Without this fix gcc (7.4) complains with
../lib/Remarks/RemarkParser.cpp: In function 'std::unique_ptr<llvm::remarks::ParserImpl> formatToParserImpl(llvm::remarks::ParserFormat, llvm::StringRef)':
../lib/Remarks/RemarkParser.cpp:29:1: error: control reaches end of non-void function [-Werror=return-type]
}
^
../lib/Remarks/RemarkParser.cpp: In function 'std::unique_ptr<llvm::remarks::ParserImpl> formatToParserImpl(llvm::remarks::ParserFormat, llvm::StringRef, const llvm::remarks::ParsedStringTable&)':
../lib/Remarks/RemarkParser.cpp:38:1: error: control reaches end of non-void function [-Werror=return-type]
}
^
The Format enum currently only contains the value YAML which is indeed
already handled in the switches, but gcc complains anyway.
Adding a default case with an llvm_unreachable silences gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365118
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David Green [Thu, 4 Jul 2019 08:58:58 +0000 (08:58 +0000)]
[ARM] Favour PL/MI over GE/LT when possible
The arm condition codes for GE is N==V (and for LT is N!=V). If the source of
flags cannot set V (overflow), such as a cmp against #0, then we can use the
simpler PL and MI conditions that only check N. As these PL/MI conditions are
simpler than GE/LT, other passes like the peephole optimiser can have a better
time optimising away the redundant CMPs.
The exception is the VSEL instruction, which cannot take the PL code, so there
the transform favours GE.
Differential Revision: https://reviews.llvm.org/D64160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365117
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David Green [Thu, 4 Jul 2019 08:49:32 +0000 (08:49 +0000)]
[ARM] Added testing for D64160. NFC
Adds some extra vsel testing and regenerates long shift and saturation bitop
tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365116
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James Henderson [Thu, 4 Jul 2019 08:49:04 +0000 (08:49 +0000)]
[docs][llvm-dwarfdump] Remove unnecessary reference to --show-children
The --show-children option description describes what it does, and
references the =<offset> parameter of section dump switches. I don't
think it needs to be explained again in the documentation of the
section dump switches too.
Reviewed by: JDevlieghere
Differential Revision: https://reviews.llvm.org/D64132
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365115
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Simon Tatham [Thu, 4 Jul 2019 08:43:20 +0000 (08:43 +0000)]
[TableGen] Allow DAG isel patterns to override default operands.
When a Tablegen instruction description uses `OperandWithDefaultOps`,
isel patterns for that instruction don't have to fill in the default
value for the operand in question. But the flip side is that they
actually //can't// override the defaults even if they want to.
This will be very inconvenient for the Arm backend, when we start
wanting to write isel patterns that generate the many MVE predicated
vector instructions, in the form with predication actually enabled. So
this small Tablegen fix makes it possible to write an isel pattern
either with or without values for a defaulted operand, and have the
default values filled in only if they are not overridden.
If all the defaulted operands come at the end of the instruction's
operand list, there's a natural way to match them up to the arguments
supplied in the pattern: consume pattern arguments until you run out,
then fill in any missing instruction operands with their default
values. But if defaulted and non-defaulted operands are interleaved,
it's less clear what to do. This does happen in existing targets (the
first example I came across was KILLGT, in the AMDGPU/R600 backend),
and of course they expect the previous behaviour (that the default for
those operands is used and a pattern argument is not consumed), so for
backwards compatibility I've stuck with that.
Reviewers: nhaehnle, hfinkel, dmgreen
Subscribers: mehdi_amini, javed.absar, tpr, kristof.beyls, steven_wu, dexonsmith, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63814
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365114
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David Green [Thu, 4 Jul 2019 08:41:23 +0000 (08:41 +0000)]
[ARM] MVE bitwise instruction patterns
This adds patterns for the simpler VAND, VORR and VEOR bitwise vector
instructions. It also adjusts the top16Zero PatLeaf to not match on vector
instructions, which can otherwise cause problems.
Code written by David Sherwood.
Differential Revision: https://reviews.llvm.org/D63867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365113
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QingShan Zhang [Thu, 4 Jul 2019 07:43:51 +0000 (07:43 +0000)]
[NFC][PowerPC] Make the PowerPC scheduling strategy feature only control the strategy instead of the scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365110
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Craig Topper [Thu, 4 Jul 2019 06:21:54 +0000 (06:21 +0000)]
[X86] Use pointer sized indices instead of i32 for EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT in a couple places.
Most places already did this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365109
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Dylan McKay [Thu, 4 Jul 2019 06:12:47 +0000 (06:12 +0000)]
[AVR] Fix tests after r363757
r363757 renamed ExpandISelPseudo to FinalizeISel, so the RUN line in
select-must-add-unconditional-jump.mir needed updating to refer to finalize-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365108
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Serguei Katkov [Thu, 4 Jul 2019 05:10:14 +0000 (05:10 +0000)]
[LoopPeel] Some small comment update. NFC.
Follow-up change of comment after
https://reviews.llvm.org/D63917 is landed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365107
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Fangrui Song [Thu, 4 Jul 2019 04:44:42 +0000 (04:44 +0000)]
[PowerPC] Support constraint code "ww"
Summary:
"ww" and "ws" are both constraint codes for VSX vector registers that
hold scalar double data. "ww" is preferred for float while "ws" is
preferred for double.
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D64119
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365106
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Alex Brachet [Thu, 4 Jul 2019 04:41:06 +0000 (04:41 +0000)]
[docs] [NFC] Removed excess spacing
Summary: Removed excess new lines from documentations. As far as I can tell, it seems as though restructured text is agnostic to new lines, the use of new lines was inconsistent and had no effect on how the files were being displayed.
Reviewers: jhenderson, rupprecht, JDevlieghere
Reviewed By: jhenderson
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63971
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365105
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Chen Zheng [Thu, 4 Jul 2019 01:51:47 +0000 (01:51 +0000)]
[PowerPC] Hardware Loop branch instruction's condition may not be icmp.
This fixes pr42492.
Differential Revision: https://reviews.llvm.org/D64124
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365104
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Francis Visoiu Mistrih [Thu, 4 Jul 2019 00:31:03 +0000 (00:31 +0000)]
[Remarks] Require an explicit format to the parser
Make the parser require an explicit format.
This allows new formats to be easily added by following YAML as an
example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365102
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Francis Visoiu Mistrih [Thu, 4 Jul 2019 00:30:58 +0000 (00:30 +0000)]
[Remarks][NFC] Move the string table parsing out of the parser constructor
Make the parser take an already-parsed string table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365101
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Derek Schuff [Thu, 4 Jul 2019 00:24:35 +0000 (00:24 +0000)]
[WebAssembly] Update test failure explanations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365100
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Shoaib Meenai [Thu, 4 Jul 2019 00:17:02 +0000 (00:17 +0000)]
[MachO] Add valid architecture function
Added array of valid architectures and function returning array.
Modified llvm-lipo to include list of valid architectures in error message for invalid arch.
Patch by Anusha Basana <anusha.basana@gmail.com>
Differential Revision: https://reviews.llvm.org/D63735
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365099
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Lang Hames [Thu, 4 Jul 2019 00:05:12 +0000 (00:05 +0000)]
[JITLink][ORC] Add EHFrameRegistrar interface, use in EHFrameRegistrationPlugin.
Replaces direct calls to eh-frame registration with calls to methods on an
EHFrameRegistrar instance. This allows clients to substitute a registrar that
registers frames in a remote process via IPC/RPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365098
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Reid Kleckner [Thu, 4 Jul 2019 00:03:30 +0000 (00:03 +0000)]
Revert [ThinLTO] Optimize writeonly globals out
This reverts r365040 (git commit
5cacb914758c7f436b47c8362100f10cef14bbc4)
Speculatively reverting, since this appears to have broken check-lld on
Linux. Partial analysis in https://crbug.com/981168.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365097
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Derek Schuff [Wed, 3 Jul 2019 23:54:06 +0000 (23:54 +0000)]
[WebAssembly] Enable IndirectBrExpandPass
Wasm doesn't have a direct way to lower indirectbr, so hook up the
IndirectBrExpandPass to lower indirectbr into a switch.
Fixes PR42498
Reviewers: aheejin
Differential Revision: https://reviews.llvm.org/D64161
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365096
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Matt Arsenault [Wed, 3 Jul 2019 23:32:29 +0000 (23:32 +0000)]
AMDGPU: Add pass to lower SGPR spills
This is split out from my patches to split register allocation into a
separate SGPR and VGPR phase, and has some parts that aren't yet used
(like maintaining LiveIntervals).
This simplifies making the frame pointer register callee saved. As it
is now, the code to determine callee saves needs to predict all the
possible SGPR spills and how many callee saved VGPRs are needed. By
handling this before PrologEpilogInserter, it's possible to just check
the spill objects that already exist.
Change-Id: I29e6df4034afcf949e06f8ef44206acb94696f04
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365095
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Eli Friedman [Wed, 3 Jul 2019 23:12:39 +0000 (23:12 +0000)]
[JumpThreading] Fix threading with unusual PHI nodes.
If the block being cloned contains a PHI node, in general, we need to
clone that PHI node, even though it's trivial. If the operand of the PHI
is an instruction in the block being cloned, the correct value for the
operand doesn't exist until SSAUpdater constructs it.
We usually don't hit this issue because we try to avoid threading across
loop headers, but it's possible to hit this in some cases involving
irreducible CFGs. I added a flag to allow threading across loop headers
to make the testcase easier to understand.
Thanks to Brian Rzycki for reducing the testcase.
Fixes https://bugs.llvm.org/show_bug.cgi?id=42085.
Differential Revision: https://reviews.llvm.org/D63913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365094
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Matt Arsenault [Wed, 3 Jul 2019 23:08:06 +0000 (23:08 +0000)]
GlobalISel: Fix widenScalar for pointer typed G_MERGE_VALUES
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365093
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Francis Visoiu Mistrih [Wed, 3 Jul 2019 22:40:07 +0000 (22:40 +0000)]
[Bitcode] Move Bitstream to a separate library
This moves Bitcode/Bitstream*, Bitcode/BitCodes.h to Bitstream/.
This is needed to avoid a circular dependency when using the bitstream
code for parsing optimization remarks.
Since Bitcode uses Core for the IR part:
libLLVMRemarks -> Bitcode -> Core
and Core uses libLLVMRemarks to generate remarks (see
IR/RemarkStreamer.cpp):
Core -> libLLVMRemarks
we need to separate the Bitstream and Bitcode part.
For clang-doc, it seems that it doesn't need the whole bitcode layer, so
I updated the CMake to only use the bitstream part.
Differential Revision: https://reviews.llvm.org/D63899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365091
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Guanzhong Chen [Wed, 3 Jul 2019 22:11:14 +0000 (22:11 +0000)]
[WebAssembly][NFC] simplify SjLj inline assembly test
Summary:
Per feedback in D64115, simplify the test.
`hidden` is left in though, because every test in the file has it.
Reviewers: aheejin, tlively
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365089
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Thomas Lively [Wed, 3 Jul 2019 22:04:54 +0000 (22:04 +0000)]
[WebAssembly] Add option to emit passive segments
Summary:
Adds `--passive-segments` and `--active-segments` flags to control
what kind of segments are emitted. For now the default is always
to emit active segments so this is not a breaking change, but in
the future the default will be changed to passive segments when
shared memory is requested and active segments otherwise. When
passive segments are emitted, corresponding memory.init and
data.drop instructions are emitted in a `__wasm_init_memory`
function that is automatically called at the beginning of
`__wasm_call_ctors`.
Reviewers: sbc100, aheejin, dschuff
Subscribers: azakai, dschuff, jgravelle-google, sunfish, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365088
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Matt Arsenault [Wed, 3 Jul 2019 21:34:34 +0000 (21:34 +0000)]
Revert "[AMDGPU] Kernel arg metadata: added support for "__hip_texture" type."
This reverts commit r365073.
This is crashing, and is improperly relying on IR type names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365087
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JF Bastien [Wed, 3 Jul 2019 20:47:53 +0000 (20:47 +0000)]
Revert "[llvm-ar][test] Add to MRI test coverage"
This reverts commit
250015bacf7f255abcfb646fb8b6b56ce8be7e01.
r365039 was re-commit of D63197 and failed on Mac. Reid XFAIL'd it, but I'd rather jsut revert and have it fixed properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365084
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Evgeniy Stepanov [Wed, 3 Jul 2019 20:19:14 +0000 (20:19 +0000)]
Teach ValueTracking that aarch64.irg result aliases its input.
Reviewers: javed.absar, olista01
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64103
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365079
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Florian Hahn [Wed, 3 Jul 2019 20:15:14 +0000 (20:15 +0000)]
[LoopBase] Strengthen isLoopExiting by requiring that BB must be inside the loop.
Currently isLoopExiting returns true for BBs that are not part of the
loop. To avoid hiding subtle bugs, this patch adds an assertion to make
sure the passed BB is inside the loop
Reviewers: reames, efriedma, hfinkel, arsenm, nhaehnle
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D63952
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365077
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Reid Kleckner [Wed, 3 Jul 2019 20:14:54 +0000 (20:14 +0000)]
Try to XFAIL mri-utf8.test on Mac
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365076
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Philip Reames [Wed, 3 Jul 2019 20:03:46 +0000 (20:03 +0000)]
[LFTR] Use SCEVExpander for the pointer limit case instead of manual IR gen
As noted in the test change, this is not trivially NFC, but all of the changes in output are cases where the SCEVExpander form is more canonical/optimal than the hand generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365075
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Konstantin Pyzhov [Wed, 3 Jul 2019 19:11:35 +0000 (19:11 +0000)]
[AMDGPU] Kernel arg metadata: added support for "__hip_texture" type.
Summary:
Hip texture type is equivalent to OpenCL image. So, we need to set the Image type for kernel arguments with __hip_texture type.
Differential revision: https://reviews.llvm.org/D63850
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365073
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Philip Reames [Wed, 3 Jul 2019 19:08:43 +0000 (19:08 +0000)]
[LFTR] Remove a stray variable shadow *of the same value* [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365072
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Philip Reames [Wed, 3 Jul 2019 19:03:37 +0000 (19:03 +0000)]
[LFTR] Style and comment changes to clarify the narrow vs wide bitwidth evaluation behavior [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365071
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Philip Reames [Wed, 3 Jul 2019 18:41:03 +0000 (18:41 +0000)]
[LFTR] Sink the decision not use truncate scheme for constants into genLoopLimit [NFC]
We might as well just evaluate the constants using SCEV, and having the cases grouped makes the logic slightly easier to read anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365070
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Jessica Paquette [Wed, 3 Jul 2019 18:30:01 +0000 (18:30 +0000)]
Fix precedence in assert from r364961
Precedence was wrong in an assert added in r364961. Add braces around the
assertion condition to make it right.
See: https://reviews.llvm.org/D64084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365069
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Philip Reames [Wed, 3 Jul 2019 18:24:06 +0000 (18:24 +0000)]
[LFTR] Remove falsely generalized (dead) code [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365067
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Philip Reames [Wed, 3 Jul 2019 18:18:36 +0000 (18:18 +0000)]
[LFTR] Hoist extend expressions outside of loops w/o waiting for LICM
The motivation for this is two fold:
1) Make the output (and thus tests) a bit more readable to a human trying to understand the result of the transform
2) Reduce spurious diffs in a potential future change to restructure all of this logic to use SCEVExpander (which hoists by default)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365066
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Alex Lorenz [Wed, 3 Jul 2019 17:46:30 +0000 (17:46 +0000)]
[macCatalyst] Print out macCatalyst in llvm-objdump for the platform
'macCatalyst' is more readable than 'maccatalyst'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365064
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Jessica Paquette [Wed, 3 Jul 2019 17:46:23 +0000 (17:46 +0000)]
[GlobalISel][AArch64] Use getConstantVRegValWithLookThrough for selectArithImmed
Instead of just stopping to see if we have a G_CONSTANT, instead, look through
G_TRUNCs, G_SEXTs, and G_ZEXTs.
This gives an average ~1.3% code size improvement on CINT2000 at -O3.
Differential Revision: https://reviews.llvm.org/D64108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365063
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Robert Lougher [Wed, 3 Jul 2019 17:45:24 +0000 (17:45 +0000)]
[X86] Update test; NFC
This updates pr38743.ll after D62605.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365062
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Robert Lougher [Wed, 3 Jul 2019 17:43:55 +0000 (17:43 +0000)]
[X86] Avoid SFB - Skip meta instructions
This patch generalizes the fix in D61680 to ignore all meta instructions,
not just debug info.
Patch by Chris Dawson.
Differential Revision: https://reviews.llvm.org/D62605
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365061
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Joel E. Denny [Wed, 3 Jul 2019 17:31:43 +0000 (17:31 +0000)]
[Bitcode] Update CHECK-DAG usage in tests
This patch adjusts tests not to depend on deprecated FileCheck
behavior that permits overlapping matches within a block of
`CHECK-DAG` directives:
1. `thinlto-function-summary-originalnames.ll`: The directive with the
pattern `<COMBINED` is surely intended to match `<COMBINED ` (note the
trailing space), but it instead matches
`<COMBINED_GLOBALVAR_INIT_REFS`, for which there is a separate
directive. With the deprecated behavior, both directives match the
latter text and neither match the former text. I've adjusted the
former directive so it matches only the former text.
2. `thinlto-summary-local-5.0.ll`: Two directives have identical
patterns when they were clearly meant to have different patterns.
3. `upgrade-pointer-address-space.ll`: There are three identical
directives but only two occurrences of the matching text. With the
deprecated behavior, they always match exactly the same text, so the
behavior can't have been useful. I removed one of the directives and
converted the other two from `CHECK-DAG` to `CHECK`.
Reviewed By: probinson, aprantl
Differential Revision: https://reviews.llvm.org/D64036
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365060
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Francis Visoiu Mistrih [Wed, 3 Jul 2019 17:16:45 +0000 (17:16 +0000)]
[CodeGen] Make branch funnels pass the machine verifier
We previously marked all the tests with branch funnels as
`-verify-machineinstrs=0`.
This is an attempt to fix it.
1) `ICALL_BRANCH_FUNNEL` has no defs. Mark it as `let OutOperandList =
(outs)`
2) After that we hit an assert: ``` Assertion failed: (Op.getValueType()
!= MVT::Other && Op.getValueType() != MVT::Glue && "Chain and glue
operands should occur at end of operand list!"), function AddOperand,
file
/Users/francisvm/llvm/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp,
line 461. ```
The chain operand was added at the beginning of the operand list. Move
that to the end.
3) After that we hit another verifier issue in the pseudo expansion
where the registers used in the cmps and jmps are not added to the
livein lists. Add the `EFLAGS` to all the new MBBs that we create.
PR39436
Differential Review: https://reviews.llvm.org/D54155
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365058
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Simon Pilgrim [Wed, 3 Jul 2019 17:06:59 +0000 (17:06 +0000)]
[X86] ComputeNumSignBitsForTargetNode - add target shuffle support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365057
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Roman Lebedev [Wed, 3 Jul 2019 16:48:53 +0000 (16:48 +0000)]
[NFC][InstCombine] onehot_merge.ll: add last few tests in the state they regress to in D62818
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365056
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Sanjay Patel [Wed, 3 Jul 2019 16:46:14 +0000 (16:46 +0000)]
[SLP] add tests for bitcasted vector pointer load; NFC
I'm not sure if this falls within the scope of SLP,
but we could create vector loads for some of these
patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365055
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Amaury Sechet [Wed, 3 Jul 2019 16:34:36 +0000 (16:34 +0000)]
Use getAllOnesConstants instead of -1 in DAGCombiner. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365054
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Philip Reames [Wed, 3 Jul 2019 16:34:08 +0000 (16:34 +0000)]
[SCEV] Preserve flags on add/muls in getSCEVATScope
We haven't changed the set of users, just specialized an operand for those users. Given that, the previous wrap flags must still be correct.
Sorry for the lack of test case. Noticed this while working on something else, and haven't figured out to exercise this standalone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365053
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Amaury Sechet [Wed, 3 Jul 2019 16:15:59 +0000 (16:15 +0000)]
[DAGCombine] More diamong carry pattern optimization.
Summary:
This diff improve the capability of DAGCOmbine to generate linear carries propagation in presence of a diamond pattern. It is now able to match a large variety of different patterns rather than some hardcoded one.
Arguably, the codegen in test cases is not better, but this is to be expected. The goal of this transformation is more about canonicalisation than actual optimisation.
Reviewers: hfinkel, RKSimon, craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D57302
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365051
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Simon Pilgrim [Wed, 3 Jul 2019 15:46:08 +0000 (15:46 +0000)]
[X86][AVX] combineX86ShufflesRecursively - peek through extract_subvector
If we have more then 2 shuffle ops to combine, try to use combineX86ShuffleChainWithExtract to see if some are from the same super vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365050
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Teresa Johnson [Wed, 3 Jul 2019 15:12:38 +0000 (15:12 +0000)]
[ThinLTO] Fix gcc warnings from commit
Remove an unnecessary const from an Optional return type introduced
in r364960 that gcc 7.4.0 warns about. It is unnecessary and possibly
incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365047
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Sam Parker [Wed, 3 Jul 2019 14:39:23 +0000 (14:39 +0000)]
[ARM] Fix for NDEBUG builds
Fix unused variable warning as well as a nonsense assert.
Differential Revision: https://reviews.llvm.org/D63816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365046
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Simon Pilgrim [Wed, 3 Jul 2019 14:34:16 +0000 (14:34 +0000)]
[X86][AVX] Combine vpermi(bitcast(x)) -> bitcast(vpermi(x))
iff the number of elements doesn't change.
This gets around an issue with combineX86ShuffleChain not being able to hint which domain is preferred for shuffles that can be done with either.
Fixes regression introduced in rL365041
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365044
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James Molloy [Wed, 3 Jul 2019 14:33:29 +0000 (14:33 +0000)]
[SelectionDAG] Propagate alias metadata to target intrinsic nodes
When a target intrinsic has been determined to touch memory, we construct a MachineMemOperand during SDAG construction. In this case, we should propagate AAMDNodes metadata to the MachineMemOperand where available.
Differential revision: https://reviews.llvm.org/D64131
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365043
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James Henderson [Wed, 3 Jul 2019 14:21:48 +0000 (14:21 +0000)]
[docs][llvm-objcopy] Write documentation for llvm-objcopy
This patch addresses https://bugs.llvm.org/show_bug.cgi?id=42183 by replacing
the stub markdown doc for llvm-objcopy with a full one describing the current
options available in llvm-objcopy.
Reviewed by: jakehehrlich, MaskRay
Differential Revision: https://reviews.llvm.org/D63820
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365042
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Simon Pilgrim [Wed, 3 Jul 2019 14:17:21 +0000 (14:17 +0000)]
[X86][AVX] combineX86ShuffleChainWithExtract - add number of non-zero extract_subvectors to the combine depth
This better accounts for the cost/benefit of removing extract_subvectors from the shuffle and will be more useful in future patches.
The vpermq predicate regression will be fixed shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365041
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Eugene Leviant [Wed, 3 Jul 2019 14:14:52 +0000 (14:14 +0000)]
[ThinLTO] Optimize writeonly globals out
Differential revision: https://reviews.llvm.org/D63444
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365040
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Owen Reynolds [Wed, 3 Jul 2019 13:47:29 +0000 (13:47 +0000)]
[llvm-ar][test] Add to MRI test coverage
This reapplies 363232 that was reverted due to a buildbot test failure, this build bot has now been fixed.
Differential Revision: https://reviews.llvm.org/D63197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365039
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Simon Atanasyan [Wed, 3 Jul 2019 12:28:05 +0000 (12:28 +0000)]
[mips] Mark general scheduling model as complete
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365034
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Simon Atanasyan [Wed, 3 Jul 2019 12:27:58 +0000 (12:27 +0000)]
[mips] Add missing atomic instructions to general scheduling definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365033
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Simon Atanasyan [Wed, 3 Jul 2019 12:27:51 +0000 (12:27 +0000)]
[mips] Add missing microMIPS instructions to general scheduling definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365032
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Simon Pilgrim [Wed, 3 Jul 2019 11:23:27 +0000 (11:23 +0000)]
[X86][SSE] lowerUINT_TO_FP_v2i32 - explicitly cast half word to double
Fixes MSVC analyzer extension->double warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365027
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Simon Pilgrim [Wed, 3 Jul 2019 10:59:52 +0000 (10:59 +0000)]
[X86][SSE] LowerINSERT_VECTOR_ELT - ensure insertion index correctness. NFCI.
Assert that the insertion index is in range and use uint64_t for the index to fix MSVC/cppcheck truncation warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365025
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Simon Pilgrim [Wed, 3 Jul 2019 10:47:33 +0000 (10:47 +0000)]
[X86][SSE] LowerScalarImmediateShift - ensure shift amount correctness. NFCI.
Assert that the shift amount is in range and create vXi8 shift masks in a way that doesn't cause MSVC/cppcheck shift result is truncated then extended warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365024
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Simon Atanasyan [Wed, 3 Jul 2019 10:33:16 +0000 (10:33 +0000)]
[mips] Add SIGRIE,GINVI,GINVT to general scheduling definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365023
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Simon Atanasyan [Wed, 3 Jul 2019 10:33:09 +0000 (10:33 +0000)]
[mips] Add missing mips16 instructions to general scheduling definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365022
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Simon Atanasyan [Wed, 3 Jul 2019 10:33:01 +0000 (10:33 +0000)]
[mips] Add missing MSA and ASE instructions to general scheduling definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365021
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Simon Atanasyan [Wed, 3 Jul 2019 10:32:54 +0000 (10:32 +0000)]
[mips] Replace some itineraries by instructions in the general scheduling definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365020
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Simon Pilgrim [Wed, 3 Jul 2019 10:22:08 +0000 (10:22 +0000)]
Fix uninitialized variable warnings. NFCI.
Both MSVC and cppcheck don't like the fact that the variables are initialized via references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365018
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Simon Pilgrim [Wed, 3 Jul 2019 10:04:16 +0000 (10:04 +0000)]
[X86] LowerFunnelShift - use modulo constant shift amount.
This avoids the use of getZExtValue and uses the modulo shift amount which is whats expected for funnel shifts anyhow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365016
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Oliver Stannard [Wed, 3 Jul 2019 09:58:52 +0000 (09:58 +0000)]
[ARM] Thumb2: favor R4-R7 over R12/LR in allocation order when opt for minsize
For Thumb2, we prefer low regs (costPerUse = 0) to allow narrow
encoding. However, current allocation order is like:
R0-R3, R12, LR, R4-R11
As a result, a lot of instructs that use R12/LR will be wide instrs.
This patch changes the allocation order to:
R0-R7, R12, LR, R8-R11
for thumb2 and -Osize.
In most cases, there is no extra push/pop instrs as they will be folded
into existing ones. There might be slight performance impact due to more
stack usage, so we only enable it when opt for min size.
https://reviews.llvm.org/D30324
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365014
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Sven van Haastregt [Wed, 3 Jul 2019 09:57:59 +0000 (09:57 +0000)]
Remove some autoconf references from docs and comments
The autoconf build system support has been removed a while ago, remove
some outdated references.
Differential Revision: https://reviews.llvm.org/D63608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365013
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Roman Lebedev [Wed, 3 Jul 2019 09:41:50 +0000 (09:41 +0000)]
[InstCombine] Y - ~X --> X + Y + 1 fold (PR42457)
Summary:
I *think* we'd want this new variant, because we obviously
have better handling for `add` as compared to `sub`/`not`.
https://rise4fun.com/Alive/WMn
Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=42457 | PR42457 ]]
Reviewers: spatel, nikic, huihuiz, efriedma
Reviewed By: spatel
Subscribers: RKSimon, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365011
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Roman Lebedev [Wed, 3 Jul 2019 09:41:35 +0000 (09:41 +0000)]
[Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)
Summary:
This is the backend part of [[ https://bugs.llvm.org/show_bug.cgi?id=42457 | PR42457 ]].
In middle-end, we'd want to prefer the form with two adds - D63992,
but as this diff shows, not every target will prefer that pattern.
Out of 4 targets for which i added tests all seem to be ok with inc-of-add for scalars,
but only X86 prefer that same pattern for vectors.
Here i'm adding a new TLI hook, always defaulting to the inc-of-add,
but adding AArch64,ARM,PowerPC overrides to prefer inc-of-add only for scalars.
Reviewers: spatel, RKSimon, efriedma, t.p.northover, hfinkel
Reviewed By: efriedma
Subscribers: nemanjai, javed.absar, kristof.beyls, kbarton, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365010
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Eugene Leviant [Wed, 3 Jul 2019 09:36:32 +0000 (09:36 +0000)]
[SCEV][LSR] Prevent using undefined value in binops
On some occasions ReuseOrCreateCast may convert previously
expanded value to undefined. That value may be passed by
SCEVExpander as an argument to InsertBinop making IV chain
undefined.
Differential revision: https://reviews.llvm.org/D63928
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365009
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Alexander Potapenko [Wed, 3 Jul 2019 09:28:50 +0000 (09:28 +0000)]
MSan: handle callbr instructions
Summary:
Handling callbr is very similar to handling an inline assembly call:
MSan must checks the instruction's inputs.
callbr doesn't (yet) have outputs, so there's nothing to unpoison,
and conservative assembly handling doesn't apply either.
Fixes PR42479.
Reviewers: eugenis
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365008
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Serguei Katkov [Wed, 3 Jul 2019 05:59:23 +0000 (05:59 +0000)]
[LoopPeel] Re-factor llvm::peelLoop method. NFC.
Extract code dealing with branch weights in separate functions.
Reviewers: reames, mkuper, iajbar, fhahn
Reviewed By: reames, fhahn
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D63917
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365002
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Jordan Rupprecht [Wed, 3 Jul 2019 04:01:51 +0000 (04:01 +0000)]
Revert [InlineCost] cleanup calculations of Cost and Threshold
This reverts r364422 (git commit
1a3dc761860d620ac8ed7e32a4285952142f780b)
The inlining cost calculation is incorrect, leading to stack overflow due to large stack frames from heavy inlining.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365000
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Teresa Johnson [Wed, 3 Jul 2019 02:14:47 +0000 (02:14 +0000)]
[ThinLTO] Reenable test with workaround for known failure
Reenable the testing disabled in r364978 with the same workaround used
for this failure in the cfi-devirt.ll test. The known issue is PR39436,
and the workaround is to add -verify-machineinstrs=0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364997
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Michael Liao [Wed, 3 Jul 2019 02:00:21 +0000 (02:00 +0000)]
[AMDGPU] Enable serializing of argument info.
Summary:
- Support serialization of all arguments in machine function info. This
enables fabricating MIR tests depending on argument info.
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364995
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Amara Emerson [Wed, 3 Jul 2019 01:49:06 +0000 (01:49 +0000)]
[AArch64][GlobalISel] Overhaul legalization & isel or shifts to select immediate forms.
There are two main issues preventing us from generating immediate form shifts:
1) We have partial SelectionDAG imported support for G_ASHR and G_LSHR shift
immediate forms, but they currently don't work because the amount type is
expected to be an s64 constant, but we only legalize them to have homogenous
types.
To deal with this, first we introduce a custom legalizer to *only* custom legalize
s32 shifts which have a constant operand into a s64.
There is also an additional artifact combiner to fold zexts(g_constant) to a
larger G_CONSTANT if it's legal, a counterpart to the anyext version committed
in an earlier patch.
2) For G_SHL the importer can't cope with the pattern. For this I introduced an
early selection phase in the arm64 selector to select these forms manually
before the tablegen selector pessimizes it to a register-register variant.
Differential Revision: https://reviews.llvm.org/D63910
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364994
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Chen Zheng [Wed, 3 Jul 2019 01:49:03 +0000 (01:49 +0000)]
[PowerPC] exclude ICmpZero in LSR if icmp can be replaced in later hardware loop.
Differential Revision: https://reviews.llvm.org/D63477
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364993
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Alex Lorenz [Wed, 3 Jul 2019 01:02:43 +0000 (01:02 +0000)]
[triple] Use 'macabi' environment name for the Mac Catalyst triples
The 'macabi' environment name is preferred instead of 'maccatalyst'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364988
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Nilanjana Basu [Wed, 3 Jul 2019 00:51:49 +0000 (00:51 +0000)]
Revert Changing CodeView debug info type record representation in assembly files to make it more human-readable & editable
This reverts r364982 (git commit
2082bf28ebea76cc187b508f801122866420d9ff)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364987
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Jonas Devlieghere [Wed, 3 Jul 2019 00:45:53 +0000 (00:45 +0000)]
[VFS] Add reverse iterator to OverlayFileSystem
Add a reverse iterator to the overlay file system. This makes it
possible to take overlays from one OverlayFileSystem, and add them to
another.
Differential revision: https://reviews.llvm.org/D64113
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364986
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Guanzhong Chen [Wed, 3 Jul 2019 00:37:49 +0000 (00:37 +0000)]
[WebAssembly] Prevent inline assembly from being mangled by SjLj
Summary:
Before, inline assembly gets mangled by the SjLj transformation.
For example, in a function with setjmp/longjmp, this LLVM IR code
call void asm sideeffect "", ""()
would be transformed into
call void @__invoke_void(void ()* asm sideeffect "", "")
This is invalid, and results in the error:
Cannot take the address of an inline asm!
In this diff, we skip the transformation for inline assembly.
Reviewers: aheejin, tlively
Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64115
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364985
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Matt Arsenault [Wed, 3 Jul 2019 00:30:47 +0000 (00:30 +0000)]
CodeGen: Set hasSideEffects = 0 on BUNDLE
The BUNDLE itself should not have side effects, and this is a property
of instructions inside the bundle. The hasProperty check already
searches for any member instructions, which was pointless since it was
overridden by this bit.
Allows me to distinguish bundles that have side effects vs. do not in
a future patch. Also fixes an unnecessary scheduling barrier in the
bundle AMDGPU uses to get PC relative addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364984
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Matt Arsenault [Wed, 3 Jul 2019 00:30:44 +0000 (00:30 +0000)]
AMDGPU: Look through bundles for existing waitcnts
These aren't produced now, but will be in a future patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364983
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Nilanjana Basu [Wed, 3 Jul 2019 00:26:23 +0000 (00:26 +0000)]
Changing CodeView debug info type record representation in assembly files to make it more human-readable & editable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364982
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Alex Lorenz [Tue, 2 Jul 2019 23:47:11 +0000 (23:47 +0000)]
Add support for the 'macCatalyst' MachO platform
Mac Catalyst is a new MachO platform in macOS Catalina.
It always uses the build_version MachO load command.
Differential Revision: https://reviews.llvm.org/D64107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364981
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