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Reid Kleckner [Thu, 16 Nov 2017 00:32:19 +0000 (00:32 +0000)]
Try to fix WebAssembly build after r318352
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318355
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Craig Topper [Thu, 16 Nov 2017 00:19:59 +0000 (00:19 +0000)]
[GVNHoist] Fix a signed/unsigned comparison warning that occurs in 32-bit builds with gcc.
std::distance returns ptrdiff_t which is signed. 64-bit builds don't notice because type promotion widens the unsigned first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318354
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Rong Xu [Thu, 16 Nov 2017 00:14:05 +0000 (00:14 +0000)]
[CodeGen] Fix the branch probability assertion in r318202
Due to integer precision, we might have numerator greater than denominator in
the branch probability scaling. Add a check to prevent this from happening.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318353
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Daniel Sanders [Wed, 15 Nov 2017 23:55:44 +0000 (23:55 +0000)]
Add backend name to Target to enable runtime info to be fed back into TableGen
Summary:
Make it possible to feed runtime information back to tablegen to enable
profile-guided tablegen-eration, detection of untested tablegen definitions, etc.
Being a cross-compiler by nature, LLVM will potentially collect data for multiple
architectures (e.g. when running 'ninja check'). We therefore need a way for
TableGen to figure out what data applies to the backend it is generating at the
time. This patch achieves that by including the name of the 'def X : Target ...'
for the backend in the TargetRegistry.
Reviewers: qcolombet
Reviewed By: qcolombet
Subscribers: jholewinski, arsenm, jyknight, aditya_nandakumar, sdardis, nemanjai, ab, nhaehnle, t.p.northover, javed.absar, qcolombet, llvm-commits, fedor.sergeev
Differential Revision: https://reviews.llvm.org/D39742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318352
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Evandro Menezes [Wed, 15 Nov 2017 23:49:58 +0000 (23:49 +0000)]
[AArch64] Adjust the cost model for Exynos M1 and M2
Fix the modeling of FP stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318351
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Aditya Nandakumar [Wed, 15 Nov 2017 23:45:04 +0000 (23:45 +0000)]
[GISel][NFC]: Move getOpcodeDef from the LegalizationArtifactCombiner into GlobalISel/Utils for use elsewhere
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318350
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Sanjay Patel [Wed, 15 Nov 2017 22:19:55 +0000 (22:19 +0000)]
[InstCombine] add sub narrowing tests; NFC
This might be the root cause of PR35295:
https://bugs.llvm.org/show_bug.cgi?id=35295
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318342
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Matt Arsenault [Wed, 15 Nov 2017 21:51:43 +0000 (21:51 +0000)]
AMDGPU: Replace i64 add/sub lowering
Use VOP3 add/addc like usual.
This has some tradeoffs. Inline immediates fold
a little better, but other constants are worse off.
SIShrinkInstructions could be made smarter to handle
these cases.
This allows us to avoid selecting scalar adds where we
need to track the carry in scc and replace its users.
This makes it easier to use the carryless VALU adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318340
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Dan Gohman [Wed, 15 Nov 2017 21:38:33 +0000 (21:38 +0000)]
[WebAssembly] Update cfg-stackify.ll to remove the workaround added in r318288.
Remove -switch-peel-threshold=100 and update the expected results in test10
in cfg-stackify.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318338
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Evandro Menezes [Wed, 15 Nov 2017 21:06:22 +0000 (21:06 +0000)]
[AArch64] Refactor the loads and stores optimizer
Move remaining inline matching of instructions of some optimizations into
separate functions, like in the other optimizations. Otherwise, NFC.
Differential revision: https://reviews.llvm.org/D40090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318335
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Rafael Espindola [Wed, 15 Nov 2017 20:55:53 +0000 (20:55 +0000)]
Simplify file handling in dsymutil.
This moves the file handling out of DwarfLinker.cpp.
This fixes what is at least an oddity if not a bug. DwarfLinker.cpp
was using ToolOutputFile, which uses RemoveFileOnSignal. The issue is
that dsymutil.cpp uses that too. It is now clear from the interface
that only dsymutil.cpp is responsible for creating and deleting files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318334
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Craig Topper [Wed, 15 Nov 2017 20:42:49 +0000 (20:42 +0000)]
[X86] Add some explanatory comments to the ProcessorFeatures enum in Host.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318331
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Craig Topper [Wed, 15 Nov 2017 20:42:47 +0000 (20:42 +0000)]
[X86] Add a return to the end of a switch to prevent an accidental fallthrough in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318330
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Jake Ehrlich [Wed, 15 Nov 2017 19:13:31 +0000 (19:13 +0000)]
[llvm-objcopy] Change -O binary to respect section removal and behave like GNU objcopy
The original -O binary implementation just copied segment data from the
object and dumped it into a file. This doesn't take into account any
operations performed on objects such as section removal. GNU objcopy has
some specific behavior that we'd also like to respect. For instance
using -O binary and -j <some_section> will dump <some_section> to a
file. This change implements GNU objcopy style -O binary to as close of
an approximation as I can determine.
Differential Revision: https://reviews.llvm.org/D39713
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318324
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Sanjay Patel [Wed, 15 Nov 2017 19:12:01 +0000 (19:12 +0000)]
[InstCombine] trunc (binop X, C) --> binop (trunc X, C')
Note that one-use and shouldChangeType() are checked ahead of the switch.
Without the narrowing folds, we can produce inferior vector code as shown in PR35299:
https://bugs.llvm.org/show_bug.cgi?id=35299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318323
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Rafael Espindola [Wed, 15 Nov 2017 19:09:22 +0000 (19:09 +0000)]
Use TempFile in lto caching.
This requires a small change to TempFile: allowing a discard after a
failed keep.
With this the cache now handles signals and reuses a fd instead of
reopening the file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318322
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Sean Fertile [Wed, 15 Nov 2017 18:58:27 +0000 (18:58 +0000)]
[PowerPC] Implement mayBeEmittedAsTailCall for PPC
Implements TargetLowering callback 'mayBeEmittedAsTailCall' that enables
CodeGenPrepare to duplicate returns when they might enable a tail-call.
Differential Revision: https://reviews.llvm.org/D39777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318321
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Reid Kleckner [Wed, 15 Nov 2017 18:51:12 +0000 (18:51 +0000)]
[InstCombine] Salvage debug info during initial DCE
InstCombine salvages debug info for every instruction it erases from its
worklist, but it wasn't doing it during its initial DCE when populating
its worklist. This fixes that.
This should help improve availability of 'this' in optimized debug info
when casts are necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318320
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Sanjay Patel [Wed, 15 Nov 2017 18:09:43 +0000 (18:09 +0000)]
[InstCombine] add tests for missing trunc folds; NFC
As noted in PR35299:
https://bugs.llvm.org/show_bug.cgi?id=35299
...this is likely the root cause for a mis-vectorization transform.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318319
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Vedant Kumar [Wed, 15 Nov 2017 18:05:19 +0000 (18:05 +0000)]
[docs] Mention opt -metarenamer in the bugpoint docs
Thanks to arsenm and davide for the suggestion!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318318
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Evandro Menezes [Wed, 15 Nov 2017 17:39:37 +0000 (17:39 +0000)]
[AArch64] Adjust the cost model for Exynos M1 and M2
Fix the modeling of loads and stores using the pre or post indexed
addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318312
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Simon Pilgrim [Wed, 15 Nov 2017 17:11:24 +0000 (17:11 +0000)]
[X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class
Some CPUs are already overriding these sign extension instructions but we should be able to use the WriteALU schedule class by default.
Differential Revision: https://reviews.llvm.org/D39899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318308
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Adam Nemet [Wed, 15 Nov 2017 17:04:53 +0000 (17:04 +0000)]
[SLP] Added more missed optimization remarks
Summary:
Added more remarks to SLP pass, in particular "missed" optimization remarks.
Also proposed several tests for new functionality.
Patch by Vladimir Miloserdov!
For reference you may look at: https://reviews.llvm.org/rL302811
Reviewers: anemet, fhahn
Reviewed By: anemet
Subscribers: javed.absar, lattner, petecoup, yakush, llvm-commits
Differential Revision: https://reviews.llvm.org/D38367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318307
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Sean Fertile [Wed, 15 Nov 2017 16:53:41 +0000 (16:53 +0000)]
[PowerPC] Split out the tailcall calling convention checks. NFC.
Move the calling convention checks for tail-call eligibility for the 64-bit
SysV ABI into a separate function. This is so that it can be shared with
'mayBeEmittedAsTailCall' in a subsequent change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318305
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Sanjay Patel [Wed, 15 Nov 2017 16:37:30 +0000 (16:37 +0000)]
[PassManager, SimplifyCFG] add test for PR34603 / D38566; NFC
This is a recommit of r316908 which was reverted by r317444.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318300
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Sanjay Patel [Wed, 15 Nov 2017 16:33:11 +0000 (16:33 +0000)]
[(new) Pass Manager] instantiate SimplifyCFG with the same options as the old PM
This is a recommit of r316869 which was speculatively reverted with r317444 and
subsequently shown to not be the cause of PR35210. That crash should be fixed
after r318237.
Original commit message:
The old PM sets the options of what used to be known as "latesimplifycfg" on the
instantiation after the vectorizers have run, so that's what we'redoing here.
FWIW, there's a later SimplifyCFGPass instantiation in both PMs where we do not
set the "late" options. I'm not sure if that's intentional or not.
Differential Revision: https://reviews.llvm.org/D39407
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318299
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Sanjay Patel [Wed, 15 Nov 2017 16:19:17 +0000 (16:19 +0000)]
[Reassociate] simplify code; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318298
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Sander de Smalen [Wed, 15 Nov 2017 15:44:43 +0000 (15:44 +0000)]
[AArch64][SVE] Asm: Report SVE parsing diagnostics only once
Summary:
Prevent an issue where a diagnostic is reported multiple times by bailing out with a ParseFail if an invalid SVE register element qualifier/suffix is specified, for example:
<stdin>:10:18: error: invalid sve vector kind qualifier
add z20.h, z2.h, z31.x
^
<stdin>:10:18: error: invalid sve vector kind qualifier
add z20.h, z2.h, z31.x
...
<stdin>:10:18: error: invalid sve vector kind qualifier
add z20.h, z2.h, z31.x
^
Reviewers: fhahn, rengolin
Reviewed By: rengolin
Subscribers: aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D39894
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318297
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Petar Jovanovic [Wed, 15 Nov 2017 15:24:04 +0000 (15:24 +0000)]
[mips] Improve genConstMult() to work with arbitrary precision
APInt is now used instead of uint64_t in function genConstMult() allowing
multiplication optimizations with constants of arbitrary length.
Patch by Milos Stojanovic.
Differential Revision: https://reviews.llvm.org/D38130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318296
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Igor Laevsky [Wed, 15 Nov 2017 15:07:37 +0000 (15:07 +0000)]
[llvm-opt-fuzzer] Add opt fuzzer to the test-depends list.
This should help with the buildbot failures after rL318293.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318295
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Igor Laevsky [Wed, 15 Nov 2017 13:35:42 +0000 (13:35 +0000)]
[llvm-opt-fuzzer] Only run tests for the x86 target.
This fixes build bot failures after rL318293.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318294
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Igor Laevsky [Wed, 15 Nov 2017 12:36:57 +0000 (12:36 +0000)]
[llvm-opt-fuzzer] NFC. Add sanity tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318293
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Momchil Velikov [Wed, 15 Nov 2017 12:02:55 +0000 (12:02 +0000)]
[ARM] Split Arm jump table branch into i12 and rs suffixed versions
This is a refactoring/cleanup of Arm `addrmode2` operand class. The patch
removes it completely.
Differential Revision: https://reviews.llvm.org/D39832
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318291
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Jonas Devlieghere [Wed, 15 Nov 2017 10:57:05 +0000 (10:57 +0000)]
[DebugInfo] Fix potential CU mismatch for SubprogramScopeDIEs.
In constructAbstractSubprogramScopeDIE there can be a potential mismatch
between `this` and the CU of ContextDIE when a scope is shared between
two DISubprograms belonging to a different CU. In that case, `this` is
the CU that was specified in the IR, but the CU of ContextDIE is that of
the first subprogram that was emitted. This patch fixes the mismatch by
looking up the CU of ContextDIE, and switching to use that.
This fixes PR35212 (https://bugs.llvm.org/show_bug.cgi?id=35212)
Patch by Philip Craig!
Differential revision: https://reviews.llvm.org/D39981
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318289
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Ilya Biryukov [Wed, 15 Nov 2017 10:50:43 +0000 (10:50 +0000)]
Workaround CodeGen/WebAssembly/cfg-stackify.ll failure after r318202
By disabling the introduced optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318288
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Mikael Holmen [Wed, 15 Nov 2017 07:46:48 +0000 (07:46 +0000)]
[Lint] Don't warn about passing alloca'd value to tail call if using byval
Summary:
This fixes PR35241.
When using byval, the data is effectively copied as part of the call
anyway, so the pointer returned by the alloca will not be leaked to the
callee and thus there is no reason to issue a warning.
Reviewers: rnk
Reviewed By: rnk
Subscribers: Ka-Ka, llvm-commits
Differential Revision: https://reviews.llvm.org/D40009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318279
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Craig Topper [Wed, 15 Nov 2017 07:46:43 +0000 (07:46 +0000)]
[X86] Redefine the 128-bit version of VPGATHERQD and VGATHERQPS to use a VK2 mask instead of a VK4 mask.
This allows us to remove extra extend creation during lowering and more accurately reflects the semantics of the instruction.
While there add an extra output VT to X86 masked gather node to better match the isel pattern predicate. Currently we're exploiting the fact that the isel table doesn't count how many output results a node actually has if the result type of any can be inferred from the first result and the type constraints defined in tablegen. I think we might ultimately want to lower all MGATHER/MSCATTER to an X86ISD node with the extra mask result and stop relying on this hole in the isel checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318278
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NAKAMURA Takumi [Wed, 15 Nov 2017 07:34:35 +0000 (07:34 +0000)]
GISelWorkList.h: Fix -fmodules build in rL318210.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318275
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NAKAMURA Takumi [Wed, 15 Nov 2017 06:46:58 +0000 (06:46 +0000)]
Fix llvm/test/Transforms/LoopRotate/pr35210.ll in rL318237, it uses debug options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318273
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Fangrui Song [Wed, 15 Nov 2017 06:17:32 +0000 (06:17 +0000)]
NFC Remove default argument of DataLayout::getPointerABIAlignment
Differential Revision: https://reviews.llvm.org/D40005
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318272
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Craig Topper [Wed, 15 Nov 2017 06:02:43 +0000 (06:02 +0000)]
[X86] Add getHostCPUName support for the Gemini Lake model number which also uses Goldmont.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318271
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Craig Topper [Wed, 15 Nov 2017 06:02:42 +0000 (06:02 +0000)]
[X86] Add getHostCPUName support for cannonlake.
This adds an explicit model number check and fallback path to the unknown family 6 detection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318270
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Craig Topper [Wed, 15 Nov 2017 05:23:02 +0000 (05:23 +0000)]
[InstCombine] Simplify binops that are only used by a select and are fed by a select with the same condition.
Summary:
This patch optimizes a binop sandwiched between 2 selects with the same condition. Since we know its only used by the select we can propagate the appropriate input value from the earlier select.
As I'm writing this I realize I may need to avoid doing this for division in case the select was protecting a divide by zero?
Reviewers: spatel, majnemer
Reviewed By: majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39999
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318267
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Hiroshi Inoue [Wed, 15 Nov 2017 04:23:26 +0000 (04:23 +0000)]
[PowerPC] fix up in redundant compare elimination
This patch fixes a potential problem in my previous commit (https://reviews.llvm.org/rL312514) by introducing an additional check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318266
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Vedant Kumar [Wed, 15 Nov 2017 02:58:45 +0000 (02:58 +0000)]
[docs] Document a way to simplify names in bugpoint output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318257
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Matt Arsenault [Wed, 15 Nov 2017 01:34:06 +0000 (01:34 +0000)]
AMDGPU: Add separate definitions for DS insts without m0 use
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318246
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Craig Topper [Wed, 15 Nov 2017 01:01:50 +0000 (01:01 +0000)]
[X86] Correct the spelling of pentiumpro in X86TargetParser.def
Thanks to Erich Keane for spotting this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318243
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Matt Arsenault [Wed, 15 Nov 2017 00:45:43 +0000 (00:45 +0000)]
AMDGPU: Don't use MUBUF vaddr if address may overflow
Effectively revert r263964. Before we would not
allow this if vaddr was not known to be positive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318240
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Hans Wennborg [Wed, 15 Nov 2017 00:38:13 +0000 (00:38 +0000)]
Revert r318193 "[SLPVectorizer] Failure to beneficially vectorize 'copyable' elements in integer binary ops."
It crashes building sqlite; see reply on the llvm-commits thread.
> [SLPVectorizer] Failure to beneficially vectorize 'copyable' elements in integer binary ops.
>
> Patch tries to improve vectorization of the following code:
>
> void add1(int * __restrict dst, const int * __restrict src) {
> *dst++ = *src++;
> *dst++ = *src++ + 1;
> *dst++ = *src++ + 2;
> *dst++ = *src++ + 3;
> }
> Allows to vectorize even if the very first operation is not a binary add, but just a load.
>
> Fixed issues related to previous commit.
>
> Reviewers: spatel, mzolotukhin, mkuper, hfinkel, RKSimon, filcab, ABataev
>
> Reviewed By: ABataev, RKSimon
>
> Subscribers: llvm-commits, RKSimon
>
> Differential Revision: https://reviews.llvm.org/D28907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318239
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Mitch Phillips [Wed, 15 Nov 2017 00:35:26 +0000 (00:35 +0000)]
[cfi-verify] Validate there are no register clobbers between CFI-check and instruction execution.
Summary:
This patch adds another failure mode for `validateCFIProtection(..)`, wherein any register that affects the indirect control flow instruction is clobbered to between the CFI-check and the instruction's execution.
Also includes a modification to make MCInstrDesc::hasDefOfPhysReg public.
Reviewers: vlad.tsyrklevich
Reviewed By: vlad.tsyrklevich
Subscribers: llvm-commits, pcc, kcc
Differential Revision: https://reviews.llvm.org/D39820
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318238
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Craig Topper [Wed, 15 Nov 2017 00:22:42 +0000 (00:22 +0000)]
[LoopRotate] processLoop should return true even if it just simplified the loop latch without making any other changes
Simplifying a loop latch changes the IR and we need to make sure the pass manager knows to invalidate analysis passes if that happened.
PR35210 discovered a case where we failed to invalidate the post dominator tree after this simplification because we no changes other than simplifying the loop latch.
Fixes PR35210.
Differential Revision: https://reviews.llvm.org/D40035
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318237
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Evgeniy Stepanov [Wed, 15 Nov 2017 00:11:51 +0000 (00:11 +0000)]
[asan] Prevent rematerialization of &__asan_shadow.
Summary:
In the mode when ASan shadow base is computed as the address of an
external global (__asan_shadow, currently on android/arm32 only),
regalloc prefers to rematerialize this value to save register spills.
Even in -Os. On arm32 it is rather expensive (2 loads + 1 constant
pool entry).
This changes adds an inline asm in the function prologue to suppress
this behavior. It reduces AsanTest binary size by 7%.
Reviewers: pcc, vitalybuka
Subscribers: aemerson, kristof.beyls, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D40048
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318235
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Vedant Kumar [Tue, 14 Nov 2017 23:56:48 +0000 (23:56 +0000)]
[PGO] Bump the indexed profile format version
Differential Revision: https://reviews.llvm.org/D39447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318228
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Petr Hosek [Tue, 14 Nov 2017 23:56:05 +0000 (23:56 +0000)]
[CMake][runtimes] Don't process common options in runtimes build
This is no longer needed for any of the runtimes build and it breaks
in case we don't have the working compiler yet, e.g. when building
a compiler that uses compiler-rt and libc++ as a default runtime,
because these common options check whether these are available.
Differential Revision: https://reviews.llvm.org/D39932
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318227
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Craig Topper [Tue, 14 Nov 2017 23:54:28 +0000 (23:54 +0000)]
[X86] Fix the parameter order in the default implementation of X86_VENDOR macro in X86TargetParser.def
The default implementation doesn't do anything so the order doesn't matter, but good for cleanliness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318226
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Petr Hosek [Tue, 14 Nov 2017 23:47:20 +0000 (23:47 +0000)]
[CMake][runtimes] Set compiler as working even for default target
Even when building builtins and runtimes for the default target
we shouldn't assume that the just built compiler is already useable.
When the compiler uses compiler-rt and libc++ as the default runtime
and C++ library, it won't be usable until we finish building runtimes.
Differential Revision: https://reviews.llvm.org/D39715
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318224
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Matt Arsenault [Tue, 14 Nov 2017 23:46:42 +0000 (23:46 +0000)]
AMDGPU: Handle or in multi-use shl ptr combine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318223
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Hans Wennborg [Tue, 14 Nov 2017 23:30:28 +0000 (23:30 +0000)]
Fix switch-lower-peel-top-case.ll isel pass is not registered error
The test was doing -stop-after=isel, but that pass is actually the
AMDGPUDAGToDAGISel pass, which might not be built when targeting x86_64.
This changes the test to -stop-after=expand-isel-pseudos instead.
Follow-up to r318202.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318220
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Davide Italiano [Tue, 14 Nov 2017 23:13:38 +0000 (23:13 +0000)]
[EntryExitInstrumenter] Placate GCC, the semicolon is redundant. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318217
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Tim Renouf [Tue, 14 Nov 2017 23:05:36 +0000 (23:05 +0000)]
[AMDGPU] updated PAL metadata record keys
Summary: The ABI changed before specification was finalized.
Reviewers: kzhuravl, dstuttard
Subscribers: wdng, nhaehnle, yaxunl, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D39807
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318213
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Sanjay Patel [Tue, 14 Nov 2017 23:03:56 +0000 (23:03 +0000)]
[Reassociate] use dyn_cast instead of isa+cast; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318212
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Mitch Phillips [Tue, 14 Nov 2017 22:43:13 +0000 (22:43 +0000)]
[cfi-verify] Add DOT graph printing for GraphResult objects.
Allows users to view GraphResult objects in a DOT directed-graph format. This feature can be turned on through the --print-graphs flag.
Also enabled pretty-printing of instructions in output. Together these features make analysis of unprotected CF instructions much easier by providing a visual control flow graph.
Reviewers: pcc
Subscribers: llvm-commits, kcc, vlad.tsyrklevich
Differential Revision: https://reviews.llvm.org/D39819
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318211
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Aditya Nandakumar [Tue, 14 Nov 2017 22:42:19 +0000 (22:42 +0000)]
[GISel]: Rework legalization algorithm for better elimination of
artifacts along with DCE
Legalization Artifacts are all those insts that are there to make the
type system happy. Currently, the target needs to say all combinations
of extends and truncs are legal and there's no way of verifying that
post legalization, we only have *truly* legal instructions. This patch
changes roughly the legalization algorithm to process all illegal insts
at one go, and then process all truncs/extends that were added to
satisfy the type constraints separately trying to combine trivial cases
until they converge. This has the added benefit that, the target
legalizerinfo can only say which truncs and extends are okay and the
artifact combiner would combine away other exts and truncs.
Updated legalization algorithm to roughly the following pseudo code.
WorkList Insts, Artifacts;
collect_all_insts_and_artifacts(Insts, Artifacts);
do {
for (Inst in Insts)
legalizeInstrStep(Inst, Insts, Artifacts);
for (Artifact in Artifacts)
tryCombineArtifact(Artifact, Insts, Artifacts);
} while(!Insts.empty());
Also, wrote a simple wrapper equivalent to SetVector, except for
erasing, it avoids moving all elements over by one and instead just
nulls them out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318210
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Hans Wennborg [Tue, 14 Nov 2017 22:32:49 +0000 (22:32 +0000)]
CMake: Turn LLVM_ENABLE_LIBXML2 into a tri-state option
In addition to the current ON and OFF options, this adds the FORCE_ON
option, which causes a configuration error if libxml2 cannot be used.
Differential revision: https://reviews.llvm.org/D40050
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318209
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Simon Dardis [Tue, 14 Nov 2017 22:26:42 +0000 (22:26 +0000)]
Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."
This adjusts the tests to hopfully pacify the
llvm-clang-x86_64-expensive-checks-win buildbot.
Unlike many other instructions, these instructions have aliases which
take coprocessor registers, gpr register, accumulator (and dsp accumulator)
registers, floating point registers, floating point control registers and
coprocessor 2 data and control operands.
For the moment, these aliases are treated as pseudo instructions which are
expanded into the underlying instruction. As a result, disassembling these
instructions shows the underlying instruction and not the alias.
Reviewers: slthakur, atanasyan
Differential Revision: https://reviews.llvm.org/D35253
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318207
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Rong Xu [Tue, 14 Nov 2017 22:08:37 +0000 (22:08 +0000)]
[CodeGen] Fix the test case added in r318202
Add the -mtriple option to filter some platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318206
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Reid Kleckner [Tue, 14 Nov 2017 21:49:06 +0000 (21:49 +0000)]
Make salvageDebugInfo of casts work for dbg.declare and dbg.addr
Summary:
Instcombine (and probably other passes) sometimes want to change the
type of an alloca. To do this, they generally create a new alloca with
the desired type, create a bitcast to make the new pointer type match
the old pointer type, replace all uses with the cast, and then simplify
the casts. We already knew how to salvage dbg.value instructions when
removing casts, but we can extend it to cover dbg.addr and dbg.declare.
Fixes a debug info quality issue uncovered in Chromium in
http://crbug.com/784609
Reviewers: aprantl, vsk
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D40042
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318203
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Rong Xu [Tue, 14 Nov 2017 21:44:09 +0000 (21:44 +0000)]
[CodeGen] Peel off the dominant case in switch statement in lowering
This patch peels off the top case in switch statement into a branch if the
probability exceeds a threshold. This will help the branch prediction and
avoids the extra compares when lowering into chain of branches.
Differential Revision: http://reviews.llvm.org/D39262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318202
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Richard Smith [Tue, 14 Nov 2017 21:26:46 +0000 (21:26 +0000)]
Fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318201
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Hans Wennborg [Tue, 14 Nov 2017 21:09:45 +0000 (21:09 +0000)]
Rename CountingFunctionInserter and use for both mcount and cygprofile calls, before and after inlining
Clang implements the -finstrument-functions flag inherited from GCC, which
inserts calls to __cyg_profile_func_{enter,exit} on function entry and exit.
This is useful for getting a trace of how the functions in a program are
executed. Normally, the calls remain even if a function is inlined into another
function, but it is useful to be able to turn this off for users who are
interested in a lower-level trace, i.e. one that reflects what functions are
called post-inlining. (We use this to generate link order files for Chromium.)
LLVM already has a pass for inserting similar instrumentation calls to
mcount(), which it does after inlining. This patch renames and extends that
pass to handle calls both to mcount and the cygprofile functions, before and/or
after inlining as controlled by function attributes.
Differential Revision: https://reviews.llvm.org/D39287
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318195
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Dinar Temirbulatov [Tue, 14 Nov 2017 20:55:08 +0000 (20:55 +0000)]
[SLPVectorizer] Failure to beneficially vectorize 'copyable' elements in integer binary ops.
Patch tries to improve vectorization of the following code:
void add1(int * __restrict dst, const int * __restrict src) {
*dst++ = *src++;
*dst++ = *src++ + 1;
*dst++ = *src++ + 2;
*dst++ = *src++ + 3;
}
Allows to vectorize even if the very first operation is not a binary add, but just a load.
Fixed issues related to previous commit.
Reviewers: spatel, mzolotukhin, mkuper, hfinkel, RKSimon, filcab, ABataev
Reviewed By: ABataev, RKSimon
Subscribers: llvm-commits, RKSimon
Differential Revision: https://reviews.llvm.org/D28907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318193
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Jake Ehrlich [Tue, 14 Nov 2017 20:36:04 +0000 (20:36 +0000)]
[llvm-objcopy] Improve command line option help messages
I was being inconsistent with the way I was capitalizing help messages
for command line options. Additionally --remove-section wasn't using
value_desc even though it benefited from it.
Differential Revision: https://reviews.llvm.org/D39978
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318190
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Matt Arsenault [Tue, 14 Nov 2017 20:33:14 +0000 (20:33 +0000)]
AMDGPU: Error on stack size overflow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318189
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Ulrich Weigand [Tue, 14 Nov 2017 20:00:34 +0000 (20:00 +0000)]
[SystemZ] Do not crash when selecting an OR of two constants
In rare cases, common code will attempt to select an OR of two
constants. This confuses the logic in splitLargeImmediate,
causing an internal error during isel. Fixed by simply leaving
this case to common code to handle.
This fixes PR34859.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318187
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Evandro Menezes [Tue, 14 Nov 2017 19:59:43 +0000 (19:59 +0000)]
[AArch64] Adjust the cost model for Exynos M1 and M2
Fix the modeling of loads and stores of registers pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318186
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Martin Storsjo [Tue, 14 Nov 2017 19:58:36 +0000 (19:58 +0000)]
[llvm-strings] Add support for the -a/--all options
They don't actually change nay behaviour, as llvm-strings currently
checks the whole object without looking at individual sections anyway.
This allows using llvm-strings in a context that explicitly passes
the -a option.
Differential Revision: https://reviews.llvm.org/D40020
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318185
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Martin Storsjo [Tue, 14 Nov 2017 19:57:59 +0000 (19:57 +0000)]
[ARM, AArch64] Fix an assert message, Darwin isn't the only target supporting TLS. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318184
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Hiroshi Yamauchi [Tue, 14 Nov 2017 19:48:59 +0000 (19:48 +0000)]
Simplify irreducible loop metadata test code.
Summary:
Shorten the irreducible loop metadata test code by removing insignificant
instructions.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40043
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318182
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Easwaran Raman [Tue, 14 Nov 2017 19:31:51 +0000 (19:31 +0000)]
[CodeGenPrepare] Disable div bypass when working set size is huge.
Summary:
Bypass of slow divs based on operand values is currently disabled for
-Os. Do the same when profile summary is available and the working set
size of the application is huge. This is similar to how loop peeling is
guarded by hasHugeWorkingSetSize. In the div bypass case, the generated
extra code (and the extra branch) tendss to outweigh the benefits of the
bypass. This results in noticeable performance improvement on an
internal application.
Reviewers: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318179
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Ulrich Weigand [Tue, 14 Nov 2017 19:20:46 +0000 (19:20 +0000)]
[SystemZ] Fix invalid codegen using RISBMux on out-of-range bits
Before using the 32-bit RISBMux set of instructions we need to
verify that the input bits are actually within range of the 32-bit
instruction. This fixer PR35289.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318177
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Alex Bradbury [Tue, 14 Nov 2017 19:16:08 +0000 (19:16 +0000)]
Set hasSideEffects=0 for TargetOpcode::{CFI_INSTRUCTION,EH_LABEL,GC_LABEL,ANNOTATION_LABEL}
D37065 (committed as rL317674) explicitly set hasSideEffects for all
TargetOpcode::* instructions where it was inferred previously. This is a
follow-up to that patch, setting hasSideEffects=0 for CFI_INSTRUCTION,
EH_LABEL, GC_LABEL and ANNOTATION_LABEL. All LLVM tests pass after this
change.
This patch also modifies MachineInstr::isLabel returns true for a
TargetOpcode::ANNOTATION_LABEL, which ensures that an annotation label won't
be incorrectly considered safe to move.
Differential Revision: https://reviews.llvm.org/D39941
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318174
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Artem Belevich [Tue, 14 Nov 2017 19:14:00 +0000 (19:14 +0000)]
Mark intrinsics operating on the whole warp as IntrInaccessibleMemOnly
It's needed to model the fact that they do access data from other threads in a
warp and thus can't be CSE'd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318173
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Simon Dardis [Tue, 14 Nov 2017 19:11:45 +0000 (19:11 +0000)]
[mips] Simplify test for 5.0.1 (NFC)
Simplify testing that an emergency spill slot is used when MSA
is used so that it can be included in the 5.0.1 release.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318172
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Jake Ehrlich [Tue, 14 Nov 2017 18:50:24 +0000 (18:50 +0000)]
[llvm-objcopy] Add -strip-non-alloc option to remove all non-allocated sections
This change adds a new flag not present in GNU objcopy that we call
--strip-non-alloc.
Differential Revision: https://reviews.llvm.org/D39926
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318168
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Yaxun Liu [Tue, 14 Nov 2017 18:46:52 +0000 (18:46 +0000)]
CodeGen: Fix TargetLowering::LowerCallTo for sret value type
TargetLowering::LowerCallTo assumes that sret value type corresponds to a
pointer in default address space, which is incorrect, since sret value type
should correspond to a pointer in alloca address space, which may not
be the default address space. This causes assertion for amdgcn target
in amdgiz environment.
This patch fixes that.
Differential Revision: https://reviews.llvm.org/D39996
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318167
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Jake Ehrlich [Tue, 14 Nov 2017 18:41:47 +0000 (18:41 +0000)]
[llvm-objcopy] Support the rest of the ELF formats
We haven't been supporting anything but ELF64LE since the start. Luckily
this was always accounted for and the change is pretty trivial. B35281
requests this change for ELF32LE. This change adds support for ELF32LE,
ELF64BE, and ELF32BE with all supported features that already existed
for ELF64LE.
Differential Revision: https://reviews.llvm.org/D39977
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318166
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Mandeep Singh Grang [Tue, 14 Nov 2017 18:22:50 +0000 (18:22 +0000)]
[PredicateInfo] Stable sort ValueDFS to remove non-deterministic ordering
Summary: This fixes failure in Transforms/Util/PredicateInfo/testandor.ll uncovered by D39245.
Reviewers: dberlin
Reviewed By: dberlin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39630
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318165
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Mandeep Singh Grang [Tue, 14 Nov 2017 18:11:08 +0000 (18:11 +0000)]
[XRay] Stable sort XRayRecord to remove non-deterministic ordering
Summary:
This fixes failure in tools/llvm-xray/X86/graph-zero-latency-calls.yaml
uncovered by D39245.
Reviewers: dberris
Reviewed By: dberris
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39943
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318163
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Serge Guelton [Tue, 14 Nov 2017 18:08:05 +0000 (18:08 +0000)]
Add missing const qualifier to AttributeSet::operator==
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318162
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Adam Nemet [Tue, 14 Nov 2017 17:12:36 +0000 (17:12 +0000)]
Adjust test after r318159
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318160
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Adam Nemet [Tue, 14 Nov 2017 16:59:18 +0000 (16:59 +0000)]
[llvm-profdata] Report if profile data file is IR- or FE-level
Differential Revision: https://reviews.llvm.org/D39997
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318159
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Craig Topper [Tue, 14 Nov 2017 16:14:00 +0000 (16:14 +0000)]
[X86] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318156
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Oliver Stannard [Tue, 14 Nov 2017 15:35:15 +0000 (15:35 +0000)]
[Docs] Add tablegen backend for target opcode documentation
This is a tablegen backend to generate documentation for the opcodes that exist
for each target. For each opcode, it lists the assembly string, the names and
types of all operands, and the flags and predicates that apply to the opcode.
Differential revision: https://reviews.llvm.org/D31025
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318155
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Ilya Biryukov [Tue, 14 Nov 2017 14:26:42 +0000 (14:26 +0000)]
Use input redirection in WebAssembly/comdat.ll test.
To match how the other tests do it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318153
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Simon Pilgrim [Tue, 14 Nov 2017 14:03:29 +0000 (14:03 +0000)]
[X86][AVX] Add scheduling test for vmovntdq 256-bit store
Needs to use inline asm as domain will otherwise be changed to float (vmovntps)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318151
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Gil Rapaport [Tue, 14 Nov 2017 12:09:30 +0000 (12:09 +0000)]
[LV] Introduce VPBlendRecipe, VPWidenMemoryInstructionRecipe
This patch is part of D38676.
The patch introduces two new Recipes to handle instructions whose vectorization
involves masking. These Recipes take VPlan-level masks in D38676, but still rely
on ILV's existing createEdgeMask(), createBlockInMask() in this patch.
VPBlendRecipe handles intra-loop phi nodes, which are vectorized as a sequence
of SELECTs. Its execute() code is refactored out of ILV::widenPHIInstruction(),
which now handles only loop-header phi nodes.
VPWidenMemoryInstructionRecipe handles load/store which are to be widened
(but are not part of an Interleave Group). In this patch it simply calls
ILV::vectorizeMemoryInstruction on execute().
Differential Revision: https://reviews.llvm.org/D39068
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318149
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Tim Northover [Tue, 14 Nov 2017 11:43:54 +0000 (11:43 +0000)]
ARM: correctly update CFG when splitting BB to fix branch.
Because the block-splitting code is multi-purpose, we have to meddle with the
branches when using it to fixup a conditional branch destination. We got the
code right, but forgot to update the CFG so the verifier complained when
expensive checks were on.
Probably harmless since constant-islands comes so late, but best to fix it
anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318148
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Diana Picus [Tue, 14 Nov 2017 11:20:32 +0000 (11:20 +0000)]
[ARM GlobalISel] Remove C++ code for G_CONSTANT
Get rid of the handwritten instruction selector code for handling
G_CONSTANT. This code wasn't checking all the preconditions correctly
anyway, so it's better to leave it to TableGen, which can handle at
least some cases correctly (e.g. MOVi, MOVi16, folding into binary
operations). Also add tests to cover those cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318146
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Momchil Velikov [Tue, 14 Nov 2017 10:36:52 +0000 (10:36 +0000)]
[ARM] Fix incorrect conversion of a tail call to an ordinary call
When we emit a tail call for Armv8-M, but then discover that the caller needs to
save/restore `LR`, we convert the tail call to an ordinary one, since restoring
`LR` takes extra instructions, which may negate the benefits of the tail
call. If the callee, however, takes stack arguments, this conversion is
incorrect, since nothing has been done to pass the stack arguments.
Thus the patch reverts https://reviews.llvm.org/rL294000
Also, we improve the instruction sequence for popping `LR` in the case when we
couldn't immediately find a scratch low register, but we can use as a temporary
one of the callee-saved low registers and restore `LR` before popping other
callee-saves.
Differential Revision: https://reviews.llvm.org/D39599
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318143
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Matt Arsenault [Tue, 14 Nov 2017 06:40:00 +0000 (06:40 +0000)]
AMDGPU: Fix test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318138
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