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Tomasz Figa [Fri, 15 Jul 2016 07:53:48 +0000 (16:53 +0900)]
egl/android: Check return value of dri2_get_dri_config()
It might return NULL if specific config variant is unsupported.
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Fri, 15 Jul 2016 07:27:09 +0000 (16:27 +0900)]
i965: store reference to the context within struct brw_fence (v2)
As the spec allows for {server,client}_wait_sync to be called without
currently bound context, while our implementation requires context
pointer.
v2: Add a mutex and acquire it for the duration of
brw_fence_client_wait() and brw_fence_is_completed() as suggested
by Chad.
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Nicolas Boichat [Fri, 15 Jul 2016 08:24:20 +0000 (16:24 +0800)]
egl/dri2: dri2_make_current: Set EGL error if bindContext fails
Without this, if a configuration is, say, available only on GLES2/3, but
not on GLES1, and is rejected by the dri module's bindContext call,
eglMakeCurrent fails with error "EGL_SUCCESS".
In this patch, we set error to EGL_BAD_MATCH, which is what CTS/dEQP
dEQP-EGL.functional.surfaceless_context expect.
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Tomasz Figa [Wed, 13 Jul 2016 03:33:24 +0000 (11:33 +0800)]
egl/android: Remove unused variables
There are some unused variables left after previous clean-ups triggering
compiler warnings. Let's remove them.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Tomasz Figa [Wed, 13 Jul 2016 03:29:45 +0000 (11:29 +0800)]
gallium/dri: Add shared glapi to LIBADD on Android
An earlier patch fixed the problem for classic drivers, however Gallium
was still left broken. This patch applies the same workaround to
Gallium, when compiled for Android. Following is a quote from the
original patch:
0cbc90c57cfc mesa: dri: Add shared glapi to LIBADD on Android
/system/vendor/lib/dri/*_dri.so actually depend on libglapi: without
this, loading the so file fails with:
cannot locate symbol "__emutls_v._glapi_tls_Context"
On non-Android (non-bionic) platform, EGL uses the following
workflow, which works fine:
dlopen("libglapi.so", RTLD_LAZY | RTLD_GLOBAL);
dlopen("dri/<driver>_dri.so", RTLD_NOW | RTLD_GLOBAL);
However, bionic does not respect the RTLD_GLOBAL flag, and the dri
library cannot find symbols in libglapi.so, so we need to link
to libglapi.so explicitly. Android.mk already does this.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 18 Jul 2016 18:28:09 +0000 (19:28 +0100)]
mesa: scons: remove left over src/glsl include
The path no longer exists.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 18 Jul 2016 18:23:02 +0000 (19:23 +0100)]
mesa: scons: list builddir before srcdir
Analogous to previous commit.
Note: scons always uses OOT builds, while the in-tree generated files
could be created either manually or by the autoconf build.
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 18 Jul 2016 18:12:17 +0000 (19:12 +0100)]
mesa: automake: list builddir before srcdir
In the case of building in out-of-tree fashion, while having generated
in-tree sources, the latter [likely stale] files will be used.
Flip the order to prevent that.
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Józef Kucia [Tue, 19 Jul 2016 11:07:26 +0000 (13:07 +0200)]
radeonsi: advertise 8 bits subpixel precision for viewport bounds
Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Józef Kucia [Tue, 19 Jul 2016 11:07:25 +0000 (13:07 +0200)]
r600: advertise 8 bits subpixel precision for viewport bounds
Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Józef Kucia [Tue, 19 Jul 2016 11:07:24 +0000 (13:07 +0200)]
gallium: add a cap for VIEWPORT_SUBPIXEL_BITS (v2)
This allows Gallium drivers to advertise the subpixel precision
for floating point viewports bounds.
v2:
- Set ViewportSubpixelBits in st_init_limits.
Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Tue, 5 Jul 2016 20:43:14 +0000 (22:43 +0200)]
nvc0: disable MS images on GM107+
MS images have to be handled explicitly and I don't plan to implement
them for now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Mon, 4 Jul 2016 23:53:56 +0000 (01:53 +0200)]
nv50/ir: print OP_SUREDB subops in debug mode
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Fri, 24 Jun 2016 20:35:59 +0000 (22:35 +0200)]
gm107/ir: add emission for SUREDx
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Fri, 24 Jun 2016 20:34:52 +0000 (22:34 +0200)]
gm107/ir: add emission for SUSTx and SULDx
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Thu, 19 May 2016 09:59:25 +0000 (11:59 +0200)]
gm107/ra: fix constraints for surface operations
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Tue, 10 May 2016 10:50:07 +0000 (12:50 +0200)]
gm107/ir: lower surface operations
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Mon, 4 Jul 2016 17:15:02 +0000 (19:15 +0200)]
nvc0: bind images for 3d/cp shaders on GM107+
On Maxwell, images binding is slightly different (and much better)
regarding Fermi and Kepler because a texture view needs to be uploaded
for each image and this is going to simplify the thing a lot.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Sun, 26 Jun 2016 00:00:40 +0000 (02:00 +0200)]
nvc0: increase the tex handles area size in the driver cb
Currently, we can store 32 tex handles of 32-bits integer each and
that fits perfectly with the underlying hardware except on GM107+
which requires to upload a texture view for each images.
This patch increases the number of storable texture handles in the
driver constant buffer from 32 to 40 because we expose 8 images.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Kenneth Graunke [Tue, 19 Jul 2016 05:42:44 +0000 (22:42 -0700)]
nir: Fix uninitialized use of 'replacement'.
For intrinsics we don't care about, just skip to the next loop iteration
and process the next instruction. We don't want to execute the rest of
the code.
This was a bug in commit
cdfc05ea6e8c87876cdbf588aa8e03d70f3da4bb.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Kenneth Graunke [Mon, 18 Jul 2016 23:55:28 +0000 (16:55 -0700)]
i965: Use tex_mocs instead of rb_mocs for GL images.
Fixes a 10-20% performance regression in OglCSDof caused by commit
5a8c89038abab0184ea72664ab390ec6ca58b4d6, which made images (in the
image load/store sense) use BDW_MOCS_PTE instead of BDW_MOCS_WB.
This seems sketchy, as the default PTE value is supposed to be
WB LLC eLLC, which is the same as our MOCS WB setting. It's only
supposed to change when using a surface for display, which won't
ever happen for images. Something may be wrong in the kernel...
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Marek Olšák [Sun, 17 Jul 2016 11:23:53 +0000 (13:23 +0200)]
winsys/amdgpu: use pb_cache buckets for fewer pb_cache misses
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 17 Jul 2016 11:23:53 +0000 (13:23 +0200)]
winsys/radeon: use pb_cache buckets for fewer pb_cache misses
This makes Bioshock Infinite with deferred flushing 2.2% faster.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 16 Jul 2016 23:27:08 +0000 (01:27 +0200)]
gallium/pb_cache: reduce the number of pointer dereferences
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 16 Jul 2016 22:53:55 +0000 (00:53 +0200)]
gallium/pb_cache: divide the cache into buckets for reducing cache misses
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 17 Jul 2016 09:59:40 +0000 (11:59 +0200)]
gallium/pb_cache: check parameters that are more likely to fail first
This makes Bioshock Infinite with deferred flushing 2% faster.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 16 Jul 2016 11:41:54 +0000 (13:41 +0200)]
radeonsi: emit PS exports last
This effectively removes s_waitcnt instructions after FP16 exports.
Before:
v_cvt_pkrtz_f16_f32_e32 v0, v0, v1 ;
5E000300
v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ;
5E020702
exp 15, 0, 1, 0, 0, v0, v1, v0, v0 ;
F800040F 00000100
s_waitcnt expcnt(0) ;
BF8C0F0F
v_cvt_pkrtz_f16_f32_e32 v0, v4, v5 ;
5E000B04
v_cvt_pkrtz_f16_f32_e32 v1, v6, v7 ;
5E020F06
exp 15, 1, 1, 0, 0, v0, v1, v0, v0 ;
F800041F 00000100
s_waitcnt expcnt(0) ;
BF8C0F0F
v_cvt_pkrtz_f16_f32_e32 v0, v8, v9 ;
5E001308
v_cvt_pkrtz_f16_f32_e32 v1, v10, v11 ;
5E02170A
exp 15, 2, 1, 0, 0, v0, v1, v0, v0 ;
F800042F 00000100
s_waitcnt expcnt(0) ;
BF8C0F0F
v_cvt_pkrtz_f16_f32_e32 v0, v12, v13 ;
5E001B0C
v_cvt_pkrtz_f16_f32_e32 v1, v14, v15 ;
5E021F0E
exp 15, 3, 1, 1, 1, v0, v1, v0, v0 ;
F8001C3F 00000100
s_endpgm ;
BF810000
After:
v_cvt_pkrtz_f16_f32_e32 v0, v0, v1 ;
5E000300
v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ;
5E020702
v_cvt_pkrtz_f16_f32_e32 v2, v4, v5 ;
5E040B04
v_cvt_pkrtz_f16_f32_e32 v3, v6, v7 ;
5E060F06
exp 15, 0, 1, 0, 0, v0, v1, v0, v0 ;
F800040F 00000100
v_cvt_pkrtz_f16_f32_e32 v4, v8, v9 ;
5E081308
v_cvt_pkrtz_f16_f32_e32 v5, v10, v11 ;
5E0A170A
exp 15, 1, 1, 0, 0, v2, v3, v0, v0 ;
F800041F 00000302
v_cvt_pkrtz_f16_f32_e32 v6, v12, v13 ;
5E0C1B0C
v_cvt_pkrtz_f16_f32_e32 v7, v14, v15 ;
5E0E1F0E
exp 15, 2, 1, 0, 0, v4, v5, v0, v0 ;
F800042F 00000504
exp 15, 3, 1, 1, 1, v6, v7, v0, v0 ;
F8001C3F 00000706
s_endpgm ;
BF810000
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 13 Jul 2016 20:34:54 +0000 (22:34 +0200)]
radeonsi: set optimal settings in COMPUTE_RESOURCE_LIMITS
ported from Vulkan
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 15 Jul 2016 14:04:03 +0000 (16:04 +0200)]
radeonsi: really wait for the second EOP event and not the first one
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 14 Jul 2016 23:15:42 +0000 (01:15 +0200)]
gallium/radeon: remove RADEON_FLUSH_KEEP_TILING_FLAGS flag
always set
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Ian Romanick [Mon, 27 Jun 2016 18:38:15 +0000 (11:38 -0700)]
nir/algebraic: Optimize fabs(u2f(x))
I noticed this when I tried to do frexp(float(some_unsigned)) in the
ir_unop_find_lsb lowering pass. The code generated for frexp() uses
fabs, and this resulted in an extra instruction. Ultimately I ended up
not using frexp.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Fri, 24 Jun 2016 08:58:18 +0000 (01:58 -0700)]
st/mesa: Enable MESA_shader_integer_functions on all GLSL 1.30 platforms
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Thu, 23 Jun 2016 23:19:45 +0000 (16:19 -0700)]
i965: Enable MESA_shader_integer_functions on all GLSL 1.30 platforms
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Thu, 9 Jun 2016 23:35:30 +0000 (16:35 -0700)]
i965: Don't lower uaddCarry and usubBorrow in both GLSL IR and NIR
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Tue, 28 Jun 2016 21:48:22 +0000 (14:48 -0700)]
i965: Update assertion to account for Gen < 7
Previously SHADER_OPCODE_MULH could only exist on Gen7+, so the
assertion assumed the Gen7+ accumulator rules. A future patch will
allow this instruction on at least Gen6, so update the assertion.
v2: Use get_lowered_simd_width instead of open coding it. Suggested by
Curro.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Ian Romanick [Wed, 22 Jun 2016 20:12:26 +0000 (13:12 -0700)]
i965: Use LZD to implement nir_op_find_lsb on Gen < 7
v2: Rebase on changes to previous two patches.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Wed, 22 Jun 2016 00:18:04 +0000 (17:18 -0700)]
i965: Use LZD to implement nir_op_ifind_msb on Gen < 7
v2: Retype LZD source as UD to avoid potential problems with 0x80000000.
Suggested by Matt. Also update comment about problem values with
LZD(abs(x)). Suggested by Curro.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Tue, 21 Jun 2016 22:14:03 +0000 (15:14 -0700)]
i965: Use LZD to implement nir_op_ufind_msb
This uses one less instruction.
v2: Move emit_find_msb_using_lzd out of the visitor classes. Suggested
by Curro.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Tue, 21 Jun 2016 18:14:58 +0000 (11:14 -0700)]
i965: Always enable GL_ARB_shading_language_packing
With the existing lowering passes, the functions from this extension
become a bunch of bit twiddling operations that have always been
supported.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Tue, 21 Jun 2016 17:56:23 +0000 (10:56 -0700)]
i965: Move enable of EXT_shader_integer_mix
This extension does not depend on the Gen. It only depends on the
availability of GLSL 1.30.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Mon, 27 Jun 2016 22:21:21 +0000 (15:21 -0700)]
glsl: Add lowering pass for ir_bin_imul_high
This isn't the lowering pass you want. Most GPUs that can support GLSL
1.30 have a multiply unit that can do something more interesting than
32x32->32. Many have 32x16->48. Any GPU that does, should do the
lowering in the backend. This is just the thing that will always work.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Fri, 24 Jun 2016 08:53:33 +0000 (01:53 -0700)]
glsl: Add lowering pass for ir_unop_find_msb
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Fri, 24 Jun 2016 08:17:23 +0000 (01:17 -0700)]
glsl: Add lowering pass for ir_unop_find_lsb
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Fri, 24 Jun 2016 07:11:26 +0000 (00:11 -0700)]
glsl: Add lowering pass for ir_unop_bitfield_reverse
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Fri, 24 Jun 2016 06:16:10 +0000 (23:16 -0700)]
glsl: Add lowering pass for ir_quadop_bitfield_insert
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Thu, 23 Jun 2016 23:57:23 +0000 (16:57 -0700)]
glsl: Add lowering pass for ir_triop_bitfield_extract
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Thu, 23 Jun 2016 23:16:21 +0000 (16:16 -0700)]
glsl: Add lowering pass for ir_unop_bit_count
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Tue, 21 Jun 2016 17:29:49 +0000 (10:29 -0700)]
MESA_shader_integer_functions: Allow new function overload matching rules
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Tue, 21 Jun 2016 17:26:34 +0000 (10:26 -0700)]
MESA_shader_integer_functions: Allow implicit int->uint conversions
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Tue, 21 Jun 2016 17:21:47 +0000 (10:21 -0700)]
MESA_shader_integer_functions: Expose new built-in functions
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Mon, 20 Jun 2016 23:35:32 +0000 (16:35 -0700)]
MESA_shader_integer_functions: Boiler plate extension tracking
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Mon, 20 Jun 2016 23:28:34 +0000 (16:28 -0700)]
MESA_shader_integer_functions: Add extension specification
v2: Fix typo in #extension line noticed by Ken.
v3: Update spec status.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Samuel Pitoiset [Tue, 19 Jul 2016 12:47:57 +0000 (14:47 +0200)]
gm107/ir: make use of ADD32I for all immediates
ADD only allows to emit 19-bits immediates.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
Samuel Pitoiset [Tue, 19 Jul 2016 12:47:56 +0000 (14:47 +0200)]
gm107/ir: add missing NEG modifier for IADD32I
Like FADD32I, the NEG modifier of src0 is at position 56.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Andreas Boll [Tue, 19 Jul 2016 10:43:38 +0000 (12:43 +0200)]
ddebug: Fix trivial typo in stderr message
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Andreas Boll [Tue, 19 Jul 2016 10:30:40 +0000 (12:30 +0200)]
configure.ac: Use ${datarootdir} for --with-vulkan-icddir help string too
The help string wasn't updated in
cbc37f7.
Fixes:
cbc37f7 ("anv: install the intel_icd.json to ${datarootdir} by
default")
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: mesa-stable@lists.freedesktop.org
Eric Engestrom [Wed, 13 Jul 2016 21:50:54 +0000 (22:50 +0100)]
vl: fix memory leak
CovID:
1363008
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Boyuan Zhang [Mon, 18 Jul 2016 22:43:37 +0000 (18:43 -0400)]
vl: add entry point
Add entrypoint to distinguish H.264 decode and encode. For example, in patch
5/11 when is calling "VaCreateContext", "pps" and "sps" shouldn't be allocated
for H.264 encoding. So we need to use the entry_point to determine this is
H.264 decode or H.264 encode. We can use config to determine the entrypoint
since config_id is passed to us for VaCreateContext call. However, for
VaDestoyContext call, only context_id is passed to us. So we need to know the
entrypoint in order to not free the pps/sps for encoding case.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Ilia Mirkin [Sun, 17 Jul 2016 21:14:24 +0000 (17:14 -0400)]
nv50,nvc0: srgb rendering is only available for rgba/bgra
Mark both L8_SRGB and L8A8_SRGB as non-renderable (the latter already
didn't have the bind flags). This makes the state tracker pick a
different format when rendering is required, or mark the fb as
incomplete. This fixes:
bin/getteximage-formats init-by-clear-and-render -auto -fbo
bin/getteximage-formats init-by-rendering -auto -fbo
which previously ran into srgb-encoding differences.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Sat, 16 Jul 2016 19:07:21 +0000 (15:07 -0400)]
nvc0: add support for BGRA8 images
This is useful for pbo downloads, which are now accelerated with images.
BGRA8 is a moderately common format to do that in.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Jason Ekstrand [Mon, 18 Jul 2016 16:13:01 +0000 (09:13 -0700)]
i965: Skip update_texture_surface when the plane doesn't exist
Thanks to rebase fail, recent surface state changes (commits
7e951cd56,
8521ce1a7, and
69c0dc5c53) effectively reverted
727a9b24933 and
367cf3a2e3e
which was unintentional. This should bring it back.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Timothy Arceri [Mon, 11 Jul 2016 02:11:42 +0000 (12:11 +1000)]
glsl: use linked shaders rather than compiled shaders
At this point there is no reason not to be using the linked shaders,
using the linked shaders should be faster and will make things simpler
for upcoming shader cache work.
The previous variable name suggests the linked shaders were intended
to be used here anyway.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Lars Hamre [Mon, 18 Jul 2016 23:20:27 +0000 (01:20 +0200)]
The extension is already exposed, this simply marks it as done.
Signed-off-by: Lars Hamre <chemecse@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Anuj Phogat [Mon, 18 Jul 2016 22:53:24 +0000 (15:53 -0700)]
docs: Fix typo in extension name
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Anuj Phogat [Mon, 18 Jul 2016 22:42:18 +0000 (15:42 -0700)]
docs: Add support for GL_KHR_texture_compression_astc_sliced_3d
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Anuj Phogat [Mon, 18 Jul 2016 22:17:53 +0000 (15:17 -0700)]
Revert "docs: Mark KHR_texture_compression_astc_sliced_3d done on i965"
This reverts commit
82f8c239506ef126dcad266156f8945c62dc6bc9.
KHR_texture_compression_astc_sliced_3d is not a requirement for
GLES 3.2.
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>\
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Anuj Phogat [Fri, 8 Jul 2016 00:05:02 +0000 (17:05 -0700)]
docs: Mark KHR_texture_compression_astc_sliced_3d done on i965
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Anuj Phogat [Fri, 8 Jul 2016 00:04:17 +0000 (17:04 -0700)]
i965/gen9: Enable KHR_texture_compression_astc_sliced_3d
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Anuj Phogat [Fri, 8 Jul 2016 00:03:19 +0000 (17:03 -0700)]
mesa: Add the infrastructure for KHR_texture_compression_astc_sliced_3d
V2: Drop the changes to gl.xml.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Christian König [Thu, 7 Jul 2016 12:28:06 +0000 (14:28 +0200)]
radeon/uvd: add session context buffer for polaris 10/11 v2
This way we have unlimited UVD sessions.
v2: only enable it when kernel supports it as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Leo Liu [Thu, 14 Jul 2016 13:19:59 +0000 (09:19 -0400)]
vl/dri3: fix a memory leak from front buffer
Inspired by fix for mem leak of vdpau interop, resource_from_handle
set texture reference count, that need to be decreased and released,
recall there is a similar case for DRI3, that is with VA-API glx
extension, there is temporary TFP(texture from pixmap), we target it
through dma-buf. leak happens when without count down the reference.
Checked and found with mpv vo=opengl case, there only one static TFP,
the leak happens once, but for totem player using gstreamer VA-API glx,
the dynamic TFP for each frame, so leak quite a bit.
This fixes mem leak for mpv and totem.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Iago Toral Quiroga [Fri, 15 Jul 2016 08:55:05 +0000 (10:55 +0200)]
i965/tes/scalar: fix 64-bit indirect input loads
We totally ignored this before because there were no piglit tests for
indirect loads in tessellation stages with doubles.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Iago Toral Quiroga [Fri, 15 Jul 2016 08:48:03 +0000 (10:48 +0200)]
i965/tcs/scalar: only update imm_offset for second message in 64bit input loads
Our indirect URB read messages take both a direct and an indirect offset
so when we emit the second message for a 64-bit input load we can just
always incremement the immediate offset, even for the indirect case.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Thu, 14 Jul 2016 03:16:11 +0000 (20:16 -0700)]
i965: Move pulls_bary setting to emit_pixel_interpolator_send().
pulls_bary should be set when the shader uses a pixel interpolator
message. So, setting it from the function that emits pixel interpolator
messages makes a lot of sense.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Thu, 14 Jul 2016 23:52:10 +0000 (16:52 -0700)]
i965: Write gl_FragCoord directly to the destination.
This patch makes emit_general_interpolation take a destination register
as an argument, and write directly to that. This is simpler than the
old approach of ralloc'ing a register, writing to that temporary, and
then making the caller emit per-component MOVs to copy it to the actual
destination.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Fri, 15 Jul 2016 00:17:14 +0000 (17:17 -0700)]
i965: Drop has_pln checks in unlit centroid workaround.
The unlit centroid workaround starts being necessary on Gen6, which
is the first platform with multisampling. PLN exists on G45+, so all
platforms which need this workaround have PLN.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Thu, 14 Jul 2016 18:48:01 +0000 (11:48 -0700)]
i965: Drop VARYING_SLOT_FACE special case in barycentric setup.
glsl_to_nir always produces a system value for gl_FrontFacing, rather
than an input. So there should never be an input with this slot,
making this code dead.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Thu, 7 Jul 2016 09:02:38 +0000 (02:02 -0700)]
compiler: Rename INTERP_QUALIFIER_* to INTERP_MODE_*.
Likewise, rename the enum type to glsl_interp_mode.
Beyond the GLSL front-end, talking about "interpolation modes" seems
more natural than "interpolation qualifiers" - in the IR, we're removed
from how exactly the source language specifies how to interpolate an
input. Also, SPIR-V calls these "decorations" rather than "qualifiers".
Generated by:
$ find . -regextype egrep -regex '.*\.(c|cpp|h)' -type f -exec sed -i \
-e 's/INTERP_QUALIFIER_/INTERP_MODE_/g' \
-e 's/glsl_interp_qualifier/glsl_interp_mode/g' {} \;
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sat, 16 Jul 2016 20:19:43 +0000 (06:19 +1000)]
virgl: drop pointless leftover init of virgl_transfer_inline_write.
Pointed out by Marek.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Sun, 19 Jun 2016 20:57:50 +0000 (16:57 -0400)]
nv50: fix alphatest for non-blendable formats
The hardware can only do alphatest when using a blendable format. This
means that the various *16 norm formats didn't work with alphatest. It
appears that Talos Principle uses such formats, as well as alpha tests,
for some internal renders, which made them be incorrect. However this
does not appear to affect the final renders, but in a different game it
easily could.
The approach we take is that when alphatests are enabled and a suitable
format is used (which we anticipate is the vast minority of the time),
we insert code into the shader to perform the comparison and discard.
Once inserted, that code lives in the shader forever, and we re-upload
it each time the function changes with a fixed-up compare. To avoid
re-uploading too often, if we switch back to a blendable format, the
test is (effectively) disabled and the hw alphatest functionality is
used.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Rob Clark [Thu, 14 Jul 2016 20:08:31 +0000 (16:08 -0400)]
mesa/st: reduce size of state->st bitmask
In
d035d50 this changed to 64b.. which I'm pretty sure was
unintentional. Revert it back to 32b so the entire state struct
is a nice round 64b.
(Note sure that it would actually be measurable, but I did notice
that check_state() was hot in some benchmarks.)
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rob Clark [Wed, 13 Jul 2016 16:17:05 +0000 (12:17 -0400)]
gallium/u_queue: add optional cleanup callback
Adds a second optional cleanup callback, called after the fence is
signaled. This is needed if, for example, the queue has the last
reference to the object that embeds the util_queue_fence. In this
case we cannot drop the ref in the main callback, since that would
result in the fence being destroyed before it is signaled.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Thu, 14 Jul 2016 14:21:52 +0000 (16:21 +0200)]
radeonsi: remove the DRAW_PREAMBLE packet
According to firmware guys, the new sequence that we added for Polaris should
work on all CIK parts, and should actually be faster on some parts.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Sat, 16 Jul 2016 03:22:53 +0000 (21:22 -0600)]
mesa: handle numSamples=0 in _mesa_test_proxy_teximage()
Should fix the regressions reported in bug 96949.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96949
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Sat, 16 Jul 2016 00:53:13 +0000 (17:53 -0700)]
nir: Use dest.ssa.num_components rather than intrin->num_components.
I recently refactored this to share code between load and atomic
lowering. loads used intrin->num_components, while atomics used
intrin->dest.ssa.num_components. They should be equivalent, but
Jason wanted me to use the latter. I missed applying his review.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Thu, 7 Jul 2016 08:02:55 +0000 (01:02 -0700)]
nir: Update outdated intrinsic const_index comments.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Thu, 14 Jul 2016 21:18:33 +0000 (14:18 -0700)]
nir: Use nir_intrinsic_set_base in atomic lowering.
This is more readable and also offers assertions that protect against
setting const_index fields on the wrong kind of intrinsic.
Suggested by Jason.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 12 Jul 2016 09:07:29 +0000 (02:07 -0700)]
nir: Split nir_lower_io's input/output/atomic handling into helpers.
The original function was becoming a bit hard to read, with the details
of creating and filling out load/store/atomic atomics all in one
function.
This patch makes helpers for creating each type of intrinsic, and also
combines them with the *_op() helpers, as they're closely coupled and
not too large.
v2: Minor style nits from Jason.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 12 Jul 2016 09:38:27 +0000 (02:38 -0700)]
nir: Drop bogus nir_var_shader_in case in nir_lower_io's store_op().
This can't happen, the caller asserts that mode is shader_out or shared.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 12 Jul 2016 09:30:02 +0000 (02:30 -0700)]
nir: Share destination rewriting and replacement code in IO lowering.
Both loads and atomics had identical code to rewrite destinations,
and all cases had the same two lines to replace instructions.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 12 Jul 2016 09:16:30 +0000 (02:16 -0700)]
nir: Share get_io_offset handling in nir_lower_io.
The load/store/atomic cases all duplicated the get_io_offset code, with
a few tiny differences: stores didn't bother checking for per-vertex
inputs, because they can't be stored to, and atomics didn't check at
all, since shared variables aren't per-vertex.
However, it's harmless to check, and allows us to share more code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 12 Jul 2016 08:51:04 +0000 (01:51 -0700)]
nir: Make a 'var' temporary in nir_lower_io.
Less typing and word wrapping issues than intrin->variables[0]->var.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 12 Jul 2016 00:19:06 +0000 (17:19 -0700)]
i965: Remove the emit_linterp() helper.
Rather than computing the barycentric mode each time we emit a LINTERP,
we can simply compute it once, as soon as we know we're doing non-flat
interpolation.
At that point, emit_linterp() doesn't do much, so fold it into the
call sites and drop it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 12 Jul 2016 00:14:50 +0000 (17:14 -0700)]
i965: Reduce the number of fs_reg(brw_reg) calls in LINTERP handling.
A bit tidier.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Mon, 11 Jul 2016 22:00:37 +0000 (15:00 -0700)]
i965: Make a barycentric_mode() helper function.
This combines two copies of basically the same code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Mon, 11 Jul 2016 23:24:12 +0000 (16:24 -0700)]
i965: Rename brw_wm_barycentric_interp_mode to brw_barycentric_mode.
brw_wm_barycentric_interp_mode is wordy, brw_barycentric_mode is less
typing and suffers from fewer line wrapping problems.
The enum values themselves don't really benefit from "WM" in the name,
either. Put "BARYCENTRIC" first instead of at the end and drop "WM".
Generated by:
for file in *.c *.cpp *.h; do sed -i \
-e 's/brw_wm_barycentric_interp_mode/brw_barycentric_mode/g' \
-e 's/BRW_WM_\([A-Z_]*\)_BARYCENTRIC/BRW_BARYCENTRIC_\1/g' \
-e 's/BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT/BRW_BARYCENTRIC_MODE_COUNT/g' \
$file;
done
with a few whitespace changes.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Thu, 7 Jul 2016 07:47:18 +0000 (00:47 -0700)]
i965: Handle default interpolation modes and locations in NIR.
This consolidates a bunch of hacks in a single place - by setting
the interpolation modes and locations on variables appropriately,
we can simply trust them in the rest of the code. This avoids
having to handle INTERP_QUALIFIER_NONE, gl_Color overrides,
sample-shading overrides, and Gen4-5 centroid-overrides in a bunch
of places.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Sat, 11 Jun 2016 03:59:21 +0000 (20:59 -0700)]
i965/context: Remove some unnecessary vfuncs
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Fri, 10 Jun 2016 01:29:15 +0000 (18:29 -0700)]
i965: Get rid of gen6_surface_state.c
The only useful thing left was gen6_init_vtable_surface_functions which we
can easily put in brw_wm_surface_state.c.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Fri, 10 Jun 2016 00:06:57 +0000 (17:06 -0700)]
i965: Use ISL for emitting buffer surface states
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>