OSDN Git Service
Simon Atanasyan [Thu, 27 Jun 2019 12:08:10 +0000 (12:08 +0000)]
[mips] Fix indentation and split long lines. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364526
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Atanasyan [Thu, 27 Jun 2019 12:08:03 +0000 (12:08 +0000)]
[mips] Reformat MSA instruction definitions. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364525
91177308-0d34-0410-b5e6-
96231b3b80d8
Jeremy Morse [Thu, 27 Jun 2019 11:52:03 +0000 (11:52 +0000)]
Add triple to a test I just added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364524
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Thu, 27 Jun 2019 11:44:45 +0000 (11:44 +0000)]
IR: compare type attributes deeply when looking into functions.
FunctionComparator attempts to produce a stable comparison of two Function
instances by looking at all available properties. Since ByVal attributes now
contain a Type pointer, they are not trivially ordered and FunctionComparator
should use its own Type comparison logic to sort them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364523
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Thu, 27 Jun 2019 11:31:43 +0000 (11:31 +0000)]
[Object/invalid.test] - Convert most of the sub tests to YAML.
Object/invalid.test is a test case that is used to check the behavior of tools
when broken inputs are used.
The most often tool tested there is llvm-readobj. I think we might want to move
such tests to test\tools\llvm-readobj. For now this patch converts
many sub-tests to use YAML and removes 12 binaries from the inputs.
Differential revision: https://reviews.llvm.org/D63762
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364522
91177308-0d34-0410-b5e6-
96231b3b80d8
Stefan Stipanovic [Thu, 27 Jun 2019 11:27:54 +0000 (11:27 +0000)]
[Attributor] Deducing existing nounwind attribute.
Adding nounwind deduction in new attributor framework.
Reviewers: jdoerfert, uenoku
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D63379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364521
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 27 Jun 2019 11:22:23 +0000 (11:22 +0000)]
[X86][SSE] Regenerate v48 shuffle test on a variety of targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364520
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 27 Jun 2019 11:16:03 +0000 (11:16 +0000)]
[X86][AVX] SimplifyDemandedVectorElts - combine PERMPD(x) -> EXTRACTF128(X)
If we only use the bottom lane, see if we can simplify this to extract_subvector - which is always at least as quick as PERMPD/PERMQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364518
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Thu, 27 Jun 2019 11:08:42 +0000 (11:08 +0000)]
[yaml2obj] - Allow overriding e_shentsize, e_shoff, e_shnum and e_shstrndx fields in the YAML.
This allows setting different values for e_shentsize, e_shoff, e_shnum
and e_shstrndx fields and is useful for producing broken inputs for various
test cases.
Differential revision: https://reviews.llvm.org/D63771
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364517
91177308-0d34-0410-b5e6-
96231b3b80d8
Djordje Todorovic [Thu, 27 Jun 2019 10:51:15 +0000 (10:51 +0000)]
[ISEL][X86] Tracking of registers that forward call arguments
While lowering calls, collect info about registers that forward arguments
into following function frame. We store such info into the MachineFunction
of the call. This is used very late when dumping DWARF info about
call site parameters.
([9/13] Introduce the debug entry values.)
Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>
Differential Revision: https://reviews.llvm.org/D60715
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364516
91177308-0d34-0410-b5e6-
96231b3b80d8
Jeremy Morse [Thu, 27 Jun 2019 10:20:27 +0000 (10:20 +0000)]
[DebugInfo] Avoid register coalesing unsoundly changing DBG_VALUE locations
Once MIR code leaves SSA form and the liveness of a vreg is considered,
DBG_VALUE insts are able to refer to non-live vregs, because their
debug-uses do not contribute to liveness. This non-liveness becomes
problematic for optimizations like register coalescing, as they can't
``see'' the debug uses in the liveness analyses.
As a result registers get coalesced regardless of debug uses, and that can
lead to invalid variable locations containing unexpected values. In the
added test case, the first vreg operand of ADD32rr is merged with various
copies of the vreg (great for performance), but a DBG_VALUE of the
unmodified operand is blindly updated to the modified operand. This changes
what value the variable will appear to have in a debugger.
Fix this by changing any DBG_VALUE whose operand will be resurrected by
register coalescing to be a $noreg DBG_VALUE, i.e. give the variable no
location. This is an overapproximation as some coalesced locations are
safe (others are not) -- an extra domination analysis would be required to
work out which, and it would be better if we just don't generate non-live
DBG_VALUEs.
This fixes PR40010.
Differential Revision: https://reviews.llvm.org/D56151
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364515
91177308-0d34-0410-b5e6-
96231b3b80d8
Diana Picus [Thu, 27 Jun 2019 09:49:07 +0000 (09:49 +0000)]
[GlobalISel] Remove [un]packRegs from IRTranslator
Remove the last use of packRegs from IRTranslator and delete
pack/unpackRegs. This introduces a fallback to DAGISel for intrinsics
with aggregate arguments, since we don't have a testcase for them so
it's hard to tell how we'd want to handle them.
Discussed in https://reviews.llvm.org/D63551
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364514
91177308-0d34-0410-b5e6-
96231b3b80d8
Diana Picus [Thu, 27 Jun 2019 09:24:30 +0000 (09:24 +0000)]
[AArch64 GlobalISel] Cleanup CallLowering. NFCI
Now that lowerCall and lowerFormalArgs have been refactored, we can
simplify splitToValueTypes.
Differential Revision: https://reviews.llvm.org/D63552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364513
91177308-0d34-0410-b5e6-
96231b3b80d8
Diana Picus [Thu, 27 Jun 2019 09:18:03 +0000 (09:18 +0000)]
[GlobalISel] Accept multiple vregs for lowerCall's args
Change the interface of CallLowering::lowerCall to accept several
virtual registers for each argument, instead of just one. This is a
follow-up to D46018.
CallLowering::lowerReturn was similarly refactored in D49660 and
lowerFormalArguments in D63549.
With this change, we no longer pack the virtual registers generated for
aggregates into one big lump before delegating to the target. Therefore,
the target can decide itself whether it wants to handle them as separate
pieces or use one big register.
ARM and AArch64 have been updated to use the passed in virtual registers
directly, which means we no longer need to generate so many
merge/extract instructions.
NFCI for AMDGPU, Mips and X86.
Differential Revision: https://reviews.llvm.org/D63551
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364512
91177308-0d34-0410-b5e6-
96231b3b80d8
Diana Picus [Thu, 27 Jun 2019 09:15:53 +0000 (09:15 +0000)]
[GlobalISel] Accept multiple vregs for lowerCall's result
Change the interface of CallLowering::lowerCall to accept several
virtual registers for the call result, instead of just one. This is a
follow-up to D46018.
CallLowering::lowerReturn was similarly refactored in D49660 and
lowerFormalArguments in D63549.
With this change, we no longer pack the virtual registers generated for
aggregates into one big lump before delegating to the target. Therefore,
the target can decide itself whether it wants to handle them as separate
pieces or use one big register.
ARM and AArch64 have been updated to use the passed in virtual registers
directly, which means we no longer need to generate so many
merge/extract instructions.
NFCI for AMDGPU, Mips and X86.
Differential Revision: https://reviews.llvm.org/D63550
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364511
91177308-0d34-0410-b5e6-
96231b3b80d8
Diana Picus [Thu, 27 Jun 2019 08:54:17 +0000 (08:54 +0000)]
[GlobalISel] Accept multiple vregs in lowerFormalArgs
Change the interface of CallLowering::lowerFormalArguments to accept
several virtual registers for each formal argument, instead of just one.
This is a follow-up to D46018.
CallLowering::lowerReturn was similarly refactored in D49660. lowerCall
will be refactored in the same way in follow-up patches.
With this change, we forward the virtual registers generated for
aggregates to CallLowering. Therefore, the target can decide itself
whether it wants to handle them as separate pieces or use one big
register. We also copy the pack/unpackRegs helpers to CallLowering to
facilitate this.
ARM and AArch64 have been updated to use the passed in virtual registers
directly, which means we no longer need to generate so many
merge/extract instructions.
AArch64 seems to have had a bug when lowering e.g. [1 x i8*], which was
put into a s64 instead of a p0. Added a test-case which illustrates the
problem more clearly (it crashes without this patch) and fixed the
existing test-case to expect p0.
AMDGPU has been updated to unpack into the virtual registers for
kernels. I think the other code paths fall back for aggregates, so this
should be NFC.
Mips doesn't support aggregates yet, so it's also NFC.
x86 seems to have code for dealing with aggregates, but I couldn't find
the tests for it, so I just added a fallback to DAGISel if we get more
than one virtual register for an argument.
Differential Revision: https://reviews.llvm.org/D63549
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364510
91177308-0d34-0410-b5e6-
96231b3b80d8
Diana Picus [Thu, 27 Jun 2019 08:50:53 +0000 (08:50 +0000)]
[GlobalISel] Allow multiple VRegs in ArgInfo. NFC
Allow CallLowering::ArgInfo to contain more than one virtual register.
This is useful when passes split aggregates into several virtual
registers, but need to also provide information about the original type
to the call lowering. Used in follow-up patches.
Differential Revision: https://reviews.llvm.org/D63548
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364509
91177308-0d34-0410-b5e6-
96231b3b80d8
Jay Foad [Thu, 27 Jun 2019 08:19:28 +0000 (08:19 +0000)]
[AMDGPU] Fix +DumpCode to print an entry label for the first function
Summary:
The +DumpCode attribute is a horrible hack in AMDGPU to embed the
disassembly of the generated code into the elf file. It is used by LLPC
to implement an extension that allows the application to read back the
disassembly of the code.
It tries to print an entry label at the start of every function, but
that didn't work for the first function in the module because
DumpCodeInstEmitter wasn't initialised until EmitFunctionBodyStart
which is too late.
Change-Id: I790d73ddf4f51fd02ab32529380c7cb7c607c4ee
Reviewers: arsenm, tpr, kzhuravl
Reviewed By: arsenm
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364508
91177308-0d34-0410-b5e6-
96231b3b80d8
Mikael Holmen [Thu, 27 Jun 2019 08:16:18 +0000 (08:16 +0000)]
Silence gcc warning after r364458
Without the fix gcc 7.4.0 complains with
../lib/Target/X86/X86ISelLowering.cpp: In function 'bool getFauxShuffleMask(llvm::SDValue, llvm::SmallVectorImpl<int>&, llvm::SmallVectorImpl<llvm::SDValue>&, llvm::SelectionDAG&)':
../lib/Target/X86/X86ISelLowering.cpp:6690:36: error: enumeral and non-enumeral type in conditional expression [-Werror=extra]
int Idx = (ZeroMask[j] ? SM_SentinelZero : (i + j + Ofs));
~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1plus: all warnings being treated as errors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364507
91177308-0d34-0410-b5e6-
96231b3b80d8
Djordje Todorovic [Thu, 27 Jun 2019 07:48:06 +0000 (07:48 +0000)]
[MachineFunction] Base support for call site info tracking
Add an attribute into the MachineFunction that tracks call site info.
([8/13] Introduce the debug entry values.)
Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>
Differential Revision: https://reviews.llvm.org/D61061
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364506
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Thu, 27 Jun 2019 07:32:19 +0000 (07:32 +0000)]
Fix -Wunused-variable warnings after r364464
/work/llvm.monorepo/llvm/lib/Bitcode/Reader/BitcodeReader.cpp: In function
‘llvm::Expected<std::basic_string<char> > readIdentificationBlock(llvm::BitstreamCursor&)’:
/work/llvm.monorepo/llvm/lib/Bitcode/Reader/BitcodeReader.cpp:205:22:
warning: unused variable ‘BitCode’ [-Wunused-variable]
switch (unsigned BitCode = MaybeBitCode.get()) {
^
/work/llvm.monorepo/llvm/lib/Bitcode/Reader/BitcodeReader.cpp: In member function
‘llvm::Error {anonymous}::ModuleSummaryIndexBitcodeReader::parseModule()’:
/work/llvm.monorepo/llvm/lib/Bitcode/Reader/BitcodeReader.cpp:5367:26:
warning: unused variable ‘BitCode’ [-Wunused-variable]
switch (unsigned BitCode = MaybeBitCode.get()) {
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364505
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Thu, 27 Jun 2019 07:32:10 +0000 (07:32 +0000)]
Fix GCC 4 build after r364464
It was failing with:
In file included from /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/lib/Bitcode/Reader/BitstreamReader.cpp:9:0:
/b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/Bitcode/BitstreamReader.h:
In member function 'llvm::Expected<long unsigned int> llvm::SimpleBitstreamCursor::ReadVBR64(unsigned int)':
/b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/Bitcode/BitstreamReader.h:262:14:
error: could not convert 'MaybeRead' from 'llvm::Expected<unsigned int>' to 'llvm::Expected<long unsigned int>'
return MaybeRead;
^
/b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/Bitcode/BitstreamReader.h:279:16:
error: could not convert 'MaybeRead' from 'llvm::Expected<unsigned int>' to 'llvm::Expected<long unsigned int>'
return MaybeRead;
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364504
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Thu, 27 Jun 2019 06:08:57 +0000 (06:08 +0000)]
gn build: Follow-up to r364491 "[GN] Update build files"
- Merge r364427 (GSYM lib) more: It was missing the new unit test
(as pointed out by llvm/utils/gn/build/sync_source_lists_from_cmake.py),
and it had some superfluous deps not present in the cmake build.
- Merge r364474 (clang DependencyScanning lib) more: The deps didn't
quite match cmake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364501
91177308-0d34-0410-b5e6-
96231b3b80d8
Djordje Todorovic [Thu, 27 Jun 2019 06:07:41 +0000 (06:07 +0000)]
[IR] Add DISuprogram and DIE for a func decl
A unique DISubprogram may be attached to a function declaration used for
call site debug info.
([6/13] Introduce the debug entry values.)
Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>
Differential Revision: https://reviews.llvm.org/D60713
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364500
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 27 Jun 2019 05:52:00 +0000 (05:52 +0000)]
[X86] Remove (vzext_movl (scalar_to_vector (load))) matching code from selectScalarSSELoad.
I think this will be turning into vzext_load during DAG combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364499
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 27 Jun 2019 05:51:56 +0000 (05:51 +0000)]
[X86] Teach selectScalarSSELoad to not narrow volatile loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364498
91177308-0d34-0410-b5e6-
96231b3b80d8
Huihui Zhang [Thu, 27 Jun 2019 05:46:06 +0000 (05:46 +0000)]
[InstCombine][NFCI] Fix test comments.
For fold
(X & (signbit l>> Y)) ==/!= 0 -> (X << Y) >=/< 0
(X & (signbit << Y)) ==/!= 0 -> (X l>> Y) >=/< 0
Test cases of X being constant are positive tests not negative.
Prep work for D62818.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364497
91177308-0d34-0410-b5e6-
96231b3b80d8
Kang Zhang [Thu, 27 Jun 2019 03:39:09 +0000 (03:39 +0000)]
[NFC][PowerPC] Improve the for loop in Early Return
Summary:
In `PPCEarlyReturn.cpp`
```
183 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
184 MachineBasicBlock &B = *I++;
185 if (processBlock(B))
186 Changed = true;
187 }
```
Above code can be improved to:
```
184 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E;) {
185 MachineBasicBlock &B = *I++;
186 Changed |= processBlock(B);
187 }
```
Reviewed By: hfinkel
Differential Revision: https://reviews.llvm.org/D63800
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364496
91177308-0d34-0410-b5e6-
96231b3b80d8
Vitaly Buka [Thu, 27 Jun 2019 01:35:47 +0000 (01:35 +0000)]
[GN] Fix check-llvm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364493
91177308-0d34-0410-b5e6-
96231b3b80d8
Vitaly Buka [Thu, 27 Jun 2019 01:34:19 +0000 (01:34 +0000)]
[GN] Update build files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364491
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Wed, 26 Jun 2019 23:46:51 +0000 (23:46 +0000)]
[ARM] Don't reserve R12 on Thumb1 as an emergency spill slot.
The current implementation of ThumbRegisterInfo::saveScavengerRegister
is bad for two reasons: one, it's buggy, and two, it blocks using R12
for other optimizations. So this patch gets rid of it, and adds the
necessary support for using an ordinary emergency spill slot on Thumb1.
(Specifically, I think saveScavengerRegister was broken by r305625, and
nobody noticed for two years because the codepath is almost never used.
The new code will also probably not be used much, but it now has better
tests, and if we fail to emit a necessary emergency spill slot we get a
reasonable error message instead of a miscompile.)
A rough outline of the changes in the patch:
1. Gets rid of ThumbRegisterInfo::saveScavengerRegister.
2. Modifies ARMFrameLowering::determineCalleeSaves to allocate an
emergency spill slot for Thumb1.
3. Implements useFPForScavengingIndex, so the emergency spill slot isn't
placed at a negative offset from FP on Thumb1.
4. Modifies the heuristics for allocating an emergency spill slot to
support Thumb1. This includes fixing ExtraCSSpill so we don't try to
use "lr" as a substitute for allocating an emergency spill slot.
5. Allocates a base pointer in more cases, so the emergency spill slot
is always accessible.
6. Modifies ARMFrameLowering::ResolveFrameIndexReference to compute the
right offset in the new cases where we're forcing a base pointer.
7. Ensures we never generate a load or store with an offset outside of
its frame object. This makes the heuristics more straightforward.
8. Changes Thumb1 prologue and epilogue emission so it never uses
register scavenging.
Some of the changes to the emergency spill slot heuristics in
determineCalleeSaves affect ARM/Thumb2; hopefully, they should allow
the compiler to avoid allocating an emergency spill slot in cases
where it isn't necessary. The rest of the changes should only affect
Thumb1.
Differential Revision: https://reviews.llvm.org/D63677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364490
91177308-0d34-0410-b5e6-
96231b3b80d8
JF Bastien [Wed, 26 Jun 2019 23:08:29 +0000 (23:08 +0000)]
Fix Bitcode/invalid.test
On the armv8 bot the failure is slightly different in the number it prints. Don't check the numbers. This was caused by r364464.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364488
91177308-0d34-0410-b5e6-
96231b3b80d8
Pengxuan Zheng [Wed, 26 Jun 2019 22:07:43 +0000 (22:07 +0000)]
[cmake] Allow config.guess to be run with MSYS on Windows
Summary:
With r363420, config.guess can no longer be run with MSYS on Windows and this
patch should be able to fix this particular case.
Reviewers: compnerd
Reviewed By: compnerd
Subscribers: mgorny, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63834
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364485
91177308-0d34-0410-b5e6-
96231b3b80d8
Gerolf Hoflehner [Wed, 26 Jun 2019 21:44:37 +0000 (21:44 +0000)]
[SCCP] Fix non-deterministic uselists of return values (DenseMap -> MapVector)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364482
91177308-0d34-0410-b5e6-
96231b3b80d8
Vasileios Porpodas [Wed, 26 Jun 2019 21:25:24 +0000 (21:25 +0000)]
[SLP] Look-ahead operand reordering heuristic.
Summary: This patch introduces a new heuristic for guiding operand reordering. The new "look-ahead" heuristic can look beyond the immediate predecessors. This helps break ties when the immediate predecessors have identical opcodes (see lit test for an example).
Reviewers: RKSimon, ABataev, dtemirbulatov, Ayal, hfinkel, rnk
Reviewed By: RKSimon, dtemirbulatov
Subscribers: rnk, rcorcs, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364478
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 26 Jun 2019 21:19:31 +0000 (21:19 +0000)]
[InstCombine] change 'tmp' variable names; NFC
I don't think there was anything going wrong here,
but the auto-generating CHECK line script is known
to have problems with 'TMP' because it uses that
to match nameless values.
This is a retry of rL364452.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364477
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 26 Jun 2019 20:56:18 +0000 (20:56 +0000)]
AMDGPU: Assert SPAdj is 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364473
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 26 Jun 2019 20:56:15 +0000 (20:56 +0000)]
PEI: Add default handling of spills to registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364472
91177308-0d34-0410-b5e6-
96231b3b80d8
Jinsong Ji [Wed, 26 Jun 2019 20:35:19 +0000 (20:35 +0000)]
[UpdateTestChecks][NFC] Remove entries with same prefix
Matching is 'lossy', triples with same prefix can be dropped.
Differential Revision: https://reviews.llvm.org/D63732
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364471
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 26 Jun 2019 20:35:18 +0000 (20:35 +0000)]
[AMDGPU] Fix Livereg computation during epilogue insertion
The LivePhysRegs calculated in order to find a scratch register in the
epilogue code wrongly uses 'LiveIns'. Instead, it should use the
'Liveout' sets. For the liveness, also considering the operands of
the terminator (return) instruction which is the insertion point for
the scratch-exec-copy instruction.
Patch by Christudasan Devadasan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364470
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 26 Jun 2019 20:16:19 +0000 (20:16 +0000)]
[X86] Rework the logic in LowerBuildVectorv16i8 to make better use of any_extend and break false dependencies. Other improvements
This patch rewrites the loop iteration to only visit every other element starting with element 0. And we work on the "even" element and "next" element at the same time. The "First" logic has been moved to the bottom of the loop and doesn't run on every element. I believe it could create dangling nodes previously since we didn't check if we were going to use SCALAR_TO_VECTOR for the first insertion. I got rid of the "First" variable and just do a null check on V which should be equivalent. We also no longer use undef as the starting V for vectors with no zeroes to avoid false dependencies. This matches v8i16.
I've changed all the extends and OR operations to use MVT::i32 since that's what they'll be promoted to anyway. I've tried to use zero_extend only when necessary and use any_extend otherwise. This resulted in some improvements in tests where we are now able to promote aligned (i32 (extload i8)) to a 32-bit load.
Differential Revision: https://reviews.llvm.org/D63702
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364469
91177308-0d34-0410-b5e6-
96231b3b80d8
Guanzhong Chen [Wed, 26 Jun 2019 20:16:14 +0000 (20:16 +0000)]
[WebAssembly] Implement Address Sanitizer for Emscripten
Summary:
This diff enables address sanitizer on Emscripten.
On Emscripten, real memory starts at the value passed to --global-base.
All memory before this is used as shadow memory, and thus the shadow mapping
function is simply dividing by 8.
Reviewers: tlively, aheejin, sbc100
Reviewed By: sbc100
Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D63742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364468
91177308-0d34-0410-b5e6-
96231b3b80d8
JF Bastien [Wed, 26 Jun 2019 19:50:12 +0000 (19:50 +0000)]
BitStream reader: propagate errors
The bitstream reader handles errors poorly. This has two effects:
* Bugs in file handling (especially modules) manifest as an "unexpected end of
file" crash
* Users of clang as a library end up aborting because the code unconditionally
calls `report_fatal_error`
The bitstream reader should be more resilient and return Expected / Error as
soon as an error is encountered, not way late like it does now. This patch
starts doing so and adopting the error handling where I think it makes sense.
There's plenty more to do: this patch propagates errors to be minimally useful,
and follow-ups will propagate them further and improve diagnostics.
https://bugs.llvm.org/show_bug.cgi?id=42311
<rdar://problem/
33159405>
Differential Revision: https://reviews.llvm.org/D63518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364464
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 26 Jun 2019 19:45:48 +0000 (19:45 +0000)]
[X86] Remove isTypePromotionOfi1ZeroUpBits and its helpers.
This was trying to optimize concat_vectors with zero of setcc or
kand instructions. But I think it produced the same code we
produce for a concat_vectors with 0 even it it doesn't come from
one of those operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364463
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 26 Jun 2019 19:18:50 +0000 (19:18 +0000)]
Fix some undefined behavior (excessive shift of signed value) in r364253 detected by ubsan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364461
91177308-0d34-0410-b5e6-
96231b3b80d8
Nicolai Haehnle [Wed, 26 Jun 2019 19:16:35 +0000 (19:16 +0000)]
llvm-objcopy: silence warning introduced in r364296
Change-Id: I306e866d497e55945fb3b471eb0727b63ad9e4b9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364460
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 26 Jun 2019 18:53:24 +0000 (18:53 +0000)]
Fix Wdocumentation warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364459
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 26 Jun 2019 18:21:26 +0000 (18:21 +0000)]
[X86][SSE] getFauxShuffleMask - handle OR(x,y) where x and y have no overlapping bits
Create a per-byte shuffle mask based on the computeKnownBits from each operand - if for each byte we have a known zero (or both) then it can be safely blended.
Fixes PR41545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364458
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 26 Jun 2019 18:06:51 +0000 (18:06 +0000)]
Revert [InstCombine] change 'tmp' variable names; NFC
This reverts r364452 (git commit
6083ae0b4a250c69f6d5b13b3742ee1fe5b878d5)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364455
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 26 Jun 2019 17:56:53 +0000 (17:56 +0000)]
[X86][AVX] Add reduced test case for PR41545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364454
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Wed, 26 Jun 2019 17:51:47 +0000 (17:51 +0000)]
Make AddLastArg() variadic and use it more. No behavior change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364453
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 26 Jun 2019 17:43:30 +0000 (17:43 +0000)]
[InstCombine] change 'tmp' variable names; NFC
I don't think there was anything going wrong here,
but the auto-generating CHECK line script is known
to have problems with 'TMP' because it uses that
to match nameless values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364452
91177308-0d34-0410-b5e6-
96231b3b80d8
Ryan Taylor [Wed, 26 Jun 2019 17:34:57 +0000 (17:34 +0000)]
[AMDGPU] Fix for branch offset hardware workaround
Summary:
This fixes a hardware bug that makes a branch offset of 0x3f unsafe.
This replaces the 32 bit branch with offset 0x3f to a 64 bit
instruction that includes the same 32 bit branch and the encoding
for a s_nop 0 to follow. The relaxer than modifies the offsets
accordingly.
Change-Id: I10b7aed99d651f8159401b01bb421f105fa6288e
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364451
91177308-0d34-0410-b5e6-
96231b3b80d8
Ulrich Weigand [Wed, 26 Jun 2019 17:19:12 +0000 (17:19 +0000)]
Allow matching extend-from-memory with strict FP nodes
This implements a small enhancement to https://reviews.llvm.org/D55506
Specifically, while we were able to match strict FP nodes for
floating-point extend operations with a register as source, this
did not work for operations with memory as source.
That is because from regular operations, this is represented as
a combined "extload" node (which is a variant of a load SD node);
but there is no equivalent using a strict FP operation.
However, it turns out that even in the absence of an extload
node, we can still just match the operations explicitly, e.g.
(strict_fpextend (f32 (load node:$ptr))
This patch implements that method to match the LDEB/LXEB/LXDB
SystemZ instructions even when the extend uses a strict-FP node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364450
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Wed, 26 Jun 2019 17:19:09 +0000 (17:19 +0000)]
[IndVars] Kill a redundant bit of debug output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364449
91177308-0d34-0410-b5e6-
96231b3b80d8
Greg Clayton [Wed, 26 Jun 2019 16:22:58 +0000 (16:22 +0000)]
Fix builbots after r364427.
I was using an iterator that was equal to the end of a collection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364447
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Wed, 26 Jun 2019 16:19:59 +0000 (16:19 +0000)]
[WebAssembly] Omit wrap on i64x2.{shl,shr*} ISel when possible
Summary:
Since the WebAssembly SIMD shift instructions take i32 operands, we
truncate the i64 operand to <2 x i64> shifts during ISel. When the i64
operand is sign extended from i32, this CL makes it so the sign
extension is dropped instead of a wrap instruction added.
Reviewers: dschuff, aheejin
Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63615
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364446
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Wed, 26 Jun 2019 16:17:15 +0000 (16:17 +0000)]
[WebAssembly] Implement tail calls and unify tablegen call classes
Summary:
Implements direct and indirect tail calls enabled by the 'tail-call'
feature in both DAG ISel and FastISel. Updates existing call tests and
adds new tests including a binary encoding test.
Reviewers: aheejin
Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62877
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364445
91177308-0d34-0410-b5e6-
96231b3b80d8
Scott Linder [Wed, 26 Jun 2019 16:13:17 +0000 (16:13 +0000)]
Fix leaks in LLVMCreateDisasmCPUFeatures
Differential Revision: https://reviews.llvm.org/D63795
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364444
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 26 Jun 2019 15:52:59 +0000 (15:52 +0000)]
[InstCombine] simplify code for inserts -> splat; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364441
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Liao [Wed, 26 Jun 2019 15:46:48 +0000 (15:46 +0000)]
Fix build in shared lib mode.
- The newly added GSYM misses LLVMBuild.txt. Add a barely one to pass
the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364440
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexandre Ganea [Wed, 26 Jun 2019 15:42:42 +0000 (15:42 +0000)]
[xray] Remove usage of procid_t
Differential Revision: https://reviews.llvm.org/D61946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364439
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 26 Jun 2019 15:24:08 +0000 (15:24 +0000)]
[InstCombine] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364437
91177308-0d34-0410-b5e6-
96231b3b80d8
Evandro Menezes [Wed, 26 Jun 2019 15:11:31 +0000 (15:11 +0000)]
[CodeGen] Improve formatting of jump tables (NFC)
Split jump tables into individual lines and fix spacing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364436
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 26 Jun 2019 14:58:11 +0000 (14:58 +0000)]
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PMULDQ
Allows narrowInsertExtractVectorBinOp to reduce vector size instead of the more restricted SimplifyDemandedVectorEltsForTargetNode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364434
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 26 Jun 2019 14:42:39 +0000 (14:42 +0000)]
[NFC][InstCombine] Revisit one-use tests in shift-amount-reassociation-in-bittest.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364433
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 26 Jun 2019 14:40:49 +0000 (14:40 +0000)]
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ
Allows narrowInsertExtractVectorBinOp to reduce vector size
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364432
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 26 Jun 2019 14:34:41 +0000 (14:34 +0000)]
[X86][SSE] X86TargetLowering::isBinOp - add PCMPGT
Allows narrowInsertExtractVectorBinOp to reduce vector size
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364431
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 26 Jun 2019 14:24:41 +0000 (14:24 +0000)]
[NFC][InstCombine] Add shift amount reassociation in bittest tests (PR42399)
https://bugs.llvm.org/show_bug.cgi?id=42399
https://rise4fun.com/Alive/kBb
https://rise4fun.com/Alive/1SB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364430
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 26 Jun 2019 14:21:29 +0000 (14:21 +0000)]
[X86] shouldScalarizeBinop - never scalarize target opcodes.
We have (almost) no target opcodes that have scalar/vector equivalents - for now assume we can't scalarize them (we can add exceptions if we need to).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364429
91177308-0d34-0410-b5e6-
96231b3b80d8
Greg Clayton [Wed, 26 Jun 2019 14:09:09 +0000 (14:09 +0000)]
Add GSYM utility files along with unit tests.
The full GSYM patch started with: https://reviews.llvm.org/D53379
In that patch we wanted to split up getting GSYM into the LLVM code base so we are not committing too much code at once.
This is a first in a series of patches where I only add the foundation classes along with complete unit tests. They provide the foundation for encoding and decoding a GSYM file.
File entries are defined in llvm::gsym::FileEntry. This class splits the file up into a directory and filename represented by uniqued string table offsets. This allows all files that are referred to in a GSYM file to be encoded as 1 based indexes into a global file table in the GSYM file.
Function information in stored in llvm::gsym::FunctionInfo. This object represents a contiguous address range that has a name and range with an optional line table and inline call stack information.
Line table entries are defined in llvm::gsym::LineEntry. They store only address, file and line information to keep the line tables simple and allows the information to be efficiently encoded in a subsequent patch.
Inline information is defined in llvm::gsym::InlineInfo. These structs store the name of the inline function, along with one or more address ranges, and the file and line that called this function. They also contain any child inline information.
There are also utility classes for address ranges in llvm::gsym::AddressRange, and string table support in llvm::gsym::StringTable which are simple classes.
The unit tests test all the APIs on these simple classes so they will be ready for the next patches where we will create GSYM files and parse GSYM files.
Differential Revision: https://reviews.llvm.org/D63104
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364427
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 26 Jun 2019 13:48:04 +0000 (13:48 +0000)]
AMDGPU: Fix unused variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364426
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 26 Jun 2019 13:39:29 +0000 (13:39 +0000)]
AMDGPU: Check MRI for callee saved regs instead of TRI
This should the same, but MRI does allow dynamically changing the CSR
set, although currently not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364425
91177308-0d34-0410-b5e6-
96231b3b80d8
Fedor Sergeev [Wed, 26 Jun 2019 13:24:24 +0000 (13:24 +0000)]
[InlineCost] cleanup calculations of Cost and Threshold
Summary:
Doing better separation of Cost and Threshold.
Cost counts the abstract complexity of live instructions, while Threshold is an upper bound of complexity that inlining is comfortable to pay.
There are two parts:
- huge 15K last-call-to-static bonus is no longer subtracted from Cost
but rather is now added to Threshold.
That makes much more sense, as the cost of inlining (Cost) is not changed by the fact
that internal function is called once. It only changes the likelyhood of this inlining
being profitable (Threshold).
- bonus for calls proved-to-be-inlinable into callee is no longer subtracted from Cost
but added to Threshold instead.
While calculations are somewhat different, overall InlineResult should stay the same since Cost >= Threshold compares the same.
Reviewers: eraman, greened, chandlerc, yrouban, apilipenko
Reviewed By: apilipenko
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364422
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 26 Jun 2019 12:19:52 +0000 (12:19 +0000)]
[X86][Codegen] X86DAGToDAGISel::matchBitExtract(): consistently capture lambdas by value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364420
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 26 Jun 2019 12:19:47 +0000 (12:19 +0000)]
[X86] X86DAGToDAGISel::matchBitExtract(): pattern c: truncation awareness
Summary:
The one thing of note here is that the 'bitwidth' constant (32/64) was previously pessimistic.
Given `x & (-1 >> (C - z))`, we were taking `C` to be `bitwidth(x)`, but in reality
we want `(-1 >> (C - z))` pattern to mean "low z bits must be all-ones".
And for that, `C` should be `bitwidth(-1 >> (C - z))`, i.e. of the shift operation itself.
Last pattern D does not seem to exhibit any of these truncation issues.
Although it has the opposite problem - if we extract low bits (no shift) from i64,
and then truncate to i32, then we fail to shrink this 64-bit extraction into 32-bit extraction.
Reviewers: RKSimon, craig.topper, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62806
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364419
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 26 Jun 2019 12:19:39 +0000 (12:19 +0000)]
[X86] X86DAGToDAGISel::matchBitExtract(): pattern b: truncation awareness
Summary:
(Not so) boringly identical to pattern a (D62786)
Not yet sure how do deal with the last pattern c.
Reviewers: RKSimon, craig.topper, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364418
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 26 Jun 2019 12:19:11 +0000 (12:19 +0000)]
[X86] X86DAGToDAGISel::matchBitExtract(): pattern a: truncation awareness
Summary:
Finally tying up loose ends here.
The problem is quite simple:
If we have pattern `(x >> start) & (1 << nbits) - 1`,
and then truncate the result, that truncation will be propagated upwards,
into the `and`. And that isn't currently handled.
I'm only fixing pattern `a` here,
the same fix will be needed for patterns `b`/`c` too.
I *think* this isn't missing any extra legality checks,
since we only look past truncations. Similary, i don't think
we can get any other truncation there other than i64->i32.
Reviewers: craig.topper, RKSimon, spatel
Reviewed By: craig.topper
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364417
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Wed, 26 Jun 2019 12:13:13 +0000 (12:13 +0000)]
Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."
Breaks sanitizers:
libFuzzer :: cxxstring.test
libFuzzer :: memcmp.test
libFuzzer :: recommended-dictionary.test
libFuzzer :: strcmp.test
libFuzzer :: value-profile-mem.test
libFuzzer :: value-profile-strcmp.test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364416
91177308-0d34-0410-b5e6-
96231b3b80d8
Chen Zheng [Wed, 26 Jun 2019 12:02:43 +0000 (12:02 +0000)]
[HardwareLoops] NFC - move loop with irreducible control flow checking logic to HarewareLoopInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364415
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Wed, 26 Jun 2019 11:56:38 +0000 (11:56 +0000)]
Fix the build after r364401
It was failing with:
/b/s/w/ir/cache/builder/src/third_party/llvm/llvm/lib/Target/X86/X86ISelLowering.cpp:18772:66:
error: call of overloaded 'makeArrayRef(<brace-enclosed initializer list>)' is ambiguous
scaleShuffleMask<int>(Scale, makeArrayRef<int>({ 0, 2, 1, 3 }), Mask);
^
/b/s/w/ir/cache/builder/src/third_party/llvm/llvm/lib/Target/X86/X86ISelLowering.cpp:18772:66: note: candidates are:
In file included from /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/CodeGen/MachineFunction.h:20:0,
from /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/CodeGen/CallingConvLower.h:19,
from /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/lib/Target/X86/X86ISelLowering.h:17,
from /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/lib/Target/X86/X86ISelLowering.cpp:14:
/b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/ADT/ArrayRef.h:480:15:
note: llvm::ArrayRef<T> llvm::makeArrayRef(const std::vector<_RealType>&) [with T = int]
ArrayRef<T> makeArrayRef(const std::vector<T> &Vec) {
^
/b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/ADT/ArrayRef.h:485:37:
note: llvm::ArrayRef<T> llvm::makeArrayRef(const llvm::ArrayRef<T>&) [with T = int]
template <typename T> ArrayRef<T> makeArrayRef(const ArrayRef<T> &Vec) {
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364414
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Wed, 26 Jun 2019 11:50:18 +0000 (11:50 +0000)]
[ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline.
This allows later passes (in particular InstCombine) to optimize more
cases.
One that's important to us is `memcmp(p, q, constant) < 0` and memcmp(p, q, constant) > 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364412
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Wed, 26 Jun 2019 11:44:54 +0000 (11:44 +0000)]
gn build: Merge r364387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364411
91177308-0d34-0410-b5e6-
96231b3b80d8
James Henderson [Wed, 26 Jun 2019 11:42:03 +0000 (11:42 +0000)]
[docs][llvm-symbolizer] Improve llvm-symbolizer documentation
As detailed in https://bugs.llvm.org/show_bug.cgi?id=42253, there were a
number of issues in the llvm-symbolizer documentation. This patch fixes
them by:
1. Adding [addresses...] to the synopsis, and matching the formatting
of other tools.
2. Rewriting the description to fix grammar issues and mention other
usage options.
3. Rewriting the examples to be easier to read.
4. Re-ordering the options into alphabetical order.
5. Improving the text of some of the option descriptions, and adding
some examples to individual options.
6. Splitting the Mach-O options into a separate section of the
document.
7. Standardizing on double dashes for long options throughout the file.
8. Adding a reference to the llvm-addr2line document.
Reviewed by: mtrent, ikudrin
Differential Revision: https://reviews.llvm.org/D63651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364410
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Wed, 26 Jun 2019 11:35:28 +0000 (11:35 +0000)]
gn build: Merge r364386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364409
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Wed, 26 Jun 2019 11:33:56 +0000 (11:33 +0000)]
gn build: Merge r364389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364408
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 26 Jun 2019 11:21:09 +0000 (11:21 +0000)]
[X86][AVX] combineExtractSubvector - 'little to big' extract_subvector(bitcast()) support
Ideally this needs to be a generic combine in DAGCombiner::visitEXTRACT_SUBVECTOR but there's some nasty regressions in aarch64 due to neon shuffles not handling bitcasts at all.....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364407
91177308-0d34-0410-b5e6-
96231b3b80d8
Djordje Todorovic [Wed, 26 Jun 2019 11:19:26 +0000 (11:19 +0000)]
[IR/DIVar] Add the flag for params that have unmodified value
Introduce the debug info flag that indicates that a parameter has unchanged
value throughout a function. This info will be used to emit the expressions
with DW_OP_entry_value.
([4/13] Introduce the debug entry values.)
Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>
Differential Revision: https://reviews.llvm.org/D58034
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364406
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 26 Jun 2019 11:17:38 +0000 (11:17 +0000)]
[DAGCombine] visitEXTRACT_SUBVECTOR - add TODO for extract_subvector(bitcast()) support
We support 'big to little' (e.g. extract_subvector(v16i8 bitcast(v2i64))) but not 'little to big' cases (e.g. extract_subvector(v2i64 bitcast(v16i8)))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364405
91177308-0d34-0410-b5e6-
96231b3b80d8
Mikhail Maltsev [Wed, 26 Jun 2019 10:48:40 +0000 (10:48 +0000)]
[ARM] Handle fixup_arm_pcrel_9 correctly on big-endian targets
Summary:
The getFixupKindContainerSizeBytes function returns the size of the
instruction containing a given fixup. Currently fixup_arm_pcrel_9 is
not handled in this function, this causes an assertion failure in
the debug build and incorrect codegen in the release build.
This patch fixes the problem.
Reviewers: ostannard, simon_tatham
Reviewed By: ostannard
Subscribers: javed.absar, kristof.beyls, hiraditya, pbarrio, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63778
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364404
91177308-0d34-0410-b5e6-
96231b3b80d8
Lewis Revill [Wed, 26 Jun 2019 10:35:58 +0000 (10:35 +0000)]
[RISCV] Add pseudo instruction for calls with explicit register
This patch adds the PseudoCALLReg instruction which allows using an
explicit register operand as the destination for the return address.
GCC can successfully parse this form of the call instruction, which
would be used for calls to functions which do not use ra as the return
address register, such as the __riscv_save libcalls. This patch forms
the first part of an implementation of -msave-restore for RISC-V.
Differential Revision: https://reviews.llvm.org/D62685
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364403
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 26 Jun 2019 09:50:11 +0000 (09:50 +0000)]
[X86][AVX] truncateVectorWithPACK - avoid bitcasted shuffles
truncateVectorWithPACK is often used in conjunction with ComputeNumSignBits which struggles when peeking through bitcasts.
This fix tries to avoid bitcast(shuffle(bitcast())) patterns in the 256-bit 64-bit sublane shuffles so we can still see through at least until lowering when the shuffles will need to be bitcasted to widen the shuffle type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364401
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Wed, 26 Jun 2019 09:16:57 +0000 (09:16 +0000)]
[LoopUnroll] Add support for loops with exiting headers and uncond latches.
This patch generalizes the UnrollLoop utility to support loops that exit
from the header instead of the latch. Usually, LoopRotate would take care
of must of those cases, but in some cases (e.g. -Oz), LoopRotate does
not kick in.
Codesize impact looks relatively neutral on ARM64 with -Oz + LTO.
Program master patch diff
External/S.../CFP2006/447.dealII/447.dealII 629060.00 627676.00 -0.2%
External/SPEC/CINT2000/176.gcc/176.gcc
1245916.00
1244932.00 -0.1%
MultiSourc...Prolangs-C/simulator/simulator 86100.00 86156.00 0.1%
MultiSourc...arks/Rodinia/backprop/backprop 66212.00 66252.00 0.1%
MultiSourc...chmarks/Prolangs-C++/life/life 67276.00 67312.00 0.1%
MultiSourc...s/Prolangs-C/compiler/compiler 69824.00 69788.00 -0.1%
MultiSourc...Prolangs-C/assembler/assembler 86672.00 86696.00 0.0%
Reviewers: efriedma, vsk, paquette
Reviewed By: paquette
Differential Revision: https://reviews.llvm.org/D61962
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364398
91177308-0d34-0410-b5e6-
96231b3b80d8
Chen Zheng [Wed, 26 Jun 2019 09:12:52 +0000 (09:12 +0000)]
[HardwareLoops] NFC - move loop with irreducible control flow checking logic to isHardwareLoopProfitable()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364397
91177308-0d34-0410-b5e6-
96231b3b80d8
Djordje Todorovic [Wed, 26 Jun 2019 08:35:43 +0000 (08:35 +0000)]
[TargetOption] Add option to ebanble the debug entry values
The option enables debug info about parameter's entry values.
([2/13] Introduce the debug entry values.)
Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>
Differential Revision: https://reviews.llvm.org/D60961
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364395
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 26 Jun 2019 08:17:05 +0000 (08:17 +0000)]
[NFC][InstCombine] Add shift amount reassociation tests (PR42391)
https://bugs.llvm.org/show_bug.cgi?id=42391
https://rise4fun.com/Alive/9E2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364393
91177308-0d34-0410-b5e6-
96231b3b80d8
Djordje Todorovic [Wed, 26 Jun 2019 07:31:09 +0000 (07:31 +0000)]
[Metadata] Add GNU extensions for call site DWARF symbols
As discussed on RFC
(http://lists.llvm.org/pipermail/llvm-dev/2019-February/130094.html), this
is set of patches that introduces debug information about call site and
call site parameters. Since the LLVM has portion of this support (dumping
DWARF 5 symbols for calls), we generate GNU extensions as well. All of that
will be restricted under an option.
([1/13] Introduce the debug entry values.)
Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>
Differential Revision: https://reviews.llvm.org/D60712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364385
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Wed, 26 Jun 2019 07:06:49 +0000 (07:06 +0000)]
[ExpandMemCmp] Honor prefer-vector-width.
Reviewers: gchatelet, echristo, spatel, atdt
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364384
91177308-0d34-0410-b5e6-
96231b3b80d8
Kai Luo [Wed, 26 Jun 2019 05:25:16 +0000 (05:25 +0000)]
[PowerPC] Fixed missing change flag of emitRLDICWhenLoweringJumpTables
PPCMIPeephole::emitRLDICWhenLoweringJumpTables should return a bool
value to indicate optimization is conducted or not.
Differential Revision: https://reviews.llvm.org/D63801
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364383
91177308-0d34-0410-b5e6-
96231b3b80d8
QingShan Zhang [Wed, 26 Jun 2019 05:12:53 +0000 (05:12 +0000)]
Teach the DAGCombine to fold this pattern(c1 and c2 is constant).
// fold (sext (select cond, c1, c2)) -> (select cond, sext c1, sext c2)
// fold (zext (select cond, c1, c2)) -> (select cond, zext c1, zext c2)
// fold (aext (select cond, c1, c2)) -> (select cond, sext c1, sext c2)
Sign extend the operands if it is any_extend, to keep the signess of the operands that, the other combine rule would apply. The any_extend is handled as zero extend for constants. i.e.
t1: i8 = select t0, Constant:i8<-1>, Constant:i8<0>
t2: i64 = any_extend t1
-->
t3: i64 = select t0, Constant:i64<-1>, Constant:i64<0>
-->
t4: i64 = sign_extend_inreg t3
Differential Revision: https://reviews.llvm.org/D63318
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364382
91177308-0d34-0410-b5e6-
96231b3b80d8