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Marc-André Lureau [Wed, 30 Aug 2023 09:38:37 +0000 (13:38 +0400)]
ui/dbus: do not require PIXMAN
Implement a fallback path for region 2D update.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Marc-André Lureau [Wed, 30 Aug 2023 09:38:36 +0000 (13:38 +0400)]
ui/gtk: -display gtk requires PIXMAN
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Marc-André Lureau [Wed, 30 Aug 2023 09:38:35 +0000 (13:38 +0400)]
ui/spice: SPICE/QXL requires PIXMAN
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Marc-André Lureau [Wed, 30 Aug 2023 09:38:34 +0000 (13:38 +0400)]
ui/vnc: VNC requires PIXMAN
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Marc-André Lureau [Wed, 30 Aug 2023 09:38:33 +0000 (13:38 +0400)]
ui/gl: opengl doesn't require PIXMAN
The QEMU fallback covers the requirements. We still need the flags of
header inclusion with CONFIG_PIXMAN.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Marc-André Lureau [Wed, 30 Aug 2023 09:38:32 +0000 (13:38 +0400)]
vhost-user-gpu: skip VHOST_USER_GPU_UPDATE when !PIXMAN
This simply means that 2d drawing updates won't be handled, but 3d
should work.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Marc-André Lureau [Wed, 30 Aug 2023 09:38:31 +0000 (13:38 +0400)]
ui/console: when PIXMAN is unavailable, don't draw placeholder msg
When we can't draw text, simply show a blank display.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Marc-André Lureau [Wed, 30 Aug 2023 09:38:30 +0000 (13:38 +0400)]
virtio-gpu: replace PIXMAN for region/rect test
Use a simpler implementation for rectangle geometry & intersect, drop
the need for (more complex) PIXMAN functions.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Marc-André Lureau [Wed, 30 Aug 2023 09:38:29 +0000 (13:38 +0400)]
qmp/hmp: disable screendump if PIXMAN is missing
The command requires color conversion and line-by-line feeding. We could
have a simple fallback for simple formats though.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Marc-André Lureau [Wed, 30 Aug 2023 09:38:28 +0000 (13:38 +0400)]
ui/vc: console-vc requires PIXMAN
Add stubs for the fallback paths.
get_vc() now returns NULL by default if !PIXMAN.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Marc-André Lureau [Tue, 5 Sep 2023 19:18:08 +0000 (23:18 +0400)]
ui/console: allow to override the default VC
If a display is backed by a specialized VC, allow to override the
default "vc:80Cx24C".
As suggested by Paolo, if the display doesn't implement a VC (get_vc()
returns NULL), use a fallback that will use a muxed console on stdio.
This changes the behaviour of "qemu -display none", to create a muxed
serial/monitor by default (on TTY & not daemonized).
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Marc-André Lureau [Wed, 18 Oct 2023 13:16:32 +0000 (17:16 +0400)]
vl: move display early init before default devices
The next commit needs to have the display registered itself before
creating the default VCs.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Marc-André Lureau [Wed, 25 Oct 2023 13:21:17 +0000 (17:21 +0400)]
vl: simplify display_remote logic
Bump the display_remote variable when the -vnc option is parsed, just
like -spice.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Marc-André Lureau [Wed, 25 Oct 2023 13:05:08 +0000 (17:05 +0400)]
qemu-options: define -vnc only #ifdef CONFIG_VNC
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Marc-André Lureau [Wed, 25 Oct 2023 12:52:56 +0000 (16:52 +0400)]
vl: drop needless -spice checks
Since commit
5324e3e958e ("qemu-options: define -spice only #ifdef
CONFIG_SPICE"), it is unnecessary to check at runtime for "-spice"
option.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Marc-André Lureau [Wed, 25 Oct 2023 12:15:24 +0000 (16:15 +0400)]
ui: add pixman-minimal.h
This is a tiny subset of PIXMAN API that is used pervasively in QEMU
codebase to manage images and identify the underlying format.
It doesn't seems worth to wrap this in a QEMU-specific API.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Marc-André Lureau [Wed, 30 Aug 2023 09:38:26 +0000 (13:38 +0400)]
ui: compile out some qemu-pixman functions when !PIXMAN
Those functions require the PIXMAN library.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Marc-André Lureau [Wed, 25 Oct 2023 12:04:45 +0000 (16:04 +0400)]
build-sys: drop needless warning pragmas for old pixman
Since commit
236f282c1c7 ("configure: check for pixman-1 version"), QEMU
requires >= 0.21.8.
Suggested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Marc-André Lureau [Wed, 30 Aug 2023 09:38:25 +0000 (13:38 +0400)]
build-sys: add a "pixman" feature
For now, pixman is mandatory, but we set config_host.h and Kconfig.
Once compilation is fixed, "pixman" will become actually optional.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Stefan Hajnoczi [Tue, 7 Nov 2023 07:01:17 +0000 (15:01 +0800)]
Merge tag 'pull-pa-
20231106' of https://gitlab.com/rth7680/qemu into staging
target/hppa: Implement PA2.0 instructions
hw/hppa: Map astro chip 64-bit I/O mem
hw/hppa: Turn on 64-bit cpu for C3700
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# gpg: Signature made Tue 07 Nov 2023 11:00:01 HKT
# gpg: using RSA key
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# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-pa-
20231106' of https://gitlab.com/rth7680/qemu: (85 commits)
hw/hppa: Allow C3700 with 64-bit and B160L with 32-bit CPU only
hw/hppa: Turn on 64-bit CPU for C3700 machine
hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memory
hw/pci-host/astro: Map Astro chip into 64-bit I/O memory region
target/hppa: Improve interrupt logging
target/hppa: Update IIAOQ, IIASQ for pa2.0
target/hppa: Create raise_exception_with_ior
target/hppa: Add unwind_breg to CPUHPPAState
target/hppa: Clear upper bits in mtctl for pa1.x
target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system
target/hppa: Add pa2.0 cpu local tlb flushes
target/hppa: Implement pa2.0 data prefetch instructions
linux-user/hppa: Drop EXCP_DUMP from handled exceptions
hw/hppa: Translate phys addresses for the cpu
include/hw/elf: Remove truncating signed casts
target/hppa: Return zero for r0 from load_gpr
target/hppa: Precompute zero into DisasContext
target/hppa: Fix interruption based on default PSW
target/hppa: Implement PERMH
target/hppa: Implement MIXH, MIXW
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Tue, 7 Nov 2023 03:08:16 +0000 (11:08 +0800)]
Merge tag 'pull-riscv-to-apply-
20231107' of https://github.com/alistair23/qemu into staging
Third RISC-V PR for 8.2
* Rename ext_icboz to ext_zicboz
* Rename ext_icbom to ext_zicbom
* Rename ext_icsr to ext_zicsr
* Rename ext_ifencei to ext_zifencei
* Add RISC-V Virtual IRQs and IRQ filtering support
* Change default linux-user cpu to 'max'
* Update 'virt' machine core limit
* Add query-cpu-model-expansion API
* Rename epmp to smepmp and expose the extension
* Clear pmp/smepmp bits on reset
* Ignore pmp writes when RW=01
* Support zicntr/zihpm flags and disable support
* Correct CSR_MSECCFG operations
* Update mail address for Weiwei Li
* Update RISC-V vector crypto to ratified v1.0.0
* Clear the Ibex/OpenTitan SPI interrupts even if disabled
* Set the OpenTitan priv to 1.12.0
* Support discontinuous PMU counters
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# gpg: Signature made Tue 07 Nov 2023 10:28:49 HKT
# gpg: using RSA key
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# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-
20231107' of https://github.com/alistair23/qemu: (49 commits)
docs/about/deprecated: Document RISC-V "pmu-num" deprecation
target/riscv: Add "pmu-mask" property to replace "pmu-num"
target/riscv: Use existing PMU counter mask in FDT generation
target/riscv: Don't assume PMU counters are continuous
target/riscv: Propagate error from PMU setup
target/riscv: cpu: Set the OpenTitan priv to 1.12.0
hw/ssi: ibex_spi_host: Clear the interrupt even if disabled
disas/riscv: Replace TABs with space
disas/riscv: Add support for vector crypto extensions
disas/riscv: Add rv_codec_vror_vi for vror.vi
disas/riscv: Add rv_fmt_vd_vs2_uimm format
target/riscv: Move vector crypto extensions to riscv_cpu_extensions
target/riscv: Expose Zvks[c|g] extnesion properties
target/riscv: Add cfg properties for Zvks[c|g] extensions
target/riscv: Expose Zvkn[c|g] extnesion properties
target/riscv: Add cfg properties for Zvkn[c|g] extensions
target/riscv: Expose Zvkb extension property
target/riscv: Replace Zvbb checking by Zvkb
target/riscv: Add cfg property for Zvkb extension
target/riscv: Expose Zvkt extension property
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Tue, 7 Nov 2023 03:05:37 +0000 (11:05 +0800)]
Merge tag 'pull-tcg-
20231106' of https://gitlab.com/rth7680/qemu into staging
util: Add cpuinfo for loongarch64
tcg/loongarch64: Use cpuinfo.h
tcg/loongarch64: Improve register allocation for INDEX_op_qemu_ld_a*_i128
host/include/loongarch64: Add atomic16 load and store
tcg: Move expanders out of line
tcg/mips: Always implement movcond
tcg/mips: Implement neg opcodes
tcg/loongarch64: Implement neg opcodes
tcg: Make movcond and neg required opcodes
tcg: Optimize env memory operations
tcg: Canonicalize sub of immediate to add
tcg/sparc64: Implement tcg_out_extrl_i64_i32
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# gpg: Signature made Tue 07 Nov 2023 10:47:25 HKT
# gpg: using RSA key
7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-
20231106' of https://gitlab.com/rth7680/qemu: (35 commits)
tcg/sparc64: Implement tcg_out_extrl_i64_i32
tcg/optimize: Canonicalize sub2 with constants to add2
tcg/optimize: Canonicalize subi to addi during optimization
tcg: Canonicalize subi to addi during opcode generation
tcg/optimize: Split out arg_new_constant
tcg: Eliminate duplicate env store operations
tcg/optimize: Optimize env memory operations
tcg/optimize: Split out cmp_better_copy
tcg/optimize: Pipe OptContext into reset_ts
tcg: Don't free vector results
tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}
tcg/loongarch64: Implement neg opcodes
tcg/mips: Implement neg opcodes
tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}
tcg/mips: Always implement movcond
tcg/mips: Split out tcg_out_setcond_int
tcg: Move tcg_temp_free_* out of line
tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of line
tcg: Move tcg_constant_* out of line
tcg: Unexport tcg_gen_op*_{i32,i64}
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Helge Deller [Wed, 25 Oct 2023 18:10:21 +0000 (20:10 +0200)]
hw/hppa: Allow C3700 with 64-bit and B160L with 32-bit CPU only
Prevent that users try to boot a 64-bit only C3700 machine with a 32-bit
CPU, and to boot a 32-bit only B160L machine with a 64-bit CPU.
Signed-off-by: Helge Deller <deller@gmx.de>
Helge Deller [Sat, 21 Oct 2023 11:40:55 +0000 (13:40 +0200)]
hw/hppa: Turn on 64-bit CPU for C3700 machine
Signed-off-by: Helge Deller <deller@gmx.de>
Helge Deller [Wed, 25 Oct 2023 19:46:39 +0000 (21:46 +0200)]
hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memory
The CPU HPA is in the high F-region on PA2.0 CPUs, so use F_EXTEND()
to trigger interrupt request at the right CPU HPA address.
Note that the cpu_hpa value comes out of the IRT, which doesn't store the
higher addresss bits.
Signed-off-by: Helge Deller <deller@gmx.de>
Helge Deller [Sat, 21 Oct 2023 13:41:02 +0000 (15:41 +0200)]
hw/pci-host/astro: Map Astro chip into 64-bit I/O memory region
Map Astro into high F-region and add alias for 32-bit OS in low region.
Signed-off-by: Helge Deller <deller@gmx.de>
Richard Henderson [Wed, 1 Nov 2023 17:33:58 +0000 (10:33 -0700)]
target/hppa: Improve interrupt logging
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 27 Oct 2023 11:10:45 +0000 (04:10 -0700)]
target/hppa: Update IIAOQ, IIASQ for pa2.0
These registers have a different format for pa2.0.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 27 Oct 2023 10:35:57 +0000 (03:35 -0700)]
target/hppa: Create raise_exception_with_ior
Handle pa2.0 logic for filling in ISR+IOR.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 27 Oct 2023 09:46:44 +0000 (02:46 -0700)]
target/hppa: Add unwind_breg to CPUHPPAState
Fill in the insn_start value during form_gva, and copy
it out to the env field in hppa_restore_state_to_opc.
The value is not yet consumed.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Helge Deller [Fri, 27 Oct 2023 04:49:48 +0000 (21:49 -0700)]
target/hppa: Clear upper bits in mtctl for pa1.x
Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 1 Nov 2023 16:56:42 +0000 (09:56 -0700)]
target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Helge Deller [Fri, 27 Oct 2023 04:41:41 +0000 (21:41 -0700)]
target/hppa: Add pa2.0 cpu local tlb flushes
The previous decoding misnamed the bit it called "local".
Other than the name, the implementation was correct for pa1.x.
Rename this field to "tlbe".
PA2.0 adds (a real) local bit to PxTLB, and also adds a range
of pages to flush in GR[b].
Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 27 Oct 2023 03:46:13 +0000 (20:46 -0700)]
target/hppa: Implement pa2.0 data prefetch instructions
These are aliased onto the normal integer loads to %g0.
Since we don't emulate caches, prefetch is a nop.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 20 Oct 2023 20:07:21 +0000 (13:07 -0700)]
linux-user/hppa: Drop EXCP_DUMP from handled exceptions
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 18 Sep 2023 01:17:31 +0000 (18:17 -0700)]
hw/hppa: Translate phys addresses for the cpu
Hack the machine to use pa2.0 physical layout when required,
using the PSW.W=0 absolute to physical mapping.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 19 Sep 2023 14:25:54 +0000 (16:25 +0200)]
include/hw/elf: Remove truncating signed casts
There's nothing about elf that specifically requires signed vs unsigned.
This is very much a target-specific preference.
In the meantime, casting low and high from uint64_t back to Elf_SWord
to uint64_t discards high bits that might have been set by translate_fn.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 18 Oct 2023 17:34:13 +0000 (10:34 -0700)]
target/hppa: Return zero for r0 from load_gpr
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 18 Oct 2023 17:24:33 +0000 (10:24 -0700)]
target/hppa: Precompute zero into DisasContext
Reduce the number of times we look for the constant 0.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Helge Deller [Tue, 17 Oct 2023 09:36:37 +0000 (11:36 +0200)]
target/hppa: Fix interruption based on default PSW
The default PSW is set by the operating system with the PDC_PSW
firmware call. Use that setting to decide if wide mode is to be
enabled for interruptions and EIRR usage.
Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 21 Sep 2023 10:07:22 +0000 (12:07 +0200)]
target/hppa: Implement PERMH
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 21 Sep 2023 07:37:10 +0000 (09:37 +0200)]
target/hppa: Implement MIXH, MIXW
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 21 Sep 2023 07:15:25 +0000 (09:15 +0200)]
target/hppa: Implement HSHLADD, HSHRADD
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 21 Sep 2023 06:56:04 +0000 (08:56 +0200)]
target/hppa: Implement HSHL, HSHR
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 20 Sep 2023 15:11:06 +0000 (17:11 +0200)]
target/hppa: Implement HAVG
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 20 Sep 2023 14:30:41 +0000 (16:30 +0200)]
target/hppa: Implement HSUB
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 20 Sep 2023 11:50:01 +0000 (13:50 +0200)]
target/hppa: Implement HADD
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 18 Oct 2023 04:49:54 +0000 (21:49 -0700)]
target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 18 Oct 2023 04:47:02 +0000 (21:47 -0700)]
target/hppa: Use tcg_temp_new_i64 not tcg_temp_new
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 26 Oct 2023 17:42:21 +0000 (10:42 -0700)]
target/hppa: Adjust vmstate_env for pa2.0 tlb
Split out the tlb to a subsection so that it can be separately
versioned -- the format is only partially following the architecture
and is partially guided by the qemu implementation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 18 Oct 2023 04:42:55 +0000 (21:42 -0700)]
target/hppa: Remove remaining TARGET_REGISTER_BITS redirections
The conversions to/from i64 can be eliminated entirely,
folding computation into adjacent operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 18 Oct 2023 04:31:08 +0000 (21:31 -0700)]
target/hppa: Remove most of the TARGET_REGISTER_BITS redirections
Remove all but those intended to change type to or from i64.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 18 Oct 2023 04:11:19 +0000 (21:11 -0700)]
target/hppa: Remove TARGET_REGISTER_BITS
Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 20 Oct 2023 17:04:22 +0000 (10:04 -0700)]
hw/hppa: Use uint32_t instead of target_ureg
The size of target_ureg is going to change.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 13 Oct 2023 00:55:12 +0000 (17:55 -0700)]
target/hppa: Implement IDTLBT, IITLBT
Rename the existing insert tlb helpers to emphasize that they
are for pa1.1 cpus. Implement a combined i/d tlb for pa2.0.
Still missing is the new 'P' tlb bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 20 Sep 2023 15:00:23 +0000 (17:00 +0200)]
target/hppa: Implement STDBY
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 20 Sep 2023 11:11:27 +0000 (13:11 +0200)]
target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 20 Sep 2023 10:44:23 +0000 (12:44 +0200)]
target/hppa: Implement SHRPD
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 20 Sep 2023 10:04:29 +0000 (12:04 +0200)]
target/hppa: Implement EXTRD
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 20 Sep 2023 09:44:17 +0000 (11:44 +0200)]
target/hppa: Implement DEPD, DEPDI
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 06:47:42 +0000 (23:47 -0700)]
target/hppa: Implement LDD, LDCD, LDDA, STD, STDA
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 05:25:30 +0000 (22:25 -0700)]
target/hppa: Decode ADDB double-word
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 05:06:04 +0000 (22:06 -0700)]
target/hppa: Decode CMPIB double-word
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 04:56:39 +0000 (21:56 -0700)]
target/hppa: Decode d for cmpb instructions
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 04:41:32 +0000 (21:41 -0700)]
target/hppa: Decode d for bb instructions
Manipulate the shift count so that the bit to be tested
is always placed at the MSB.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 04:25:44 +0000 (21:25 -0700)]
target/hppa: Decode d for sub instructions
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 03:51:13 +0000 (20:51 -0700)]
target/hppa: Decode d for add instructions
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 03:40:23 +0000 (20:40 -0700)]
target/hppa: Decode d for cmpclr instructions
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 03:32:37 +0000 (20:32 -0700)]
target/hppa: Decode d for unit instructions
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 03:21:14 +0000 (20:21 -0700)]
target/hppa: Decode d for logical instructions
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 04:06:49 +0000 (21:06 -0700)]
target/hppa: Remove TARGET_HPPA64
Allow both user-only and system mode to run pa2.0 cpus.
Avoid creating a separate qemu-system-hppa64 binary;
force the qemu-hppa binary to use TARGET_ABI32.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 18 Oct 2023 03:48:38 +0000 (20:48 -0700)]
target/hppa: Drop attempted gdbstub support for hppa64
There is no support for hppa64 in gdb. Any attempt to provide the
data for the larger hppa64 registers results in an error from gdb.
Mask CR_SAR writes to the width of the register: 5 or 6 bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 17 Oct 2023 21:09:58 +0000 (14:09 -0700)]
linux-user/hppa: Fixes for TARGET_ABI32
Avoid target_ulong and use abi_* types.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 02:52:46 +0000 (19:52 -0700)]
target/hppa: Pass d to do_unit_cond
Hoist the resolution of d up one level above do_unit_cond.
All computations are logical, and are simplified by using a mask of the
correct width, after which the result may be compared with zero.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 02:34:39 +0000 (19:34 -0700)]
target/hppa: Pass d to do_sed_cond
Hoist the resolution of d up one level above do_sed_cond.
The MOVB comparison and the existing shift/extract/deposit
are all 32-bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 02:30:10 +0000 (19:30 -0700)]
target/hppa: Pass d to do_log_cond
Hoist the resolution of d up one level above do_log_cond.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 02:28:12 +0000 (19:28 -0700)]
target/hppa: Pass d to do_sub_cond
Hoist the resolution of d up one level above do_sub_cond.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 02:26:15 +0000 (19:26 -0700)]
target/hppa: Pass d to do_cond
Hoist the resolution of d up one level above do_cond.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Helge Deller [Mon, 16 Oct 2023 12:43:18 +0000 (14:43 +0200)]
target/hppa: sar register allows only 5 bits on 32-bit CPU
The sar shift amount register is limited to 5 bits when running
a 32-bit CPU. Strip off the remaining bits.
The interesting part is, that this register allows to detect at runtime
if a physical CPU is capable to execute PA2.0 (64-bit) instructions.
Signed-off-by: Helge Deller <deller@gmx.de>
Richard Henderson [Fri, 27 Oct 2023 02:03:34 +0000 (19:03 -0700)]
target/hppa: Mask inputs in copy_iaoq_entry
Ensure that the destination is always a valid GVA offset.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 27 Oct 2023 01:55:54 +0000 (18:55 -0700)]
target/hppa: Use copy_iaoq_entry for link in do_ibranch
We need to make sure the link is masked properly along the
use_nullify_skip path. The other three settings of a link
register already use this.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 27 Oct 2023 01:51:25 +0000 (18:51 -0700)]
target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb]
This will be how we ensure that the IAOQ is always
valid per PSW.W, therefore all stores to these two
variables must be done with this function.
Use third argument -1 if the destination is always dynamic,
and fourth argument NULL if the destination is always static.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 27 Oct 2023 01:34:01 +0000 (18:34 -0700)]
target/hppa: Pass DisasContext to copy_iaoq_entry
Interface change only, no functional effect.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 16 Sep 2023 23:52:51 +0000 (16:52 -0700)]
target/hppa: Fix hppa64 addressing
In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W == 0.
In space_select, the bits that choose the space depend on PSW_W.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 19 Sep 2023 13:43:57 +0000 (15:43 +0200)]
target/hppa: Adjust hppa_cpu_dump_state for hppa64
Dump all 64 bits for pa2.0 and low 32 bits for pa1.x.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 21:54:16 +0000 (14:54 -0700)]
target/hppa: Handle absolute addresses for pa2.0
With pa2.0, absolute addresses are not the same as physical addresses,
and undergo a transformation based on PSW_W.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 21 Sep 2023 08:13:35 +0000 (10:13 +0200)]
target/hppa: Update cpu_hppa_get/put_psw for hppa64
With 64-bit registers, there are 16 carry bits in the PSW.
Clear reserved bits based on cpu revision.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 18 Sep 2023 01:42:27 +0000 (18:42 -0700)]
target/hppa: Implement hppa_cpu_class_by_name
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 18 Sep 2023 01:38:59 +0000 (18:38 -0700)]
target/hppa: Implement cpu_list
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 13 Oct 2023 00:46:55 +0000 (17:46 -0700)]
target/hppa: Make HPPA_BTLB_ENTRIES variable
Depend on hppa_is_pa20.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 22:31:47 +0000 (15:31 -0700)]
target/hppa: Introduce TYPE_HPPA64_CPU
Prepare for the qemu binary supporting both pa10 and pa20
at the same time.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 19 Sep 2023 14:07:14 +0000 (16:07 +0200)]
target/hppa: Fix extrw and depw with sar for hppa64
These are 32-bit operations regardless of processor.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 17 Oct 2023 23:39:47 +0000 (16:39 -0700)]
target/hppa: Fix bb_sar for hppa64
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 17 Oct 2023 23:16:03 +0000 (16:16 -0700)]
target/hppa: Fix do_add, do_sub for hppa64
Select the proper carry bit for input to the arithmetic
and for output for the condition.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 16 Sep 2023 23:28:23 +0000 (16:28 -0700)]
target/hppa: Fix trans_ds for hppa64
This instruction always uses the input carry from bit 32,
but produces all 16 output carry bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 16 Sep 2023 23:22:14 +0000 (16:22 -0700)]
target/hppa: Truncate rotate count in trans_shrpw_sar
When forcing rotate by i32, the shift count must be as well.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 16 Sep 2023 23:20:28 +0000 (16:20 -0700)]
target/hppa: Fix load in do_load_32
The destination is TCGv_i32, so use tcg_gen_qemu_ld_i32
not tcg_gen_qemu_ld_reg.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 16 Sep 2023 23:19:27 +0000 (16:19 -0700)]
target/hppa: Fix hppa64 case in machine.c
Typo of VMSTATE_UINTTR_V and VMSTATE_UINTTR_ARRAY_V macros.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 20 Sep 2023 09:47:02 +0000 (11:47 +0200)]
target/hppa: Remove load_const
Replace with tcg_constant_reg.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 17 Sep 2023 04:05:03 +0000 (21:05 -0700)]
target/hppa: Remove get_temp_tl
Replace with tcg_temp_new_tl without recording into ctx.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>