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Jonas Devlieghere [Tue, 23 Oct 2018 00:32:22 +0000 (00:32 +0000)]
[dsymutil] Improve error reporting when we cannot create output file.
Before this patch we were returning an empty string in case we couldn't
create the output file. Now we return an expected string so we can
return and print the proper issue. We now return errors instead of bools
and defer printing to the call site.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344983
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Heejin Ahn [Tue, 23 Oct 2018 00:28:14 +0000 (00:28 +0000)]
[WebAssembly] Fix assembly printing of br_table
Summary: In `br_table's stack version asm string, \t was missing.
Reviewers: aardappel
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53516
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344981
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Wouter van Oortmerssen [Tue, 23 Oct 2018 00:12:49 +0000 (00:12 +0000)]
[WebAssembly] Added test for inline assembly roundtrip.
Summary:
Due to previous work to make WebAssembly MC by default stack-only
inline assembly now "just works" (previously it didn't since it had
no way to know types of registers), so no further work required.
So far we only have tests (in inline-asm.ll) which test with
non-existing instructions, so this adds a test that roundtrips
both the inline assembly and its surrounding code thru the assembler.
Reviewers: dschuff, sunfish
Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits
Differential Revision: https://reviews.llvm.org/D52914
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344977
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Saleem Abdulrasool [Mon, 22 Oct 2018 23:34:24 +0000 (23:34 +0000)]
X86: fix a comment copy-paste issue (NFC)
The comment was copy-pasted but not updated. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344973
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Craig Topper [Mon, 22 Oct 2018 23:14:55 +0000 (23:14 +0000)]
[X86] Remove unused entries from the X86ProcFamily enum. Add a note to discourage creation of new enum entries.
As we've learned multiple times, a coarse grained enum like this is not scalable and we should be migrating away from it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344972
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Leonard Chan [Mon, 22 Oct 2018 23:08:40 +0000 (23:08 +0000)]
[Intrinsic] Unigned Saturation Addition Intrinsic
Add an intrinsic that takes 2 integers and perform unsigned saturation
addition on them.
This is a part of implementing fixed point arithmetic in clang where some of
the more complex operations will be implemented as intrinsics.
Differential Revision: https://reviews.llvm.org/D53340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344971
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Matthias Braun [Mon, 22 Oct 2018 22:52:23 +0000 (22:52 +0000)]
X86: Do not optimize branches with undef eflags inputs
analyzeBranch()/insertBranch() etc. do not properly deal with an undef
flag on the eflags input and used to produce invalid MIR. I don't see
this ever affecting real world inputs (I don't think it is possible to
produce undef flags with llvm IR), so I simply changed the code to bail
out in this case.
rdar://
42122367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344970
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Sanjay Patel [Mon, 22 Oct 2018 22:50:27 +0000 (22:50 +0000)]
[Reassociate] remove bogus tests; NFC
I was trying to provide test coverage for D53533
with rL344964, but these don't do it...and I don't
think they add any value, so deleting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344969
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Reid Kleckner [Mon, 22 Oct 2018 22:29:09 +0000 (22:29 +0000)]
[MC] Shrink MCAsmParser by grouping bools, add const, NFC
I was considering adding another boolean here. I standardized on bools
since they allow default member initializers in the class definition.
This makes ShowParsedOperands protected instead of private, but that's
probably fine.
Reduce the SmallVector size while we're at it, since the common case is
that there is never a pending error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344967
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Simon Pilgrim [Mon, 22 Oct 2018 22:26:00 +0000 (22:26 +0000)]
[ARM] Regenerate reverse shuffle costs
Came about while cleaning up general shuffle costs for PR39368
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344966
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Craig Topper [Mon, 22 Oct 2018 22:14:05 +0000 (22:14 +0000)]
Recommit r344877 "[X86] Stop promoting integer loads to vXi64"
I've included a fix to DAGCombiner::ForwardStoreValueToDirectLoad that I believe will prevent the previous miscompile.
Original commit message:
Theoretically this was done to simplify the amount of isel patterns that were needed. But it also meant a substantial number of our isel patterns have to match an explicit bitcast. By making the vXi32/vXi16/vXi8 types legal for loads, DAG combiner should be able to change the load type to rem
I had to add some additional plain load instruction patterns and a few other special cases, but overall the isel table has reduced in size by ~12000 bytes. So it looks like this promotion was hurting us more than helping.
I still have one crash in vector-trunc.ll that I'm hoping @RKSimon can help with. It seems to relate to using getTargetConstantFromNode on a load that was shrunk due to an extract_subvector combine after the constant pool entry was created. So we end up decoding more mask elements than the lo
I'm hoping this patch will simplify the number of patterns needed to remove the and/or/xor promotion.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits, RKSimon
Differential Revision: https://reviews.llvm.org/D53306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344965
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Sanjay Patel [Mon, 22 Oct 2018 22:04:13 +0000 (22:04 +0000)]
[Reassociate] add vector tests with undef elements; NFC
Also, regenerate checks for these files. We should do better
on the vector tests by using the PatternMatch API instead of
BinaryOperator::isNot/isNeg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344964
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Thomas Lively [Mon, 22 Oct 2018 21:55:26 +0000 (21:55 +0000)]
[WebAssembly][NFC] Remove WebAssemblyStackifier TableGen backend
Summary:
Replace its functionality with a TableGen InstrInfo relational
instruction mapping. Although arguably more complex than the TableGen
backend, the relational mapping is a smaller maintenance burden than a
TableGen backend.
Reviewers: aardappel, aheejin, dschuff
Subscribers: mgorny, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53307
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344962
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Vedant Kumar [Mon, 22 Oct 2018 21:44:21 +0000 (21:44 +0000)]
[DWARF] Use a function-local offset for AT_call_return_pc
Logs provided by @stella.stamenova indicate that on Linux, lldb adds a
spurious slide offset to the return PC it loads from AT_call_return_pc
attributes (see the list thread: "[PATCH] D50478: Add support for
artificial tail call frames").
This patch side-steps the issue by getting rid of the load address
calculation in lldb's CallEdge::GetReturnPCAddress.
The idea is to have the DWARF writer emit function-local offsets to the
instruction after a call. I.e. return-pc = label-after-call-insn -
function-entry. LLDB can simply add this offset to the base address of a
function to get the return PC.
Differential Revision: https://reviews.llvm.org/D53469
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344960
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Sanjay Patel [Mon, 22 Oct 2018 21:37:02 +0000 (21:37 +0000)]
[Reassociate] add 'using namespace' to reduce bloat; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344959
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Lang Hames [Mon, 22 Oct 2018 21:17:56 +0000 (21:17 +0000)]
[ORC] Guard access to the MemMgrs vector in RTDyldObjectLinkingLayer.
Otherwise we can end up with a data-race when linking concurrently.
This should fix an intermittent failure in the multiple-compile-threads-basic.ll
testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344956
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Sanjay Patel [Mon, 22 Oct 2018 21:11:15 +0000 (21:11 +0000)]
[x86] add test for PR25498 and complete checks; NFC
Might as well test the actual codegen instead of just the absence of crashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344955
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Tim Northover [Mon, 22 Oct 2018 20:38:13 +0000 (20:38 +0000)]
X86: add alias for pushfw/popfw in Intel mode
A while ago we changed pushf and popf in Intel mode to generate pushfq
and popfq. Unfortunately that left us with no way to get the 16-bit
encoding in Intel mode so this patch adds pushfw and popfw as aliases
there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344949
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Justin Bogner [Mon, 22 Oct 2018 19:51:31 +0000 (19:51 +0000)]
Reapply "[MachineCopyPropagation] Reimplement CopyTracker in terms of register units"
Recommits r342942, which was reverted in r343189, with a fix for an
issue where we would propagate unsafely if we defined only the upper
part of a register.
Original message:
Change the copy tracker to keep a single map of register units
instead of 3 maps of registers. This gives a very significant
compile time performance improvement to the pass. I measured a
30-40% decrease in time spent in MCP on x86 and AArch64 and much
more significant improvements on out of tree targets with more
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344942
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Teresa Johnson [Mon, 22 Oct 2018 19:06:42 +0000 (19:06 +0000)]
[hot-cold-split] Add opt remark on success
Summary: Emit optimization remark on successful hot cold split.
Reviewers: sebpop, hiraditya
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344938
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Simon Pilgrim [Mon, 22 Oct 2018 19:01:25 +0000 (19:01 +0000)]
Revert rL344931 from llvm/trunk: [X86][SSE] getTargetShuffleMaskIndices - allow opt-in support for whole undef shuffle mask elements
We can't safely assume that certain RawMask entries are UNDEF as most variable shuffles ignore non-index bits - PSHUFB only works on i8 elts so it'd be safe to use but I'm intending to come up with an alternative approach that works for all.
........
Enable this for PSHUFB constant mask decoding and remove the ConstantPool DecodePSHUFBMask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344937
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Simon Pilgrim [Mon, 22 Oct 2018 18:58:32 +0000 (18:58 +0000)]
Revert rL344933 from llvm/trunk: [X86][SSE] Tidyup DecodeVPERMILPMask shuffle mask decoding
We can't safely assume that certain RawMask entries are UNDEF as most variable shuffles ignore non-index bits.
........
Add support for UNDEF raw mask elements and remove the ConstantPool DecodeVPERMILPMask usage in X86ISelLowering.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344936
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Aaron Ballman [Mon, 22 Oct 2018 18:51:29 +0000 (18:51 +0000)]
Revert r344930 as it broke some of the bots on Windows.
http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/739
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344935
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Simon Pilgrim [Mon, 22 Oct 2018 18:35:13 +0000 (18:35 +0000)]
[X86][SSE] Tidyup DecodeVPERMILPMask shuffle mask decoding
Add support for UNDEF raw mask elements and remove the ConstantPool DecodeVPERMILPMask usage in X86ISelLowering.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344933
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Simon Pilgrim [Mon, 22 Oct 2018 18:09:02 +0000 (18:09 +0000)]
[X86][SSE] getTargetShuffleMaskIndices - allow opt-in support for whole undef shuffle mask elements
Enable this for PSHUFB constant mask decoding and remove the ConstantPool DecodePSHUFBMask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344931
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Joel E. Denny [Mon, 22 Oct 2018 18:00:49 +0000 (18:00 +0000)]
[SourceMgr][FileCheck] Obey -color by extending WithColor
While this change specifically targets FileCheck, it affects any tool
using the same SourceMgr facilities.
Previously, -color was documented in FileCheck's -help output, but
-color had no effect. Now, -color obeys its documentation: it forces
colors to be used in FileCheck diagnostics even when stderr is not a
terminal.
-color is especially helpful when combined with FileCheck's -v, which
can produce a long series of diagnostics that you might wish to pipe
to a pager, such as less -R. The WithColor extensions here will also
help to clean up color usage in FileCheck's annotated dump of input,
which is proposed in D52999.
Reviewed By: JDevlieghere
Differential Revision: https://reviews.llvm.org/D53419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344930
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Teresa Johnson [Mon, 22 Oct 2018 17:57:02 +0000 (17:57 +0000)]
[hot-cold-split] Add missing FileCheck invocations
Summary:
r344558 added some CHECK statements to split-cold-2.ll, but didn't add
any invocations of FileCheck. Add those here.
Reviewers: sebpop
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344928
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Fangrui Song [Mon, 22 Oct 2018 17:52:31 +0000 (17:52 +0000)]
[llvm-exegesis] Fix name lookup ambiguity in MSVC after 344922
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344927
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Simon Pilgrim [Mon, 22 Oct 2018 17:43:33 +0000 (17:43 +0000)]
[X86] getTargetConstantBitsFromNode - handle extraction from larger constant pool entries
First step towards removing X86ShuffleDecodeConstantPool usage from X86ISelLowering.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344924
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Fangrui Song [Mon, 22 Oct 2018 17:10:47 +0000 (17:10 +0000)]
[llvm-exegesis] Move namespace exegesis inside llvm::
Summary:
This allows simplifying references of llvm::foo with foo when the needs
come in the future.
Reviewers: courbet, gchatelet
Reviewed By: gchatelet
Subscribers: javed.absar, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D53455
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344922
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Craig Topper [Mon, 22 Oct 2018 16:59:24 +0000 (16:59 +0000)]
Revert r344877 "[X86] Stop promoting integer loads to vXi64"
Sam McCall reported miscompiles in some tensorflow code. Reverting while I try to figure out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344921
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Vedant Kumar [Mon, 22 Oct 2018 16:50:24 +0000 (16:50 +0000)]
[test] Relax test/Other/opt-hot-cold-split.ll
On some ARM bots, 'Target Pass Configuration' does not run after 'Target
Transform Info'. Relax this pipeline test to allow that.
This is the same fix as in r328167.
Bot URL: http://lab.llvm.org:8011/builders/clang-cmake-armv7-quick/builds/4611
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344919
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Andrea Di Biagio [Mon, 22 Oct 2018 16:28:07 +0000 (16:28 +0000)]
[llvm-mca] Remove a couple of using directives and a bunch of redundant namespace llvm prefixes. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344916
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Matt Arsenault [Mon, 22 Oct 2018 16:27:27 +0000 (16:27 +0000)]
DAG: Change behavior of fminnum/fmaxnum nodes
Introduce new versions that follow the IEEE semantics
to help with legalization that may need quieted inputs.
There are some regressions from inserting unnecessary
canonicalizes when these are matched from fast math
fcmp + select which should be fixed in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344914
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Zachary Turner [Mon, 22 Oct 2018 16:19:07 +0000 (16:19 +0000)]
Some cleanups to the native pdb plugin [NFC].
This is mostly some cleanup done in the process of implementing
some basic support for types. I tried to split up the patch a
bit to get some of the NFC portion of the patch out into a separate
commit, and this is the result of that. It moves some code around,
deletes some spurious namespace qualifications, removes some
unnecessary header includes, forward declarations, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344913
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Andrea Di Biagio [Mon, 22 Oct 2018 15:36:15 +0000 (15:36 +0000)]
[llvm-mca] Use llvm::ArrayRef in class SourceMgr. NFCI
Class SourceMgr now uses type ArrayRef<MCInst> to reference the
sequence of code from a "CodeRegion".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344911
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Simon Pilgrim [Mon, 22 Oct 2018 15:33:30 +0000 (15:33 +0000)]
[X86][SSE] getTargetShuffleMask - pull out repeated shuffle mask element size. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344910
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Aleksandr Urakov [Mon, 22 Oct 2018 15:30:48 +0000 (15:30 +0000)]
Revert "[PDB] Extend IPDBSession's interface to retrieve frame data"
This reverts commit
b5c7e2f9a4dbb34e3667c4bb4972735eadd3247a.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344909
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Sanjay Patel [Mon, 22 Oct 2018 15:26:27 +0000 (15:26 +0000)]
[InstCombine] add tests for shuffle+insert folds; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344908
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Guillaume Chatelet [Mon, 22 Oct 2018 15:06:10 +0000 (15:06 +0000)]
[llvm-exegesis] Crash when assembling invalid Operand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344907
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Guillaume Chatelet [Mon, 22 Oct 2018 14:55:43 +0000 (14:55 +0000)]
[llvm-exegesis] Mark x86 segment register instructions as unsupported.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D53499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344906
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Guillaume Chatelet [Mon, 22 Oct 2018 14:46:08 +0000 (14:46 +0000)]
[llvm-exegesis] Reject x86 instructions that use non uniform memory accesses
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D53438
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344905
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Roman Lebedev [Mon, 22 Oct 2018 14:12:44 +0000 (14:12 +0000)]
[X86] X86DAGToDAGISel: handle BZHI selection too, not just BEXTR.
Summary:
As discussed in D52304 / IRC, we now have pattern matching for
'bit extract' in two places - tablegen and `X86DAGToDAGISel`.
There are 4 patterns.
And we will have a problem with `x & (-1 >> (32 - y))` pattern.
* If the mask is one-use, then it is always unfolded into `x << (32 - y) >> (32 - y)` first.
Thus, the existing test coverage is already broken.
* If it is not one-use, then it is not unfolded, and is matched as BZHI.
* If it is not one-use, we will not match it as BEXTR. And if it is one-use, it will have been unfolded already.
So we will either not handle that pattern for BEXTR, or not have test coverage for it.
This is bad.
As discussed with @craig.topper, let's unify this matching, and do everything in `X86DAGToDAGISel`.
Then we will not have code duplication, and will have proper test coverage.
This indeed does not affect any tests, and this is great.
It means that for these two patterns, the `X86DAGToDAGISel` is identical to the tablegen version.
Please review carefully, i'm not fully sure about that intrinsic change, and introduction of the new `X86ISD` opcode.
Reviewers: craig.topper, RKSimon, spatel
Reviewed By: craig.topper
Subscribers: llvm-commits, craig.topper
Differential Revision: https://reviews.llvm.org/D53164
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344904
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David Greene [Mon, 22 Oct 2018 14:04:13 +0000 (14:04 +0000)]
Document bisect-skip-count
Provide an example of how to use bisect-skip count to find bugs.
Differential revision: https://reviews.llvm.org/D52314
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344903
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Roman Lebedev [Mon, 22 Oct 2018 13:54:17 +0000 (13:54 +0000)]
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ((1 << nbits) + (-1)) pattern
Summary:
Trivial continuation of D52304.
While this pattern is not canonical, we do select it in the BZHI case,
so this should not be any different.
Reviewers: RKSimon, craig.topper, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344902
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Petar Avramovic [Mon, 22 Oct 2018 13:27:50 +0000 (13:27 +0000)]
Test commit: change comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344900
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George Rimar [Mon, 22 Oct 2018 12:18:30 +0000 (12:18 +0000)]
[llvm-dwarfdump] - Fix win10 build bot failture.
Bot failed:
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/20877/steps/test/logs/stdio
This was broken after the
r344895 "[llvm-dwarfdump] - Add the support of parsing .debug_loclists."
because of wrong formatting specifiers used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344896
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George Rimar [Mon, 22 Oct 2018 11:30:54 +0000 (11:30 +0000)]
[llvm-dwarfdump] - Add the support of parsing .debug_loclists.
This teaches llvm-dwarfdump to dump the content of .debug_loclists sections.
It converts the DWARFDebugLocDWO class to DWARFDebugLoclists,
teaches llvm-dwarfdump about .debug_loclists section and
adds the implementation for parsing the DW_LLE_offset_pair entries.
Differential revision: https://reviews.llvm.org/D53364
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344895
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Nemanja Ivanovic [Mon, 22 Oct 2018 11:22:59 +0000 (11:22 +0000)]
[PowerPC][NFC] Fix bugs in r+r to r+i conversion
The D-Form VSX loads introduced in ISA 3.0 are not direct D-Form equivalent of
the corresponding X-Forms since they only target the Altivec registers.
Namely LXSSPX can load into any of the 64 VSX registers whereas LXSSP can only
load into the upper 32 VSX registers. Similarly with the remaining affected
instructions.
There is currently no way that I can see to trigger the bug, but as we add other
ways of exploiting these instructions, there may very well be instances that do.
This is an NFC patch in practical terms since the changes it introduces can not
be triggered without an MIR test.
Differential revision: https://reviews.llvm.org/D53323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344894
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Benjamin Kramer [Mon, 22 Oct 2018 10:51:34 +0000 (10:51 +0000)]
[CGProfile] Turn constant-size SmallVector into array
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344893
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Aleksandr Urakov [Mon, 22 Oct 2018 07:18:08 +0000 (07:18 +0000)]
[PDB] Extend IPDBSession's interface to retrieve frame data
Summary:
This patch just extends the `IPDBSession` interface to allow retrieving
of frame data through it, and adds an implementation over DIA. It is needed
for an implementation (for now with DIA) of the conversion from FPO programs
to DWARF expressions mentioned in D53086.
Reviewers: zturner, asmith, rnk
Reviewed By: asmith
Subscribers: mgorny, aprantl, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D53324
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344886
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Craig Topper [Mon, 22 Oct 2018 06:30:22 +0000 (06:30 +0000)]
[X86] Add patterns for vector and/or/xor/andn with other types than vXi64.
This makes fast isel treat all legal vector types the same way. Previously only vXi64 was in the fast-isel tables.
This unfortunately prevents matching of andn by fast-isel for these types since the requires SelectionDAG. But we already had this issue for vXi64. So at least we're consistent now.
Interestinly it looks like fast-isel can't handle instructions with constant vector arguments so the the not part of the andn patterns is selected with SelectionDAG. This explains why VPTERNLOG shows up in some of the tests.
This is a subset of D53268. As I make progress on that, I will try to reduce the number of lines in the tablegen files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344884
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Dorit Nuzman [Mon, 22 Oct 2018 06:17:09 +0000 (06:17 +0000)]
[IAI,LV] Avoid creating a scalar epilogue due to gaps in interleave-groups when
optimizing for size
LV is careful to respect -Os and not to create a scalar epilog in all cases
(runtime tests, trip-counts that require a remainder loop) except for peeling
due to gaps in interleave-groups. This patch fixes that; -Os will now have us
invalidate such interleave-groups and vectorize without an epilog.
The patch also removes a related FIXME comment that is now obsolete, and was
also inaccurate:
"FIXME: return None if loop requiresScalarEpilog(<MaxVF>), or look for a smaller
MaxVF that does not require a scalar epilog."
(requiresScalarEpilog() has nothing to do with VF).
Reviewers: Ayal, hsaito, dcaballe, fhahn
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D53420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344883
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Craig Topper [Sun, 21 Oct 2018 21:30:26 +0000 (21:30 +0000)]
[X86] Stop promoting integer loads to vXi64
Summary:
Theoretically this was done to simplify the amount of isel patterns that were needed. But it also meant a substantial number of our isel patterns have to match an explicit bitcast. By making the vXi32/vXi16/vXi8 types legal for loads, DAG combiner should be able to change the load type to remove the bitcast.
I had to add some additional plain load instruction patterns and a few other special cases, but overall the isel table has reduced in size by ~12000 bytes. So it looks like this promotion was hurting us more than helping.
I still have one crash in vector-trunc.ll that I'm hoping @RKSimon can help with. It seems to relate to using getTargetConstantFromNode on a load that was shrunk due to an extract_subvector combine after the constant pool entry was created. So we end up decoding more mask elements than the load size.
I'm hoping this patch will simplify the number of patterns needed to remove the and/or/xor promotion.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits, RKSimon
Differential Revision: https://reviews.llvm.org/D53306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344877
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Craig Topper [Sun, 21 Oct 2018 21:08:37 +0000 (21:08 +0000)]
Revert r344873 "foo"
Rebase gone wrong left this in my tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344875
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Craig Topper [Sun, 21 Oct 2018 21:07:27 +0000 (21:07 +0000)]
[X86] Remove SDIVREM8_SEXT_HREG/UDIVREM8_ZEXT_HREG and their associated DAG combine and target bits support. Use a post isel peephole instead.
Summary:
These nodes exist to overcome an isel problem where we can generate a zero extend of an AH register followed by an extract subreg, and another zero extend. The first zero extend exists to avoid a partial register update copying the AH register into the low 8-bits. The second zero extend exists if the user wanted the remainder zero extended.
To make this work we had a DAG combine to morph the DIVREM opcode to a special opcode that included the extend. But then we had to add the new node to computeKnownBits and computeNumSignBits to process the extension portion.
This patch instead removes all of that and adds a late peephole to detect the two extends.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53449
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344874
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Craig Topper [Sun, 21 Oct 2018 21:07:25 +0000 (21:07 +0000)]
foo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344873
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Sanjay Patel [Sun, 21 Oct 2018 20:13:29 +0000 (20:13 +0000)]
[DAGCombiner] reduce insert+bitcast+extract vector ops to truncate (PR39016)
This is a late backend subset of the IR transform added with:
D52439
We can confirm that the conversion to a 'trunc' is correct by running:
$ opt -instcombine -data-layout="e"
(assuming the IR transforms are correct; change "e" to "E" for big-endian)
As discussed in PR39016:
https://bugs.llvm.org/show_bug.cgi?id=39016
...the pattern may emerge during legalization, so that's we are waiting for an
insertelement to become a scalar_to_vector in the pattern matching here.
The DAG allows for fun variations that are not possible in IR. Result types for
extracts and scalar_to_vector don't necessarily match input types, so that means
we have to be a bit more careful in the transform (see code comments).
The tests show that we don't handle cases that require a shift (as we did in the
IR version). I've left that as a potential follow-up because I'm not sure if
that's a real concern at this late stage.
Differential Revision: https://reviews.llvm.org/D53201
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344872
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Aditya Kumar [Sun, 21 Oct 2018 18:11:56 +0000 (18:11 +0000)]
Schedule Hot Cold Splitting pass after most optimization passes
Summary:
In the new+old pass manager, hot cold splitting was schedule too early.
Thanks to Vedant for pointing this out.
Reviewers: sebpop, vsk
Reviewed By: sebpop, vsk
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D53437
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344869
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Simon Pilgrim [Sun, 21 Oct 2018 17:07:50 +0000 (17:07 +0000)]
[X86][AVX] Enable lowerVectorShuffleAsLanePermuteAndPermute v16i16/v32i8 unary shuffle lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344868
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Simon Pilgrim [Sun, 21 Oct 2018 11:55:56 +0000 (11:55 +0000)]
[X86] Only extract constant pool shuffle mask data with zero offsets
D53306 exposes an issue where we sometimes use constant pool data from bigger vectors than the target shuffle mask. This should be safe to do, but we have to be certain that we're using the bottom most part of the vector as the shuffle mask decoders have no way to peek into subvectors with non-zero offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344867
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Heejin Ahn [Sun, 21 Oct 2018 11:16:50 +0000 (11:16 +0000)]
[WebAssembly] Change tabs to spaces in basic-assembly.s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344866
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Lang Hames [Sat, 20 Oct 2018 20:39:53 +0000 (20:39 +0000)]
[ORC] Add some more basic sanity tests for the LLJIT.
minimal.ll contains a main function that returns zero, and
single-function-call.ll contains a main function that calls a foo function that
returns zero. These minimal tests can help to rule out some trivial JIT bugs
when other tests fail.
This commit also renames hello.ll to global-ctors-and-dtors.ll, which better
reflects what it is actually testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344863
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Sanjay Patel [Sat, 20 Oct 2018 18:18:55 +0000 (18:18 +0000)]
[InstCombine] add test for possible shuffle fold; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344860
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Simon Pilgrim [Sat, 20 Oct 2018 17:38:33 +0000 (17:38 +0000)]
[CostModel][X86] Add some initial extract/insert subvector shuffle cost tests
Just f64/i64 tests initially to demonstrate PR39368
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344857
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Sanjay Patel [Sat, 20 Oct 2018 17:15:57 +0000 (17:15 +0000)]
[InstCombine] use 'match' to simplify code; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344855
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Sanjay Patel [Sat, 20 Oct 2018 16:58:27 +0000 (16:58 +0000)]
[InstCombine] make code more flexible with lambda; NFC
I couldn't tell from svn history when these checks were added,
but it pre-dates the split of instcombine into its own directory
at rL92459.
The motivation for changing the check is partly shown by the
code in PR34724:
https://bugs.llvm.org/show_bug.cgi?id=34724
There are also existing regression tests for SLPVectorizer with
sequences of extract+insert that are likely assumed to become
shuffles by the vectorizer cost models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344854
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Sanjay Patel [Sat, 20 Oct 2018 16:25:55 +0000 (16:25 +0000)]
[InstCombine] add explanatory comment for strange vector logic; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344852
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Simon Pilgrim [Sat, 20 Oct 2018 15:17:27 +0000 (15:17 +0000)]
[SLPVectorizer][X86] Add mul/and/or/xor unrolled reduction tests
We miss arithmetic reduction for everything but Add/FAdd (I assume because that's the only cases which x86 has horizontal ops for.....)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344849
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Sanjay Patel [Sat, 20 Oct 2018 14:53:07 +0000 (14:53 +0000)]
[SLPVectorizer] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344848
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Simon Pilgrim [Sat, 20 Oct 2018 14:29:59 +0000 (14:29 +0000)]
[CostModel][X86] Add integer vector reduction cost tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344846
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Simon Pilgrim [Sat, 20 Oct 2018 13:16:31 +0000 (13:16 +0000)]
Replace setFeature macro with lambda to fix MSVC "shift count negative or too big" warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344843
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David Blaikie [Sat, 20 Oct 2018 09:16:49 +0000 (09:16 +0000)]
DebugInfo: Use base address specifiers more aggressively
Using a base address specifier even for a single-element range is a size
win for object files (7 words versus 8 words - more significant savings
if the debug info is compressed (since it's 3 words of uncompressable
reloc + 4 compressable words compared to 6 uncompressable reloc + 2
compressable words) - does trade off executable size increase though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344841
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David Blaikie [Sat, 20 Oct 2018 08:55:51 +0000 (08:55 +0000)]
Add missed file from previous commit (r344838)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344839
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David Blaikie [Sat, 20 Oct 2018 08:54:05 +0000 (08:54 +0000)]
DebugInfo: Use DW_OP_addrx in DWARFv5
Reuse addresses in the address pool, even in non-split cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344838
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David Blaikie [Sat, 20 Oct 2018 08:12:36 +0000 (08:12 +0000)]
DebugInfo: Implement debug_rnglists.dwo
Save space/relocations in .o files by keeping dwo ranges in the dwo
file rather than the .o file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344837
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David Blaikie [Sat, 20 Oct 2018 07:36:39 +0000 (07:36 +0000)]
DebugInfo: Use address pool forms in debug_rnglists
Save no relocations by reusing addresses from the address pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344836
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David Blaikie [Sat, 20 Oct 2018 06:16:25 +0000 (06:16 +0000)]
llvm-dwarfdump: Support RLE_addressx and RLE_startx_length in .debug_rnglists
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344835
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David Blaikie [Sat, 20 Oct 2018 06:02:15 +0000 (06:02 +0000)]
DebugInfo: Use debug_addr for non-dwo addresses in DWARF 5
Putting addresses in the address pool, even with non-fission, can reduce
relocations - reusing the addresses from debug_info and debug_rnglists
(the latter coming soon)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344834
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Craig Topper [Sat, 20 Oct 2018 03:51:43 +0000 (03:51 +0000)]
[X86] Add additional CPUs and features to Host.cpp and X86TargetParser.def to match compiler-rt and enable __builtin_cpu_supports/__builtin_cpu_is support in clang
Summary: This matches LLVM to D53461 for compiler-rt.
Reviewers: echristo, erichkeane
Reviewed By: echristo
Subscribers: dberris, llvm-commits
Differential Revision: https://reviews.llvm.org/D53462
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344831
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Thomas Lively [Sat, 20 Oct 2018 01:35:23 +0000 (01:35 +0000)]
[WebAssembly] Implement vector sext_inreg and tests with comparisons
Summary: Depends on D53251.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53252
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344826
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Thomas Lively [Sat, 20 Oct 2018 01:31:18 +0000 (01:31 +0000)]
[WebAssembly] Custom lower i64x2 constant shifts to avoid wrap
Summary: Depends on D53057.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53251
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344825
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Roman Tereshin [Sat, 20 Oct 2018 00:06:15 +0000 (00:06 +0000)]
[MachineCSE][GlobalISel] Making sure MachineCSE works mid-GlobalISel (again)
Change of approach, it looks like it's a much better idea to deal with
the vregs that have LLTs and reg classes both properly, than trying to
avoid creating those across all GlobalISel passes and all targets.
The change mostly touches MachineRegisterInfo::constrainRegClass,
which is apparently only used by MachineCSE. The changes are NFC for
any pipeline but one that contains MachineCSE mid-GlobalISel.
NOTE on isCallerPreservedOrConstPhysReg change in MachineCSE:
There is no test covering it as the only way to insert a new pass
(MachineCSE) from a command line I know of is llc's -run-pass option,
which only works with MIR, but MIRParser freezes reserved registers upon
MachineFunctions creation, making it impossible to reproduce the state
that exposes the issue.
Reviwed By: aditya_nandakumar
Differential Revision: https://reviews.llvm.org/D53144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344822
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Petar Jovanovic [Fri, 19 Oct 2018 22:16:49 +0000 (22:16 +0000)]
[llvm-objdump] Fix --file-headers (-f) option
Changed the format call to match the surrounding code. Previously it was
printing an unsigned int while the return type being printed was
long unsigned int or wider. This caused problems for big-endian systems
which were discovered on mips64.
Also, the printed address had less characters than it should because the
character count was directly obtained from the number of bytes in the
address.
The tests were adapted to fit this fix and now use longer addresses.
Patch by Milos Stojanovic.
Differential Revision: https://reviews.llvm.org/D53403
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344818
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Thomas Lively [Fri, 19 Oct 2018 21:11:43 +0000 (21:11 +0000)]
[LoopVectorize] Loop vectorization for minimum and maximum
Summary: Depends on D52766.
Reviewers: aheejin, dschuff
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344816
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Changpeng Fang [Fri, 19 Oct 2018 21:09:21 +0000 (21:09 +0000)]
AMDGPU: Add support pattern for SUB of one bit
Summary:
Add selection patterns to support one bit Sub.
Reviewers:
rampitec, arsenm
Differential Revision:
https://reviews.llvm.org/D52946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344815
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Evandro Menezes [Fri, 19 Oct 2018 20:57:45 +0000 (20:57 +0000)]
[NFC][InstCombine] Undo stray change
Undo stray change introduced by r344725.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344814
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Craig Topper [Fri, 19 Oct 2018 20:44:33 +0000 (20:44 +0000)]
[X86] Remove some left over code from when MVT:i1 was a legal type for AVX512.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344813
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Matt Arsenault [Fri, 19 Oct 2018 20:17:05 +0000 (20:17 +0000)]
Fix typos in assert message
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344812
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Aditya Nandakumar [Fri, 19 Oct 2018 20:11:52 +0000 (20:11 +0000)]
[GISel]: Allow PHIs to be DCEd
https://reviews.llvm.org/D53304
Currently dead phis are not cleaned up during DCE. This patch allows
dead PHI and G_PHI insts to be deleted.
Reviewed by: dsanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344811
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Craig Topper [Fri, 19 Oct 2018 19:24:42 +0000 (19:24 +0000)]
[X86] In PostprocessISelDAG, start from allnodes_end, not the root.
There is no guarantee the root is at the end if isel created any nodes without morphing them. This includes the nodes created by manual isel from C++ code in X86ISelDAGToDAG.
This is similar to r333415 from PowerPC which is where I originally stole the peephole loop from.
I don't have a test case, but without this a future patch doesn't work which is how I found it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344808
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Wolfgang Pieb [Fri, 19 Oct 2018 19:23:16 +0000 (19:23 +0000)]
[DWARF] Make llvm-dwarfdump display location lists in a .dwp file correctly. Fixes PR38990.
Considers the index when extracting location lists from a .dwp file.
Majority of the patch by David Blaikie.
Reviewers: dblaikie
Differential revision: https://reviews.llvm.org/D53155
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344807
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Thomas Lively [Fri, 19 Oct 2018 19:08:06 +0000 (19:08 +0000)]
[WebAssembly] Handle undefined lane indices in SIMD patterns
Summary:
Undefined indices in shuffles can be used when not all lanes of the
output vector will be used. This happens for example in the expansion
of vector reduce operations. Regardless, undefs are legal as lane
indices in IR and should be supported.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344803
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Krzysztof Pszeniczny [Fri, 19 Oct 2018 19:02:16 +0000 (19:02 +0000)]
Fix a use-after-RAUW bug in large GEP splitting
Summary:
Large GEP splitting, introduced in rL332015, uses a `DenseMap<AssertingVH<Value>, ...>`. This causes an assertion to fail (in debug builds) or undefined behaviour to occur (in release builds) when a value is RAUWed.
This manifested itself in the 7zip benchmark from the llvm test suite built on ARM with `-fstrict-vtable-pointers` enabled while RAUWing invariant group launders and splits in CodeGenPrepare.
This patch merges the large offsets of the argument and the result of an invariant.group strip/launder intrinsic before RAUWing.
Reviewers: Prazek, javed.absar, haicheng, efriedma
Reviewed By: Prazek, efriedma
Subscribers: kristof.beyls, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D51936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344802
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Thomas Lively [Fri, 19 Oct 2018 19:01:26 +0000 (19:01 +0000)]
[InstCombine] InstCombine and InstSimplify for minimum and maximum
Summary: Depends on D52765
Reviewers: aheejin, dschuff
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52766
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344799
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Andrea Di Biagio [Fri, 19 Oct 2018 18:39:29 +0000 (18:39 +0000)]
[llvm-mca] Remove a stale TODO comment. NFC
Starting from revision r344334, we can now describe optimizable
register-register moves in the machine scheduling models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344797
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Thomas Lively [Fri, 19 Oct 2018 18:15:32 +0000 (18:15 +0000)]
[ConstantFolding] Constant fold minimum and maximum intrinsics
Summary: Depends on D52764
Reviewers: aheejin, dschuff
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52765
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344796
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Jonas Devlieghere [Fri, 19 Oct 2018 17:57:53 +0000 (17:57 +0000)]
[dwarfdump] Hide ranges in diff-mode.
llvm-dwarfdump --diff should not print DW_AT_ranges. This patch fixes
that.
Differential revision: https://reviews.llvm.org/D53353
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344794
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Sanjay Patel [Fri, 19 Oct 2018 17:54:53 +0000 (17:54 +0000)]
[InstCombine] use m_Neg() in dyn_castNegVal() to match vectors with undef elts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344793
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Krzysztof Parzyszek [Fri, 19 Oct 2018 17:31:11 +0000 (17:31 +0000)]
[Hexagon] Remove support for V4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344791
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