OSDN Git Service
Masahiro Yamada [Wed, 14 Jun 2017 04:49:29 +0000 (13:49 +0900)]
pinctrl: uniphier: fix WARN_ON() of pingroups dump on LD11
The pingroups dump of debugfs hits WARN_ON() in pinctrl_groups_show().
Filling non-existing ports with '-1' turned out a bad idea.
Fixes:
70f2f9c4cf25 ("pinctrl: uniphier: add UniPhier PH1-LD11 pinctrl driver")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Tue, 20 Jun 2017 08:07:34 +0000 (10:07 +0200)]
Merge tag 'samsung-pinctrl-4.13' of git://git./linux/kernel/git/pinctrl/samsung into devel
Samsung pinctrl drivers update for v4.13:
1. Split drivers per ARMv7 and ARMv8 architectures because there
is no need to compile everything on each of them.
2. Fix for possible NULL-pointer dereference after memory allocation
failure.
3. Cleanups (silencing cast warnings, constify, removal of unneeded
casts, removal of modular boiler-plate).
Hanna Hawa [Mon, 12 Jun 2017 15:34:57 +0000 (17:34 +0200)]
pinctrl: mvebu: add driver for Armada CP110 pinctrl
This commit adds a pinctrl driver for the CP110 part of the Marvell
Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all
the MPP pins are available. On the other side, the Armada 8K has two
CP110, and the available MPPs are split between the master CP110 (MPPs 32
to 62) and the slave CP110 (MPPs 0 to 31).
The register interface to control the MPPs is however the same as all
other mvebu SoCs, so we can reuse the common pinctrl-mvebu.c logic.
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Reviewed-by: Shadi Ammouri <shadi@marvell.com>
[updated for mvebu pinctrl and 4.9 changes:
- converted to simple_mmio
- converted to syscon/regmap
- removed unimplemented .remove function
- dropped DTS changes
- defered gpio ranges to DT
- fixed warning
- properly set soc->nmodes
-- rmk]
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
[ add missing MPP[61:56] function 14 (SDIO)
-- Konstantin Porotchkin]
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
[ allow to properly register more then one instance of this driver
-- Grzegorz Jaszczyk]
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[ - rebased on 4.12-rc1
- fixed the 80 character limit for mvebu_mpp_mode array
- aligned the compatible name on the ones already used
- fixed the MPP table for CP110: some MPP are not available on Armada 7K
-- Gregory CLEMENT]
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Hanna Hawa [Mon, 12 Jun 2017 15:34:56 +0000 (17:34 +0200)]
pinctrl: mvebu: add driver for Armada AP806 pinctrl
This commit adds a pinctrl driver for the pin-muxing controller found in
the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register
interface is compatible with the one used by previous mvebu pin
controllers, so the common logic in drivers/pinctrl/mvebu/pinctrl-mvebu.c
is used.
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Reviewed-by: Shadi Ammouri <shadi@marvell.com>
[updated for mvebu pinctrl changes
- converted to simple_mmio
- removed unimplemented .remove function
- removed DTS description
- converted to use syscon/regmap
--rmk]
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Russell King [Mon, 12 Jun 2017 15:34:54 +0000 (17:34 +0200)]
pinctrl: avoid PLAT_ORION dependency
Armada 8040 also needs orion pinctrl, and as these symbols are only
selected, there's no need to make them depend on PLAT_ORION.
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Gregory CLEMENT [Mon, 12 Jun 2017 15:34:53 +0000 (17:34 +0200)]
pinctrl: mvebu: remove the offset property for regmap
The offset property of the pinctrl node, when a regmap is used in the
device tree, was never used nor documented in the binding. Moreover, the
compatible string is enough to let the driver know which offset using.
So this patch removes the property and move the information at the driver
level.
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Jerome Brunet [Thu, 8 Jun 2017 13:09:48 +0000 (15:09 +0200)]
pinctrl: meson-gxl: add tsin_a pins
Add Tsin A pins to bank DV and X.
We don't have a driver for the tsin yet but since the tsin A pinmux is
enabled by default at boot time, declaring this pinmux is required to
properly operate on GPIOX.
Without this change, GPIOX 8, 9, 10 and 11 can't be driven as GPIO output
as the tsin A seems to have priority.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Mika Westerberg [Tue, 6 Jun 2017 13:18:19 +0000 (16:18 +0300)]
pinctrl: intel: Add Intel Cannon Lake PCH pin controller support
This adds pinctrl/GPIO support for Intel Cannon Lake PCH. The Cannon
Lake PCH GPIO is based on newer version of the Intel GPIO hardware.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Mika Westerberg [Tue, 6 Jun 2017 13:18:18 +0000 (16:18 +0300)]
pinctrl: intel: Make it possible to specify mode per pin in a group
On some SoCs not all pins in a group use the same mode when a certain
function is muxed out of them. This makes it possible to specify mode per
pin as an array instead in addition to single integer.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Mika Westerberg [Tue, 6 Jun 2017 13:18:17 +0000 (16:18 +0300)]
pinctrl: intel: Add support for variable size pad groups
The Intel GPIO hardware has a concept of pad groups, which means 1 to 32
pads occupying their own GPI_IS, GPI_IE, PAD_OWN and so on registers. The
existing hardware has the same amount of pads in each pad group (except the
last one) so it is possible to use community->gpp_size to calculate start
offset of each register.
With the next generation SoCs the pad group size is not always the same
anymore which means we cannot use community->gpp_size for register offset
calculations directly.
To support variable size pad groups we introduce struct intel_padgroup that
can be filled in by the client drivers according the hardware pad group
layout. The core driver will always use these when it performs calculations
for pad register offsets. The core driver will automatically populate pad
groups based on community->gpp_size if the driver does not provide any.
This makes sure the existing drivers still work as expected.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Chuah, Kim Tatt <kim.tatt.chuah@intel.com>
Signed-off-by: Tan Jui Nee <jui.nee.tan@intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Chen-Yu Tsai [Sat, 3 Jun 2017 14:44:26 +0000 (22:44 +0800)]
pinctrl: sunxi: Add support for A83T R_PIO
The R_PIO on the A83T is almost the same as the one found on the A64,
except that the CIR_RX function was moved from pin PL11 to pin PL12.
Add a driver for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Chen-Yu Tsai [Sat, 3 Jun 2017 14:44:25 +0000 (22:44 +0800)]
dt-bindings: pinctrl: sunxi: Add compatible string for A83T R_PIO
The R_PIO on the A83T is almost the same as the one found on the A64,
except that the CIR_RX function was moved from pin PL11 to pin PL12.
Add a compatible string for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Scott Branden [Fri, 2 Jun 2017 18:52:21 +0000 (11:52 -0700)]
pinctrl: bcm: cleanup Broadcom license headers
Use consistent license headers for Broadcom files by
placing additional comments outside of standard legal header.
Also, update legal header to 2017 format as "Broadcom Corporation"
has changed to "Broadcom".
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tobias Klauser [Fri, 2 Jun 2017 11:29:58 +0000 (13:29 +0200)]
pinctrl: sunxi: constify irq_domain_ops
struct irq_domain_ops is not modified, so it can be made const.
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Alexandre TORGUE [Wed, 31 May 2017 09:10:43 +0000 (11:10 +0200)]
pinctrl: stm32: remove useless check
There is no link between the number of elements of tab which contains all
pin desc (located in each pinctrl-stm32xxxx.c files) and the pin number
(defined in the tab).
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Jerome Brunet [Thu, 8 Jun 2017 19:37:50 +0000 (21:37 +0200)]
pinctrl: meson: add interrupts to pinctrl data
Add GPIO interrupt information to pinctrl data. Added to the original
version from Jerome was data for Meson GXL.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Heiner Kallweit [Wed, 7 Jun 2017 05:44:20 +0000 (07:44 +0200)]
pinctrl: meson-gxbb: remove non-existing pin GPIOX_22
After commit
34e61801a3b9 "pinctrl: meson-gxbb: Add missing GPIODV_18
pin entry" I started to get the following warning:
"meson-pinctrl
c8834000.periphs:pinctrl@4b0: names 119 do not match
number of GPIOs 120"
It turned out that not the mentioned commit has a problem, it just
revealed another problem which had existed before.
There is no PIN GPIOX_22 on Meson GXBB.
Fixes:
468c234f9ed7 ("pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC")
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Krzysztof Kozlowski [Tue, 23 May 2017 18:36:53 +0000 (20:36 +0200)]
pinctrl: samsung: Explicitly cast pointer returned by of_iomap() to iomem
For S5Pv210 retention control, the driver stores the iomem pointer from
of_iomap() under a void pointer member. This makes sparse unhappy:
drivers/pinctrl/samsung/pinctrl-exynos.c:664:36: warning: incorrect type in argument 1 (different address spaces)
drivers/pinctrl/samsung/pinctrl-exynos.c:664:36: expected void const volatile [noderef] <asn:2>*addr
drivers/pinctrl/samsung/pinctrl-exynos.c:664:36: got void *
The iomem pointer is used safely (stored under priv by
s5pv210_retention_init(), used by s5pv210_retention_disable()) thus we
can add explicit casts to iomem to silence the warning.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Krzysztof Kozlowski [Tue, 23 May 2017 18:41:40 +0000 (20:41 +0200)]
pinctrl: samsung: Handle memory allocation failure during wakeup banks init
Check if kmemdup failed during wakeup banks initialization. Otherwise
NULL pointer would be stored under "irq_chip" member of bank and later
dereferenced in interrupt handler.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Krzysztof Kozlowski [Tue, 23 May 2017 18:41:39 +0000 (20:41 +0200)]
pinctrl: samsung: Constify wakeup driver specific data
Static exynos_irq_chip structures, containing driver specific data, are
referenced only through opaque data pointer in const of_device_id table.
The contents of pointed memory (exynos_irq_chip structure itself) is
then copied with kmemdup() during wakeup initialization so
exynos_irq_chip can be made const for code safenes.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Krzysztof Kozlowski [Tue, 16 May 2017 18:56:27 +0000 (20:56 +0200)]
pinctrl: samsung: Split Exynos drivers per ARMv7 and ARMv8
Exynos pinctrl drivers contain pretty big per-SoC data structures. The
pinctrl-exynos object file contained code and data for both ARMv7 and
ARMv8 SoCs thus it grew big. There will not be a shared image between
ARMv7 and ARMv8 so there is no need to combine all of this into one
driver.
Splitting the data allows to make it more granular (e.g. code related to
ARMv8 Exynos is self-contained), slightly speed up the compilation and
reduce the effective size of compiled kernel.
The common data structures and functions reside still in existing
pinctrl-exynos.c. Only the SoC-specific parts were moved out to new
files. Except marking few functions non-static and adding them to
header, there were no functional changes in the code.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Linus Walleij [Wed, 31 May 2017 00:09:43 +0000 (02:09 +0200)]
Merge tag 'sh-pfc-for-v4.13-tag1' of git://git./linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.13
- Add PWM, AVB MDIO/MII, and sound pin groups on R-Car M3-W,
- Add support for RZ/G1M and RZ/G1E,
- Small fixes and cleanups.
Alexandre TORGUE [Mon, 29 May 2017 16:17:32 +0000 (18:17 +0200)]
pinctrl: stm32: Implement .get_direction gpio_chip callback
Add .get_direction() gpiochip callback in STM32 pinctrl driver.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Alexandre TORGUE [Mon, 29 May 2017 16:17:31 +0000 (18:17 +0200)]
pinctrl: stm32: set pin to gpio input when used as interrupt
This patch ensures that pin is correctly set as gpio input when it is used
as an interrupt.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Arnd Bergmann [Tue, 30 May 2017 09:11:28 +0000 (11:11 +0200)]
pinctrl: mcp23s08: improve I2C Kconfig dependency
With "SPI_MASTER=y && I2C=m", we can build mcp23s08 as a built-in driver,
which then results in a link failure:
drivers/pinctrl/built-in.o: In function `mcp23s08_probe_one.isra.0':
:(.text+0x7910): undefined reference to `__devm_regmap_init_i2c'
drivers/pinctrl/built-in.o: In function `mcp23s08_init':
:(.init.text+0x110): undefined reference to `i2c_register_driver'
drivers/pinctrl/built-in.o: In function `mcp23s08_exit':
:(.exit.text+0x3c): undefined reference to `i2c_del_driver'
To avoid the problem, this adds another dependency on I2C that enforces
mcp23s08 to be a loadable module whenever the I2C core is a module.
Fixes:
64ac43e6fa28 ("gpio: mcp23s08: move to pinctrl")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Martin Schiller [Mon, 29 May 2017 04:08:38 +0000 (06:08 +0200)]
pinctrl: xway: fix copy/paste error in xrx200_grps
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Icenowy Zheng [Sat, 27 May 2017 10:23:03 +0000 (18:23 +0800)]
dt-bindings: add compatible string for Allwinner R40 pinctrl
Allwinner R40 has a pin controller like the ones in older Allwinner SoCs
(especially A20), and can use modified version of the A10/A20 pinctrl
driver.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Icenowy Zheng [Sat, 27 May 2017 10:23:02 +0000 (18:23 +0800)]
pinctrl: sunxi: drop dedicated A20 driver
As we added A20 support to A10 pinctrl driver, now we can delete the
dedicated A20 pinctrl driver, which is duplicated code.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
[Drop Makefile entry]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Icenowy Zheng [Sat, 27 May 2017 10:23:01 +0000 (18:23 +0800)]
pinctrl: sunxi: add A20 support to A10 driver
As A20 is designed as a pin-compatible upgrade of A10, their pin
controller are very similar, and can share one driver.
Add A20 support to the A10 driver.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Icenowy Zheng [Sat, 27 May 2017 10:23:00 +0000 (18:23 +0800)]
pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs
Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
into A10 driver, and add R40 support into it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
David Wu [Fri, 26 May 2017 07:20:23 +0000 (15:20 +0800)]
pinctrl: rockchip: Add iomux-route switching support for rk3399
There are 2 IP blocks pin routes need to be switched, that are
uart2dbg, pcie_clkreq.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
David Wu [Fri, 26 May 2017 07:20:22 +0000 (15:20 +0800)]
pinctrl: rockchip: Add iomux-route switching support for rk3328
There are 8 IP blocks pin routes need to be switched, that are
uart2dbg, gmac-m1-optimized, pdm, spi, i2s2, card, tsp, cif.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
David Wu [Fri, 26 May 2017 07:20:21 +0000 (15:20 +0800)]
pinctrl: rockchip: Add iomux-route switching support for rk3228
There are 9 IP blocks pin routes need to be switched, that are
pwm-0, pwm-1, pwm-2, pwm-3, sdio, spi, emmc, uart2, uart1.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
David Wu [Fri, 26 May 2017 07:20:20 +0000 (15:20 +0800)]
pinctrl: rockchip: Add iomux-route switching support
On the some rockchip SOCS, some things like rk3399 specific uart2 can use
multiple pins. Somewhere between the pin io-cells and the uart it seems
to have some sort of switch to decide to which pin to actually route the
data.
+-------+ +--------+ /- GPIO4_B0 (pinmux 2)
| uart2 | -- | switch | --- GPIO4_C0 (pinmux 2)
+-------+ +--------+ \- GPIO4_C3 (pinmux 2)
(switch selects one of the 3 pins base on the GRF_SOC_CON7[BIT0, BIT1])
The routing switch is determined by one pin of a specific group to be set
to its special pinmux function. If the pinmux setting is wrong for that
pin the ip block won't work correctly anyway.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Mon, 29 May 2017 11:40:45 +0000 (13:40 +0200)]
gpio/pinctrl: ingenic: depend on OF
Fix compile errors due to missing OF.
Cc: Paul Cercueil <paul@crapouillou.net>
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Neil Armstrong [Wed, 24 May 2017 08:20:42 +0000 (10:20 +0200)]
pinctrl: meson-gxl: Add Ethernet PHY LEDS pins
The Amlogic Meson GXL SoCs embeds an 10/100 Ethernet PHY, this patchs enables
the Link and Activity LEDs signals.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Neil Armstrong [Wed, 24 May 2017 08:20:41 +0000 (10:20 +0200)]
pinctrl: meson-gxl: Add CEC pins
Add the AO and EE domain CEC pins for the Amlogic Meson GXL SoCs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Neil Armstrong [Wed, 24 May 2017 08:20:40 +0000 (10:20 +0200)]
pinctrl: meson-gxbb: Add CEC pins
Add the AO and EE domain CEC pins for the Amlogic Meson GXBB SoCs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Neil Armstrong [Wed, 24 May 2017 08:20:39 +0000 (10:20 +0200)]
pinctrl: meson-gxl: Fix typo in AO SPDIF pins
The AO SPDIF pins were incorrectly defined with the EE pin offset.
Fixes:
b840d649f9ec ("pinctrl: meson: gxl: add spdif output pins")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Neil Armstrong [Wed, 24 May 2017 08:20:38 +0000 (10:20 +0200)]
pinctrl: meson-gxl: Fix typo in AO I2S pins
The AO I2S pins were incorrectly defined with the EE pin offset.
Fixes:
2899adf0422 ("pinctrl: meson: gxl: add i2s output pins")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Neil Armstrong [Tue, 23 May 2017 14:09:19 +0000 (16:09 +0200)]
pinctrl: meson-gxbb: Add missing GPIODV_18 pin entry
GPIODV_18 entry was missing in the original driver push.
Fixes:
468c234f9ed7 ("pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Neil Armstrong [Tue, 23 May 2017 14:09:18 +0000 (16:09 +0200)]
pinctrl: meson-gxl: Add missing GPIODV_18 pin entry
GPIODV_18 entry was missing in the original driver push.
Fixes:
0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Gortmaker [Mon, 22 May 2017 20:56:48 +0000 (16:56 -0400)]
pinctrl: bcm: clean up modular vs. non-modular distinctions
Fixups here tend to be more of a conglomerate of some of the other
repeated/systematic ones we've seen in the earlier pinctrl cleanups.
We remove module.h from code that isn't doing anything modular at
all; if they have __init sections, then replace it with init.h
One driver has a .remove that would be dispatched on module_exit,
and as that code is essentially orphaned, so we remove it. In case
anyone was previously doing the (pointless) unbind to get to that
function, we disable unbind for this one driver as well.
A couple bool drivers (hence non-modular) are converted over to
to builtin_platform_driver().
Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.
Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
We also delete the MODULE_LICENSE tag etc. since all that information
was (or is now) contained at the top of the file in the comments.
Cc: Eric Anholt <eric@anholt.net>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Jon Mason <jonmason@broadcom.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: Sherman Yin <syin@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: linux-gpio@vger.kernel.org
Cc: linux-rpi-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Gortmaker [Mon, 22 May 2017 20:56:47 +0000 (16:56 -0400)]
pinctrl: tegra: clean up modular vs. non-modular distinctions
None of the Kconfigs for any of these drivers are tristate,
meaning that they currently are not being built as a module by anyone.
Lets remove the modular code that is essentially orphaned, so that
when reading the drivers there is no doubt they are builtin-only. All
drivers get similar changes, so they are handled in batch.
We remove module.h from code that isn't doing anything modular at
all; if they have __init sections, then replace it with init.h.
A couple drivers have module_exit() code that is essentially orphaned,
and so we remove that.
Quite a few bool drivers (hence non-modular) are converted over to
to builtin_platform_driver().
Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.
Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
We also delete the MODULE_LICENSE tag etc. since all that information
was (or is now) contained at the top of the file in the comments.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Pritesh Raithatha <praithatha@nvidia.com>
Cc: Ashwini Ghuge <aghuge@nvidia.com>
Cc: linux-gpio@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Sat, 20 May 2017 16:02:17 +0000 (01:02 +0900)]
pinctrl: single: use of_device_get_match_data() to get soc data
Use of_device_get_match_data() instead of of_match_device().
It allows us to remove the forward declaration of pcs_of_match.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Shawn Guo [Mon, 22 May 2017 13:59:35 +0000 (21:59 +0800)]
pinctrl: zte: fix group_desc initialization
There are a couple of issues with group_desc initialization in function
zx_pinctrl_build_state().
- num_pins is not initialized and remains zero.
- pins shouldn't be initialized with a pointer to variable in the
stack.
With them fixed, pin_request() in pinmux_enable_setting() can be invoked
correctly.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Neil Armstrong [Mon, 22 May 2017 12:59:26 +0000 (14:59 +0200)]
pinctrl: meson-gxbb: Add SPI pins for SPICC controller
The SPICC controller has dedicated SPI pins, this patchs add the pins
definition in the GXBB pinctrl driver
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Neil Armstrong [Mon, 22 May 2017 12:59:25 +0000 (14:59 +0200)]
pinctrl: meson-gxl: Add SPI pins for the SPICC controller
The SPICC controller has dedicated SPI pins, this patchs add the pins
definition in the GXL pinctrl driver.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Krzysztof Kozlowski [Tue, 16 May 2017 20:06:48 +0000 (22:06 +0200)]
pinctrl: samsung: Add include guard to local header
The pinctrl-exynos.h header is included only once so till now it did not
require an include guard. However adding such is harmless and makes
code prepared for more inclusions.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Paul Gortmaker [Mon, 22 May 2017 20:56:46 +0000 (16:56 -0400)]
pinctrl: samsung: Clean up modular vs. non-modular distinctions
Fixups here tend to be more all over the map vs. some of the other
repeated/systematic ones we've seen elsewhere.
We remove module.h from code that isn't doing anything modular at
all; if they have __init sections, then replace it with init.h
A couple drivers have module_exit() code that is essentially orphaned,
and so we remove that.
There are no module_init replacements, so we have no concerns wrt.
initcall ordering changes as per some of the other cleanups.
Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
We also delete the MODULE_LICENSE tag etc. since all that information
was (or is now) contained at the top of the file in the comments.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Chen-Yu Tsai [Mon, 22 May 2017 06:25:49 +0000 (14:25 +0800)]
pinctrl: sunxi: Fix SPDIF function name for A83T
We use well known standard names for functions that have name, such as
I2C, SPI, SPDIF, etc..
Fix the function name of SPDIF, which was named OWA (One Wire Audio)
based on Allwinner datasheets.
Fixes:
4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller
support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Gregory CLEMENT [Fri, 19 May 2017 16:04:43 +0000 (18:04 +0200)]
MAINTAINERS: extend mvebu SoC entry with pinctrl drivers
There was no entry for the mvebu pinctrl drivers. As they are tightly
linked to the SoCs and there is a lot of common code to support the
various pinctrl of each SoCs, then add a new entry for the mvebu
maintainers.
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Mauro Carvalho Chehab [Fri, 19 May 2017 01:25:45 +0000 (22:25 -0300)]
pinctrl: pinctrl.txt: standardize document format
Each text file under Documentation follows a different
format. Some doesn't even have titles!
Change its representation to follow the adopted standard,
using ReST markups for it to be parseable by Sphinx.
This document is almost following the standard stile.
There are only two things to adjust on it:
- promote the level of the document title;
- mark literal blocks as such.
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
[Fix some indentations]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Tue, 23 May 2017 07:52:08 +0000 (09:52 +0200)]
Merge branch 'mcp23s08' into devel
Sebastian Reichel [Mon, 15 May 2017 09:24:38 +0000 (11:24 +0200)]
pinctrl: mcp23s08: fix comment for mcp23s08_platform_data.base
The comment does not match the driver, which actually supports
automatic assignment. Fix this by updating the comment.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sebastian Reichel [Mon, 15 May 2017 09:24:37 +0000 (11:24 +0200)]
pinctrl: mcp23s08: drop comment about missing irq support
The driver supports using mcp23xxx as interrupt controller, so
let's drop all comments stating otherwise.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sebastian Reichel [Mon, 15 May 2017 09:24:36 +0000 (11:24 +0200)]
pinctrl: mcp23s08: simplify spi_present_mask handling
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sebastian Reichel [Mon, 15 May 2017 09:24:35 +0000 (11:24 +0200)]
pinctrl: mcp23s08: generalize irq property handling
This moves irq property handling from spi/i2c specific code into
the generic mcp23s08_probe_one. This is possible because the
device properties are named equally.
As a side-effect this drops support for setting the properties via
pdata, which has no mainline users. If boardcode wants to enable
the chip as interrupt controller it can attach the device properties
instead.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sebastian Reichel [Mon, 15 May 2017 09:24:34 +0000 (11:24 +0200)]
pinctrl: mcp23s08: simplify spi pdata handling
Simplify spi pdata handling, so that it uses pdata when available
and falls back to reading device properties otherwise.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sebastian Reichel [Mon, 15 May 2017 09:24:33 +0000 (11:24 +0200)]
pinctrl: mcp23s08: simplify i2c pdata handling
Simplify i2c pdata handling, so that it uses pdata when available
and falls back to reading device properties otherwise.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sebastian Reichel [Mon, 15 May 2017 09:24:32 +0000 (11:24 +0200)]
pinctrl: mcp23s08: switch to devm_gpiochip_add_data
Switching to devm_gpiochip_add_data simplifies the driver's
cleanup routine and safes a few loc.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sebastian Reichel [Mon, 15 May 2017 09:24:31 +0000 (11:24 +0200)]
pinctrl: mcp23s08: use managed kzalloc for mcp
Let's remove a few lines of code by using managed memory for mcp
variable.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sebastian Reichel [Mon, 15 May 2017 09:24:30 +0000 (11:24 +0200)]
pinctrl: mcp23s08: irq mapping is already done
i2c-core and spi-core already assign the irq, so we
can drop the additional call from the mcp driver.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sebastian Reichel [Mon, 15 May 2017 09:24:29 +0000 (11:24 +0200)]
pinctrl: mcp23s08: drop OF_GPIO dependency
The driver compiles & works perfectly fine without OF_GPIO on x86,
so lets drop the dependency.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sebastian Reichel [Mon, 15 May 2017 09:24:28 +0000 (11:24 +0200)]
pinctrl: mcp23s08: switch to regmap caching
Instead of using custom caching, this switches to regmap based
caching. Before the conversion the debugfs file used uncached
values, so that it was easily possible to see power-loss related
problems. The new code will check and recover at this place.
The patch will also ensure, that irqs are not cleared by checking
register status in debugfs.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sebastian Reichel [Mon, 15 May 2017 09:24:27 +0000 (11:24 +0200)]
pinctrl: mcp23s08: drop pullup config from pdata
mcp23s08 support configuration of the pullups using the
pinconf framework. This removes the custom pullup configuration
from platform data, which has no upstream users.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sebastian Reichel [Mon, 15 May 2017 09:24:26 +0000 (11:24 +0200)]
pinctrl: mcp23s08: add pinconf support
mcp23xxx device have configurable 100k pullup resistors. This adds
support for enabling them using pinctrl's pinconf interface.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sebastian Reichel [Mon, 15 May 2017 09:24:25 +0000 (11:24 +0200)]
gpio: mcp23s08: move to pinctrl
This moves the mcp23s08 driver from gpio to pinctrl. Actual
pinctrl support for configuration of the pull-up resistors
follows in its own patch.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Mon, 22 May 2017 15:27:18 +0000 (17:27 +0200)]
Merge branch 'ingenic' into devel
Paul Cercueil [Fri, 12 May 2017 16:53:07 +0000 (18:53 +0200)]
MIPS: jz4740: Remove custom GPIO code
All the drivers for the various hardware elements of the jz4740 SoC have
been modified to use the pinctrl framework for their pin configuration
needs.
As such, this platform code is now unused and can be deleted.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:53:02 +0000 (18:53 +0200)]
MIPS: JZ4780: CI20: Add pinctrl configuration for several drivers
We set the pin configuration for the jz4780-nand and jz4780-uart
drivers.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:53:01 +0000 (18:53 +0200)]
MIPS: JZ4740: Qi LB60: Add pinctrl configuration for several drivers
We set the pin configuration for the jz4740-nand, jz4740-mmc,
jz4740-fb, jz4740-pwm and jz4740-uart drivers.
This will permit those drivers to be cleaned out of the custom GPIO code
that they currently use.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:53:00 +0000 (18:53 +0200)]
MIPS: jz4780: DTS: Add nodes for ingenic pinctrl and gpio drivers
For a description of the devicetree node, please read
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
For a description of the gpio devicetree nodes, please read
Documentation/devicetree/bindings/gpio/ingenic,gpio.txt
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:52:59 +0000 (18:52 +0200)]
MIPS: jz4740: DTS: Add nodes for ingenic pinctrl and gpio drivers
For a description of the pinctrl devicetree node, please read
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
For a description of the gpio devicetree nodes, please read
Documentation/devicetree/bindings/gpio/ingenic,gpio.txt
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:52:58 +0000 (18:52 +0200)]
MIPS: ingenic: Enable pinctrl for all ingenic SoCs
There is a pinctrl driver for each of the Ingenic SoCs supported by the
upstream Linux kernel. In order to switch away from the old GPIO
platform code, we now enable the pinctrl drivers by default for the
Ingenic SoCs.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:53:04 +0000 (18:53 +0200)]
mtd: nand: jz4740: Let the pinctrl driver configure the pins
Before, this NAND driver would set itself the configuration of the
chip-select pins for the various NAND banks.
Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:53:05 +0000 (18:53 +0200)]
fbdev: jz4740-fb: Let the pinctrl driver configure the pins
Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:53:06 +0000 (18:53 +0200)]
pwm: jz4740: Let the pinctrl driver configure the pins
Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.
One inherent problem of this new approach is that the pinctrl framework
does not allow us to configure each pin on demand, when the various PWM
channels are requested or released. For instance, the PWM channels can
be configured from sysfs, which would require all PWM pins to be configured
properly beforehand for the PWM function, eventually causing conflicts
with other platform or board drivers.
The proper solution here would be to modify the pwm-jz4740 driver to
handle only one PWM channel, and create an instance of this driver
for each one of the 8 PWM channels. Then, it could use the pinctrl
framework to dynamically configure the PWM pin it controls.
Until this can be done, the only jz4740 board supported upstream
(Qi lb60) can configure all of its connected PWM pins in PWM function
mode, since those are not used by other drivers nor by GPIOs on the
board.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:53:03 +0000 (18:53 +0200)]
mmc: jz4740: Let the pinctrl driver configure the pins
Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:52:57 +0000 (18:52 +0200)]
gpio: Add gpio-ingenic driver
This driver handles the GPIOs of all the Ingenic JZ47xx SoCs
currently supported by the upsteam Linux kernel.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:52:56 +0000 (18:52 +0200)]
pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs
This driver handles pin configuration and pin muxing for the
JZ4740 and JZ4780 SoCs from Ingenic.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:52:55 +0000 (18:52 +0200)]
dt/bindings: Document gpio-ingenic
This commit adds documentation for the devicetree bindings of the
gpio-ingenic driver, which handles GPIOs of the Ingenic SoCs
currently supported by the Linux kernel.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:52:54 +0000 (18:52 +0200)]
dt/bindings: Document pinctrl-ingenic
This commit adds documentation for the devicetree bindings of the
pinctrl-ingenic driver, which handles pin configuration and pin
muxing of the Ingenic SoCs currently supported by the Linux kernel.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nikita Yushchenko [Thu, 11 May 2017 20:02:11 +0000 (23:02 +0300)]
pinctrl: When claiming hog, skip maps not served by same device
When pinctrl device registers, it automatically claims hogs, that is,
maps that pinctrl device serves for itself.
It is possible that in addition to SoC's pinctrl device, other pinctrl
devices get registered. E.g. some gpio expander devies are registered
as pinctrl devices. For such devices, pinctrl maps could be defined
that set up SoC's pins (e.g. interrupt pin for gpio expander). Such
a map will have target device set to gpio expander.
Here is device tree snippet that causes this scenario:
&i2c0 {
sx1503@20 {
compatible = "semtech,sx1503q";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sx1503_20>;
...
};
};
...
&iomuxc {
pinctrl_sx1503_20: pinctrl-sx1503-20 {
fsl,pins = <
VF610_PAD_PTB1__GPIO_23 0x219d
>;
};
};
Such a map will have target device set to gpio expander. However is not
a hog, it is a regular map that is claimed by core before gpio expander
device is probed.
Thus when looking for hogs, it is not enough to check that map's target
device is set to pinctrl device being registered. Need also check that
map's control device is also set to the same.
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Dong Aisheng [Fri, 19 May 2017 07:05:43 +0000 (15:05 +0800)]
pinctrl: imx: add soc specific mux_mode mask and shift property
MX7ULP MUX mode mask and shift bit is different from VF610.
Let's make it a platform specific property for the later easy of
adding MX7ULP support.
One trick in exist code that Vybrid hardcoded the config part
as 0xffff because its mux_config register BIT[15-0] are all configs
part. But it's not true in ULP, so use mux_mask instead to address
the difference.
Cc: Stefan Agner <stefan@agner.ch>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Dong Aisheng [Fri, 19 May 2017 07:05:42 +0000 (15:05 +0800)]
pinctrl: imx: add generic pin config core support
The design is based on the exist architecture that the core will
provide a uniformed way to decode the generic pin config into platform
config register raw data according to the imx_cfg_params_decode maps
registered by platform.
Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT,
are created for platform to register decode map conveniently.
In order to cope with some special case, a platform specific fixup()
function is also available to use.
Note that rather than fully utilizing the generic pinconf support
provided by pinctrl core, IMX only adopts the device tree bindings
of generic pinconf. The config used in .pin_config_get[set] are raw
register data instead of generic one which makes us align the exist
using. And that's also why we cannot set pinconf_ops.is_generic.
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Dong Aisheng [Fri, 19 May 2017 07:05:41 +0000 (15:05 +0800)]
pinctrl: imx: fix debug message for SHARE_MUX_CONF_REG case
The original implemented debug message does not work for
SHARE_MUX_CONF_REG case. This patch fixes it.
Fixes:
bf5a530971af ("pinctrl: imx: add VF610 support to imx pinctrl framework")
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Christophe JAILLET [Sat, 6 May 2017 08:23:59 +0000 (10:23 +0200)]
pinctrl: imx: Check for memory allocation failure
If 'devm_kzalloc' fails, a NULL pointer will be dereferenced.
Return -ENOMEM instead, as done for the other memory allocation just a
few lines below.
BTW, change the 'devm_kzalloc' into a 'devm_kcalloc'.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sean Wang [Mon, 1 May 2017 07:54:34 +0000 (15:54 +0800)]
pinctrl: mediatek: reuse pinctrl driver for mt7623
mt7623 pinctrl hardware can be compatible with mt2701 driver,
so the patch lets the pinctrl on mt7623 SoC reuse the driver
and deletes those redundant ones.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Acked-by: John Crispin <john@phrozen.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Martin Blumenstingl [Sat, 6 May 2017 16:57:51 +0000 (18:57 +0200)]
pinctrl: meson: meson8: add the AO HDMI CEC pin
This adds another missing pin found in the Meson8 SoCs. Currently
there's no driver which would use this pin yet.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Martin Blumenstingl [Sat, 6 May 2017 16:57:50 +0000 (18:57 +0200)]
pinctrl: meson: meson8: add support for the AO remote output pin
This adds another missing pin found in the Meson8 SoCs. Currently
there's no driver which would use this pin yet.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Martin Blumenstingl [Sat, 6 May 2017 16:57:49 +0000 (18:57 +0200)]
pinctrl: meson: meson8: add support for the I2S and SPDIF pins
This adds support for the I2S and SPDIF input and output pins, similar
to what we have on GXBB and GXL.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Martin Blumenstingl [Sat, 6 May 2017 16:57:48 +0000 (18:57 +0200)]
pinctrl: meson: meson8: add the PWM pins
This adds the missing pins for the PWM controllers found in Amlogic
Meson8 SoCs. This includes the pins for PWM_A, PWM_B, PWM_C, PWM_D,
PWM_E and PWM_F controllers.
There is an additional PWM function with the name PWM_VS in the vendor
kernel sources which seems to be used for external video input. Thus
it's not part of this change as the IP block behind the pwm-meson driver
is not responsible for these pins.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Markus Elfring [Tue, 2 May 2017 09:04:55 +0000 (11:04 +0200)]
pinctrl: Adjust nine checks for null pointers
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The script “checkpatch.pl” pointed information out like the following.
Comparison to NULL could be written …
Thus fix the affected source code places.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Markus Elfring [Tue, 2 May 2017 08:47:35 +0000 (10:47 +0200)]
pinctrl: Use seq_putc() in pinctrl_maps_show()
A single character (line break) should be put into a sequence.
Thus use the corresponding function "seq_putc".
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Markus Elfring [Tue, 2 May 2017 08:32:19 +0000 (10:32 +0200)]
pinctrl: Add spaces for better code readability
The script "checkpatch.pl" pointed information out like the following.
CHECK: spaces preferred around that '+' (ctx:VxV)
Thus fix the affected source code places.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Markus Elfring [Tue, 2 May 2017 08:22:47 +0000 (10:22 +0200)]
pinctrl: Combine substrings for a message in pin_config_group_get()
The script "checkpatch.pl" pointed information out like the following.
WARNING: quoted string split across lines
Thus fix the affected source code place.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Markus Elfring [Tue, 2 May 2017 08:01:57 +0000 (10:01 +0200)]
pinctrl: Adjust five checks for null pointers
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The script “checkpatch.pl” pointed information out like the following.
Comparison to NULL could be written !…
Thus fix the affected source code places.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Markus Elfring [Tue, 2 May 2017 07:52:50 +0000 (09:52 +0200)]
pinctrl: Replace two seq_printf() calls by seq_puts() in pinconf_show_map()
Strings which did not contain data format specifications should be put
into a sequence. Thus use the corresponding function "seq_puts".
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Shyam Sundar S K [Wed, 3 May 2017 06:29:11 +0000 (11:59 +0530)]
pinctrl/amd: Update contact information for AMD pinctrl/amd
Updating the point of contact for AMD GPIO driver.
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Signed-off-by: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
Cc: Ken Xue <Ken.Xue@amd.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>