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Hans Wennborg [Fri, 21 Apr 2017 21:48:41 +0000 (21:48 +0000)]
Re-commit r301040 "X86: Don't emit zero-byte functions on Windows"
In addition to the original commit, tighten the condition for when to
pad empty functions to COFF Windows. This avoids running into problems
when targeting e.g. Win32 AMDGPU, which caused test failures when this
was committed initially.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301047
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Frederich Munch [Fri, 21 Apr 2017 21:39:50 +0000 (21:39 +0000)]
[Test commit] Remove extra newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301046
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Matt Arsenault [Fri, 21 Apr 2017 21:35:04 +0000 (21:35 +0000)]
InferAddressSpaces: Infer for just GEPs
Fixes leaving intermediate flat addressing computations
where a GEP instruction's source is a constant expression.
Still leaves behind a trivial addrspacecast + gep pair that
instcombine is able to handle, which ideally could be folded
here directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301044
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Xinliang David Li [Fri, 21 Apr 2017 21:20:56 +0000 (21:20 +0000)]
[PartialInliner] Partial inliner needs to check use kind before transformation
Differential Revision: https://reviews.llvm.org/D32373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301042
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Hans Wennborg [Fri, 21 Apr 2017 21:10:37 +0000 (21:10 +0000)]
Revert r301040 "X86: Don't emit zero-byte functions on Windows"
This broke almost all bots. Reverting while fixing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301041
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Hans Wennborg [Fri, 21 Apr 2017 20:58:12 +0000 (20:58 +0000)]
X86: Don't emit zero-byte functions on Windows
Empty functions can lead to duplicate entries in the Guard CF Function
Table of a binary due to multiple functions sharing the same RVA,
causing the kernel to refuse to load that binary.
We had a terrific bug due to this in Chromium.
It turns out we were already doing this for Mach-O in certain
situations. This patch expands the code for that in
AsmPrinter::EmitFunctionBody() and renames
TargetInstrInfo::getNoopForMachoTarget() to simply getNoop() since it
seems it was used for not just Mach-O anyway.
Differential Revision: https://reviews.llvm.org/D32330
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301040
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Zachary Turner [Fri, 21 Apr 2017 20:45:11 +0000 (20:45 +0000)]
Add a dependency from llvm/test to llvm-cvtres.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301038
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Tim Northover [Fri, 21 Apr 2017 20:36:08 +0000 (20:36 +0000)]
AArch64: add test for "fence singlethread"
Forgot a git add yesterday.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301037
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Tim Northover [Fri, 21 Apr 2017 20:35:52 +0000 (20:35 +0000)]
ARM: make sure we use all entries in a vector before forming a vpaddl.
Otherwise there's some mismatch, and we'll either form an illegal type or an
illegal node.
Thanks to Eli Friedman for pointing out the problem with my original solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301036
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Sanjay Patel [Fri, 21 Apr 2017 20:29:17 +0000 (20:29 +0000)]
[InstCombine] revert r300977 and r301021
This can cause an inf-loop. Investigating...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301035
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Zachary Turner [Fri, 21 Apr 2017 20:18:43 +0000 (20:18 +0000)]
Fixed a type conversion error in BitVector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301033
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Zachary Turner [Fri, 21 Apr 2017 20:12:08 +0000 (20:12 +0000)]
[BitVector] Make BitVector store an ArrayRef.
This makes certain operations on the underlying storage
easier since we have access to ArrayRef methods such as
drop_front, drop_back, slice, range-based for loops, etc.
Differential Revision: https://reviews.llvm.org/D32367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301031
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Adrian Prantl [Fri, 21 Apr 2017 20:06:41 +0000 (20:06 +0000)]
typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301030
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Konstantin Zhuravlyov [Fri, 21 Apr 2017 19:57:53 +0000 (19:57 +0000)]
AMDGPU/GFX9: Enable FastFMAF32
Differential Revision: https://reviews.llvm.org/D32363
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301029
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Konstantin Zhuravlyov [Fri, 21 Apr 2017 19:45:22 +0000 (19:45 +0000)]
AMDGPU: Temporarily disable packed inlinable literals (v2f16, v2i16)
Differential Revision: https://reviews.llvm.org/D32361
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301028
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Konstantin Zhuravlyov [Fri, 21 Apr 2017 19:35:05 +0000 (19:35 +0000)]
AMDGPU: Fix S_PACK_HH_B32_B16
- We really ought to zero out lower 16 bits
Differential Revision: https://reviews.llvm.org/D32356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301026
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Yaxun Liu [Fri, 21 Apr 2017 19:32:02 +0000 (19:32 +0000)]
[AMDGPU] Handle SI_MASKED_UNREACHABLE in instruction emitter
SI_MASKED_UNREACHABLE does not have machine instruction encoding.
It needs special handling in AMDGPUAsmPrinter::EmitInstruction like some
other pseudo instructions.
This patch fixes compilation failure of RadeonRays.
Differential Revision: https://reviews.llvm.org/D32364
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301025
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Matthias Braun [Fri, 21 Apr 2017 19:26:45 +0000 (19:26 +0000)]
Revert "X86RegisterInfo: eliminateFrameIndex: Avoid code duplication; NFC"
It seems we have on situation in a sanitizer enable bootstrap build
where the return instruction has a frame index operand that does not
point to a fixed object and fails the assert added here.
This reverts commit r300923.
This reverts commit r300922.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301024
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Konstantin Zhuravlyov [Fri, 21 Apr 2017 19:25:33 +0000 (19:25 +0000)]
AMDGPU: Do not lower fast unsafe div for safe, f32, with fp32 denormals
Differential Revision: https://reviews.llvm.org/D32085
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301023
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Sanjay Patel [Fri, 21 Apr 2017 19:16:52 +0000 (19:16 +0000)]
[InstCombine] use isSubsetOf() for efficiency
C | ~D == -1
~(C | ~D) == 0
~C & D == 0
D & ~C == 0
D.isSubsetOf(C)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301021
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Akira Hatanaka [Fri, 21 Apr 2017 18:53:12 +0000 (18:53 +0000)]
[AArch64] Improve code generation for logical instructions taking
immediate operands.
This commit adds an AArch64 dag-combine that optimizes code generation
for logical instructions taking immediate operands. The optimization
uses demanded bits to change a logical instruction's immediate operand
so that the immediate can be folded into the immediate field of the
instruction.
This recommits r300932 and r300930, which was causing dag-combine to
loop forever. The problem was that optimizeLogicalImm was returning
true even when there was no change to the immediate node (which happened
when the immediate was all zeros or ones), which caused dag-combine to
push and pop the same node to the work list over and over again without
making any progress.
This commit fixes the bug by returning false early in optimizeLogicalImm
if the immediate is all zeros or ones. Also, it changes the code to
compare the immediate with 0 or Mask rather than calling
countPopulation.
rdar://problem/
18231627
Differential Revision: https://reviews.llvm.org/D5591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301019
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Artur Pilipenko [Fri, 21 Apr 2017 18:45:25 +0000 (18:45 +0000)]
[InstCombine] fadd double (sitofp x), y check that the promotion is valid
Doing these transformations check that the result of integer addition is representable in the FP type.
(fadd double (sitofp x), fpcst) --> (sitofp (add int x, intcst))
(fadd double (sitofp x), (sitofp y)) --> (sitofp (add int x, y))
This is a fix for https://bugs.llvm.org//show_bug.cgi?id=27036
Reviewed By: andrew.w.kaylor, scanon, spatel
Differential Revision: https://reviews.llvm.org/D31182
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301018
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Kuba Mracek [Fri, 21 Apr 2017 18:19:56 +0000 (18:19 +0000)]
Fixup for r301007: Restrict the -D hack to Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301017
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Zachary Turner [Fri, 21 Apr 2017 18:07:46 +0000 (18:07 +0000)]
[BitVector] Add find_last() and find_last_unset().
Differential Revision: https://reviews.llvm.org/D32302
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301014
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Kuba Mracek [Fri, 21 Apr 2017 18:02:22 +0000 (18:02 +0000)]
Revert r301010: Bot failures on Windows, NetBSD and even some old Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301012
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Kuba Mracek [Fri, 21 Apr 2017 17:47:44 +0000 (17:47 +0000)]
[libFuzzer] Always build libFuzzer
There are two reasons why users might want to build libfuzzer:
- To fuzz LLVM itself
- To get the libFuzzer.a archive file, so that they can attach it to their code
This change always builds libfuzzer, and supports the second use case if the specified flag is set.
The point of this patch is to have something that can potentially be shipped with the compiler, and this also ensures that the version of libFuzzer is correct to use with that compiler.
Patch by George Karpenkov.
Differential Revision: https://reviews.llvm.org/D32096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301010
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Kuba Mracek [Fri, 21 Apr 2017 17:39:50 +0000 (17:39 +0000)]
[libFuzzer] Changing thread_local to __thread in libFuzzer
Old Apple compilers do not support thread_local keyword. This patch adds -Dthread_local=__thread when the compiler doesn't support thread_local.
Differential Revision: https://reviews.llvm.org/D32312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301007
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Zachary Turner [Fri, 21 Apr 2017 17:37:31 +0000 (17:37 +0000)]
Add llvm-cvtres to LLVMBuild.txt
It wasn't getting picked up as an implicit project, so it wasn't
being built.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301006
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Joel Jones [Fri, 21 Apr 2017 17:31:03 +0000 (17:31 +0000)]
[AArch64] Refactor instruction selection lowering for addresses. NFCI
Factor out the common code used for generating addresses into common
templated functions that call overloaded versions of a new function,
getTargetNode.
Tested with make check-llvm with targets AArch64.
Differential Revision: https://reviews.llvm.org/D32169
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301005
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Zachary Turner [Fri, 21 Apr 2017 17:30:29 +0000 (17:30 +0000)]
Add empty shell of llvm-cvtres.
This marks the beginning of an effort to port remaining
MSVC toolchain miscellaneous utilities to all platforms.
Currently clang-cl shells out to certain additional tools
such as the IDL compiler, resource compiler, and a few
other tools, but as these tools are Windows-only it
limits the ability of clang to target Windows on other
platforms. having a full suite of these tools directly
in LLVM should eliminate this constraint.
The current implementation provides no actual functionality,
it is just an empty skeleton executable for the purposes
of making incremental changes.
Differential Revision: https://reviews.llvm.org/D32095
Patch by Eric Beckmann (ecbeckmann@google.com)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301004
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Tim Northover [Fri, 21 Apr 2017 17:21:59 +0000 (17:21 +0000)]
ARM: don't try to create an i8 -> i32 vpaddl.
DAG combine was mistakenly assuming that the step-up it was looking at was
always a doubling, but it can sometimes be a larger extension in which case
we'd crash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301002
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Kuba Mracek [Fri, 21 Apr 2017 16:57:37 +0000 (16:57 +0000)]
[libFuzzer] Check for target(popcnt) capability before usage
Older compilers (e.g. LLVM 3.4) do not support the attribute target("popcnt").
In order to support those, this diff check the attribute support using the preprocessor.
Patch by George Karpenkov.
Differential Revision: https://reviews.llvm.org/D32311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300999
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Craig Topper [Fri, 21 Apr 2017 16:43:32 +0000 (16:43 +0000)]
[ValueTracking] Use APInt::setAllBits and APInt::intersects to simplify some code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300997
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Craig Topper [Fri, 21 Apr 2017 16:13:15 +0000 (16:13 +0000)]
[APInt] Add compare/compareSigned methods that return -1, 0, 1. Reimplement slt/ult and friends using them
Currently sle and ule have to call slt/ult and eq to get the proper answer. This results in extra code for both calls and additional scans of multiword APInts.
This patch replaces slt/ult with a compareSigned/compare that can return -1, 0, or 1 so we can cover all the comparison functions with a single call.
While I was there I removed the activeBits calls and other checks at the start of the slow part of ult. Both of the activeBits calls potentially scan through each of the APInts separately. I can't imagine that's any better than just scanning them in parallel and doing the compares. Now we just share the code with tcCompare.
These changes seem to be good for about a 7-8k reduction on the size of the opt binary on my local x86-64 build.
Differential Revision: https://reviews.llvm.org/D32339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300995
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Juergen Ributzka [Fri, 21 Apr 2017 16:05:01 +0000 (16:05 +0000)]
Remove empty and unused header file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300994
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Daniel Sanders [Fri, 21 Apr 2017 15:59:56 +0000 (15:59 +0000)]
[globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule.
Summary:
The SelectionDAG importer now imports rules with Predicate's attached via
Requires, PredicateControl, etc. These predicates are implemented as
bitset's to allow multiple predicates to be tested together. However,
unlike the MC layer subtarget features, each target only pays for it's own
predicates (e.g. AArch64 doesn't have 192 feature bits just because X86
needs a lot).
Both AArch64 and X86 derive at least one predicate from the MachineFunction
or Function so they must re-initialize AvailableFeatures before each
function. They also declare locals in <Target>InstructionSelector so that
computeAvailableFeatures() can use the code from SelectionDAG without
modification.
Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab
Reviewed By: rovka
Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D31418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300993
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Craig Topper [Fri, 21 Apr 2017 15:53:42 +0000 (15:53 +0000)]
[SimplifyCFG] Fix the determination of PostBB in conditional store merging to handle the targets on the second branch being commuted
Currently we choose PostBB as the single successor of QFB, but its possible that QTB's single successor is QFB which would make QFB the correct choice.
Differential Revision: https://reviews.llvm.org/D32323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300992
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Wei Mi [Fri, 21 Apr 2017 15:50:16 +0000 (15:50 +0000)]
[ConstHoisting] Add BFI in constanthoisting pass and select the best insertion
places based on it.
Existing constant hoisting pass will merge a group of contants in a small range
and hoist the const materialization code to the common dominator of their uses.
However, if the uses are all in cold pathes, existing implementation may hoist
the materialization code from cold pathes to a hot place. This may hurt performance.
The patch introduces BFI to the pass and selects the best insertion places based
on it.
The change is controlled by an option consthoist-with-block-frequency which is
off by default for now.
Differential Revision: https://reviews.llvm.org/D28962
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300989
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Chad Rosier [Fri, 21 Apr 2017 14:58:32 +0000 (14:58 +0000)]
[AArch64][Falkor] Refine modeling of store-release exclusive instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300987
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Joel Jones [Fri, 21 Apr 2017 14:49:27 +0000 (14:49 +0000)]
[Mips] Document Mips Backend Relocation Principles
This revision documents the combination of C++ and table-gen code that
handles relocations and addresses.
Thanks for Simon Dardis for the careful reviews.
Differential Revision: https://reviews.llvm.org/D31628
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300986
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Chad Rosier [Fri, 21 Apr 2017 14:33:13 +0000 (14:33 +0000)]
[AArch64][Falkor] Refine resource needs of STRQ with register offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300984
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Matthew Simpson [Fri, 21 Apr 2017 14:14:54 +0000 (14:14 +0000)]
[LV] Model if-converted phi node costs
Phi nodes in non-header blocks are converted to select instructions after
if-conversion. This patch updates the cost model to account for the selects.
Differential Revision: https://reviews.llvm.org/D31906
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300980
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Daniel Sanders [Fri, 21 Apr 2017 14:09:20 +0000 (14:09 +0000)]
Revert r300964 + r300970 - [globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule.
It's causing llvm-clang-x86_64-expensive-checks-win to fail to compile and I
haven't worked out why. Reverting to make it green while I figure it out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300978
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Sanjay Patel [Fri, 21 Apr 2017 14:03:54 +0000 (14:03 +0000)]
[InstCombine] prefer xor with -1 because 'not' is easier to understand (PR32706)
This matches the demanded bits behavior in the DAG and should fix:
https://bugs.llvm.org/show_bug.cgi?id=32706
Differential Revision: https://reviews.llvm.org/D32255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300977
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Chad Rosier [Fri, 21 Apr 2017 13:55:41 +0000 (13:55 +0000)]
[AArch64][Falkor] Refine loads/stores that require an extra LD pipe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300976
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Chad Rosier [Fri, 21 Apr 2017 13:37:01 +0000 (13:37 +0000)]
[AArch64][Falkor] Fix number of microops for WriteSTIdx missed in r300892.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300975
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Chad Rosier [Fri, 21 Apr 2017 13:36:57 +0000 (13:36 +0000)]
[AArch64] Fix a few missed pre/post-inc in Falkor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300974
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Diana Picus [Fri, 21 Apr 2017 13:16:50 +0000 (13:16 +0000)]
[ARM] GlobalISel: Add support for G_TRUNC
Select them as copies. We only select if both the source and the
destination are on the same register bank, so this shouldn't cause any
trouble.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300971
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Daniel Sanders [Fri, 21 Apr 2017 12:51:43 +0000 (12:51 +0000)]
[globalisel][tablegen] Try again to fix builds on old MSVC's after r300964
This should fix llvm-clang-x86_64-expensive-checks-win
I reproduced the error using the following code:
namespace llvm {
// Moving this out of the llvm namespace fixes the error.
template<unsigned NumBits> class PredicateBitsetImpl {};
}
namespace {
const unsigned MAX_SUBTARGET_PREDICATES = 11;
// This works on Clang but is broken on MSVC
// using PredicateBitset = PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
// Some versions emit a syntax error here ("error C2061: syntax error: identifier
// 'PredicateBitsetImpl'") but others accept it and only emit the C3646 below.
//
// This works on Clang and MSVC
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
class Foo {
private:
PredicateBitset A; // error C3646: 'A': unknown override specifier
};
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300970
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Daniel Sanders [Fri, 21 Apr 2017 12:08:25 +0000 (12:08 +0000)]
Revert: r300966 - [globalisel][tablegen] Attempt to fix builds on old MSVC's after r300964
It didn't fix the builder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300968
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Diana Picus [Fri, 21 Apr 2017 11:53:01 +0000 (11:53 +0000)]
[ARM] GlobalISel: Make struct arguments fail elegantly
The condition in isSupportedType didn't handle struct/array arguments
properly. Fix the check and add a test to make sure we use the fallback
path in this kind of situation. The test deals with some common cases
where the call lowering should error out. There are still some issues
here that need to be addressed (tail calls come to mind), but they can
be addressed in other patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300967
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Daniel Sanders [Fri, 21 Apr 2017 11:29:29 +0000 (11:29 +0000)]
[globalisel][tablegen] Attempt to fix builds on old MSVC's after r300964
This should fix llvm-clang-x86_64-expensive-checks-win
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300966
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Daniel Sanders [Fri, 21 Apr 2017 10:27:20 +0000 (10:27 +0000)]
[globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule.
Summary:
The SelectionDAG importer now imports rules with Predicate's attached via
Requires, PredicateControl, etc. These predicates are implemented as
bitset's to allow multiple predicates to be tested together. However,
unlike the MC layer subtarget features, each target only pays for it's own
predicates (e.g. AArch64 doesn't have 192 feature bits just because X86
needs a lot).
Both AArch64 and X86 derive at least one predicate from the MachineFunction
or Function so they must re-initialize AvailableFeatures before each
function. They also declare locals in <Target>InstructionSelector so that
computeAvailableFeatures() can use the code from SelectionDAG without
modification.
Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab
Reviewed By: rovka
Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D31418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300964
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Clement Courbet [Fri, 21 Apr 2017 09:21:05 +0000 (09:21 +0000)]
typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300963
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Clement Courbet [Fri, 21 Apr 2017 09:21:01 +0000 (09:21 +0000)]
add skylake
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300962
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Clement Courbet [Fri, 21 Apr 2017 09:20:58 +0000 (09:20 +0000)]
add 32 bit tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300961
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Clement Courbet [Fri, 21 Apr 2017 09:20:55 +0000 (09:20 +0000)]
use repmovsb when optimizing forminsize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300960
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Clement Courbet [Fri, 21 Apr 2017 09:20:50 +0000 (09:20 +0000)]
Rename FastString flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300959
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Clement Courbet [Fri, 21 Apr 2017 09:20:44 +0000 (09:20 +0000)]
add more tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300958
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Clement Courbet [Fri, 21 Apr 2017 09:20:39 +0000 (09:20 +0000)]
X86 memcpy: use REPMOVSB instead of REPMOVS{Q,D,W} for inline copies
when the subtarget has fast strings.
This has two advantages:
- Speed is improved. For example, on Haswell thoughput improvements increase
linearly with size from 256 to 512 bytes, after which they plateau:
(e.g. 1% for 260 bytes, 25% for 400 bytes, 40% for 508 bytes).
- Code is much smaller (no need to handle boundaries).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300957
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George Rimar [Fri, 21 Apr 2017 09:12:18 +0000 (09:12 +0000)]
[DWARF] - Refactoring: localize handling of relocations in a single place.
This is splitted from D32228,
currently DWARF parsers code has few places that applied relocations values manually.
These places has similar duplicated code. Patch introduces separate method that can be
used to obtain relocated value. That helps to reduce code and simplifies things.
Differential revision: https://reviews.llvm.org/D32284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300956
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Clement Courbet [Fri, 21 Apr 2017 07:40:59 +0000 (07:40 +0000)]
Delete dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300952
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Artyom Skrobov [Fri, 21 Apr 2017 07:35:21 +0000 (07:35 +0000)]
[Thumb1] The recently added tADCS and tSBCS pseudo-instructions were missing `Uses = [CPSR]`
Summary: Thanks to Oliver Stannard for helping catch this.
Reviewers: olista01, efriedma
Subscribers: llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D31815
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300951
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Serguei Katkov [Fri, 21 Apr 2017 06:14:38 +0000 (06:14 +0000)]
[AsmWriter] Eliminate warning. NFC
This patch eliminates the following warning
lib/IR/AsmWriter.cpp:1128:57: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
(StrVal[1] >= '0' && StrVal[1] <= '9')) &&
Reviewers: timshen, rnk, davide
Reviewed By: davide
Subscribers: davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D32337
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300950
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George Burgess IV [Fri, 21 Apr 2017 04:54:52 +0000 (04:54 +0000)]
[MSSA] Clean up the updater a bit. NFC
- Mark an internal function static
- Remove the llvm namespace (just holding on to the `using namespace
llvm;` Works on My Machine(TM))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300947
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Davide Italiano [Fri, 21 Apr 2017 04:25:00 +0000 (04:25 +0000)]
[PartialInliner] Fix crash when inlining functions with unreachable blocks.
CodeExtractor looks up the dominator node corresponding to return blocks
when splitting them. If one of these blocks is unreachable, there's no
node in the Dom and CodeExtractor crashes because it doesn't check
for domtree node validity.
In theory, we could add just a check for skipping null DTNodes in
`splitReturnBlock` but the fix I propose here is slightly different. To the
best of my knowledge, unreachable blocks are irrelevant for the algorithm,
therefore we can just skip them when building the candidate set in the
constructor.
Differential Revision: https://reviews.llvm.org/D32335
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300946
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Serguei Katkov [Fri, 21 Apr 2017 03:14:30 +0000 (03:14 +0000)]
[BPI] Add multiplication by scalar operators to BranchProbability
This patch just adds two operators to BranchProbability class:
(BP * scalar) and (BP *= scalar).
Reviewers: junbuml, chandlerc, sanjoy, vsk
Reviewed By: chandlerc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D32334
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300945
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Serguei Katkov [Fri, 21 Apr 2017 02:52:17 +0000 (02:52 +0000)]
[AsmWriter/APFloat] FP constant printing: Avoid usage of locale dependent snprinf
This should fix the bug https://bugs.llvm.org/show_bug.cgi?id=12906
To print the FP constant AsmWriter does the following:
1) convert FP value to String (actually using snprintf function which is locale dependent).
2) Convert String back to FP Value
3) Compare original and got FP values. If they are not equal just dump as hex.
The problem happens on the 2nd step when APFloat does not expect group delimiter or
fraction delimiter other than period symbol and so on, which can be produced on the
first step if LLVM library is used in an environment with corresponding locale set.
To fix this issue the locale independent APFloat:toString function is used.
However it prints FP values slightly differently than snprintf does. Specifically
it suppress trailing zeros in significant, use capital E and so on.
It results in 117 test failures during make check.
To avoid this I've also updated APFloat.toString a bit to pass make check at least.
Reviewers: sberg, bogner, majnemer, sanjoy, timshen, rnk
Reviewed By: timshen, rnk
Subscribers: rnk, llvm-commits
Differential Revision: https://reviews.llvm.org/D32276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300943
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Akira Hatanaka [Fri, 21 Apr 2017 01:31:50 +0000 (01:31 +0000)]
Revert r300932 and r300930.
It seems that r300930 was creating an infinite loop in dag-combine when
compling the following file:
MultiSource/Benchmarks/MiBench/consumer-typeset/z21.c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300940
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Akira Hatanaka [Fri, 21 Apr 2017 00:35:27 +0000 (00:35 +0000)]
[AArch64] Use suffix ULL to shift a 64-bit value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300932
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Davide Italiano [Fri, 21 Apr 2017 00:21:09 +0000 (00:21 +0000)]
[CodeExtractor] Remove an unneeded level of indirection. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300931
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Akira Hatanaka [Fri, 21 Apr 2017 00:05:16 +0000 (00:05 +0000)]
[AArch64] Improve code generation for logical instructions taking
immediate operands.
This commit adds an AArch64 dag-combine that optimizes code generation
for logical instructions taking immediate operands. The optimization
uses demanded bits to change a logical instruction's immediate operand
so that the immediate can be folded into the immediate field of the
instruction.
This recommits r300913, which broke bots because I didn't fix a call to
ShrinkDemandedConstant in SIISelLowering.cpp after changing the APIs of
TargetLoweringOpt and TargetLowering.
rdar://problem/
18231627
Differential Revision: https://reviews.llvm.org/D5591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300930
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Eli Friedman [Thu, 20 Apr 2017 23:59:05 +0000 (23:59 +0000)]
Revert r300746 (SCEV analysis for or instructions).
There have been multiple reports of this causing problems: a
compile-time explosion on the LLVM testsuite, and a stack
overflow for an opencl kernel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300928
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Craig Topper [Thu, 20 Apr 2017 23:58:27 +0000 (23:58 +0000)]
[InstCombine] Remove the zextOrTrunc from ShrinkDemandedConstant.
The demanded mask and the constant should always be the same width for all callers today.
Also stop copying the demanded mask as its passed in. We should avoid allocating memory unless we are going to do something. The final AND to create the new constant will take care of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300927
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Matthias Braun [Thu, 20 Apr 2017 23:34:50 +0000 (23:34 +0000)]
X86RegisterInfo: eliminateFrameIndex: Avoid code duplication; NFC
X86RegisterInfo::eliminateFrameIndex() and
X86FrameLowering::getFrameIndexReference() both had logic to compute the
base register. This consolidates the code.
Also use MachineInstr::isReturn instead of manually enumerating tail
call instructions (return instructions were not included in the previous
list because they never reference frame indexes).
Differential Revision: https://reviews.llvm.org/D32206
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300923
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Matthias Braun [Thu, 20 Apr 2017 23:34:46 +0000 (23:34 +0000)]
X86RegisterInfo: eliminateFrameIndex: Force SP for AfterFPPop; NFC
AfterFPPop is used for tailcall/tailjump instructions. We shouldn't ever
have frame-pointer/base-pointer relative addressing for those. After all
the frame/base pointer should already be restored to their previous
values at the return.
Make this fact explicit in preparation for an upcoming refactoring.
Differential Revision: https://reviews.llvm.org/D32205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300922
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Sanjoy Das [Thu, 20 Apr 2017 23:07:00 +0000 (23:07 +0000)]
Fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300918
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Akira Hatanaka [Thu, 20 Apr 2017 23:03:30 +0000 (23:03 +0000)]
Revert "[AArch64] Improve code generation for logical instructions taking"
This reverts r300913.
This broke bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300916
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Craig Topper [Thu, 20 Apr 2017 22:57:36 +0000 (22:57 +0000)]
[Simplify] Add testcase to show that merging conditional stores for triangles is sensitive to the order of the branch targets on the conditional branches. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300915
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Akira Hatanaka [Thu, 20 Apr 2017 22:47:56 +0000 (22:47 +0000)]
[AArch64] Improve code generation for logical instructions taking
immediate operands.
This commit adds an AArch64 dag-combine that optimizes code generation
for logical instructions taking immediate operands. The optimization
uses demanded bits to change a logical instruction's immediate operand
so that the immediate can be folded into the immediate field of the
instruction.
rdar://problem/
18231627
Differential Revision: https://reviews.llvm.org/D5591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300913
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Sanjay Patel [Thu, 20 Apr 2017 22:37:01 +0000 (22:37 +0000)]
[InstCombine] function names start with lower-case letter; NFC
Forgot to make this fix with the signature change in r300911.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300912
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Sanjay Patel [Thu, 20 Apr 2017 22:33:54 +0000 (22:33 +0000)]
[InstCombine] allow shl+shr demanded bits folds with splat constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300911
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Sanjay Patel [Thu, 20 Apr 2017 22:18:47 +0000 (22:18 +0000)]
[InstCombine] add tests for shl+shr demanded bits splat vector folds; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300907
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Tim Northover [Thu, 20 Apr 2017 21:57:45 +0000 (21:57 +0000)]
AArch64: lower "fence singlethread" to a pure compiler barrier.
Single-threaded fences aren't required to provide any synchronization with
other processing elements so there's no need for a DMB. They should still be a
barrier for compiler optimizations though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300905
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Tim Northover [Thu, 20 Apr 2017 21:56:52 +0000 (21:56 +0000)]
ARM: lower "fence singlethread" to a pure compiler barrier.
Single-threaded fences aren't required to provide any synchronization with
other processing elements so there's no need for a DMB. They should still be a
barrier for compiler optimizations though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300904
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Xinliang David Li [Thu, 20 Apr 2017 21:40:22 +0000 (21:40 +0000)]
Use basicblock split block utility function
Instead of calling BasicBlock::SplitBasicBlock directly in
CodeExtractor.
Differential Revision: https://reviews.llvm.org/D32308
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300899
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Sanjay Patel [Thu, 20 Apr 2017 21:33:02 +0000 (21:33 +0000)]
[InstCombine] allow shl demanded bits folds with splat constants
More fixes are needed to enable the helper SimplifyShrShlDemandedBits().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300898
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Craig Topper [Thu, 20 Apr 2017 21:24:37 +0000 (21:24 +0000)]
[InstCombine] Use APInt::intersects and APInt::isSubsetOf to improve a few more places in SimplifyDemandedBits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300896
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Chad Rosier [Thu, 20 Apr 2017 21:11:17 +0000 (21:11 +0000)]
[AArch64] Whitespace/ordering fixes for Falkor machine description. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300893
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Chad Rosier [Thu, 20 Apr 2017 21:11:09 +0000 (21:11 +0000)]
[AArch64] Refine Falkor machine description for pre/post-inc and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300892
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Sanjay Patel [Thu, 20 Apr 2017 20:59:02 +0000 (20:59 +0000)]
[InstCombine] allow ashr/lshr demanded bits folds with splat constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300888
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Craig Topper [Thu, 20 Apr 2017 20:47:35 +0000 (20:47 +0000)]
[InstCombine] Use APInt::isSubsetOf to simplify some code in SimplifyDemandedBits. NFC
This allows us to use less temporary APInt for And and Invert operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300885
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Sanjay Patel [Thu, 20 Apr 2017 20:44:54 +0000 (20:44 +0000)]
[InstCombine] add tests for demanded bits ashr/lshr splat constants; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300884
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Adrian Prantl [Thu, 20 Apr 2017 20:42:33 +0000 (20:42 +0000)]
Don't emit locations that need a DW_OP_stack_value in DWARF 2 & 3.
https://bugs.llvm.org/show_bug.cgi?id=32382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300883
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Benjamin Kramer [Thu, 20 Apr 2017 20:28:18 +0000 (20:28 +0000)]
[Support] Make asan poisoning for recyclers more aggressive by also poisoning the 'next' pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300882
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Benjamin Kramer [Thu, 20 Apr 2017 20:03:36 +0000 (20:03 +0000)]
Remove stray ^S. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300880
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Paul Robinson [Thu, 20 Apr 2017 20:03:03 +0000 (20:03 +0000)]
[DWARF] Fix a couple of typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300879
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Tim Northover [Thu, 20 Apr 2017 19:54:02 +0000 (19:54 +0000)]
ARM: handle post-indexed NEON ops where the offset isn't the access width.
Before, we assumed that any ConstantInt offset was precisely the access width,
so we could use the "[rN]!" form. ISelLowering only ever created that kind, but
further simplification during combining could lead to unexpected constants and
incorrect codegen.
Should fix PR32658.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300878
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Adrian McCarthy [Thu, 20 Apr 2017 19:34:06 +0000 (19:34 +0000)]
VarStreamArrayIterator needed non-const operator* overload.
Without this change, the operator-> provided by iterator_facade lost type
qualifiers.
Differential Revision: https://reviews.llvm.org/D32235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300877
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Craig Topper [Thu, 20 Apr 2017 19:31:22 +0000 (19:31 +0000)]
[InstCombine] Remove redundant code from SimplifyDemandedBits handling for Or. The code above it is equivalent if you work through the bitwise math.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300876
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