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Simon Pilgrim [Thu, 7 Dec 2017 15:46:58 +0000 (15:46 +0000)]
[X86] Add SALC scheduling test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320052
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Simon Pilgrim [Thu, 7 Dec 2017 15:24:14 +0000 (15:24 +0000)]
[X86] Tag LZCNT/TZCNT instructions scheduler classes
Tagged as IMUL instructions for a reasonable approximation (ALU tends to be a lot faster) - POPCNT is currently tagged as FAdd which I think should be replaced with IMUL as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320051
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Sanjay Patel [Thu, 7 Dec 2017 15:17:58 +0000 (15:17 +0000)]
[DAGCombiner] eliminate shuffle of insert element
I noticed this pattern in D38316 / D38388. We failed to combine a shuffle that is either
repeating a scalar insertion at the same position in a vector or translated to a different
element index.
Like the earlier patch, this could be an instcombine too, but since we opted to make this
a DAG transform earlier, I've made this one a DAG patch too.
We do not need any legality checking because the new insert is identical to the existing
insert except that it may have a different constant insertion operand.
The constant insertion test in test/CodeGen/X86/vector-shuffle-combining.ll was the
motivation for D38756.
Differential Revision: https://reviews.llvm.org/D40209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320050
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Igor Laevsky [Thu, 7 Dec 2017 15:00:52 +0000 (15:00 +0000)]
[InstCombine] Don't crash on out of bounds index in the insertelement
Differential Revision: https://reviews.llvm.org/D40390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320049
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Simon Pilgrim [Thu, 7 Dec 2017 14:51:47 +0000 (14:51 +0000)]
[X86][FMA] Regenerate fma schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320048
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Simon Pilgrim [Thu, 7 Dec 2017 14:35:17 +0000 (14:35 +0000)]
[X86][SVM] Tag SVM instructions scheduler classes
Tagged all as system instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320047
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Francis Visoiu Mistrih [Thu, 7 Dec 2017 14:32:15 +0000 (14:32 +0000)]
[CodeGen] Use more getMFIfAvailable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320046
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Simon Pilgrim [Thu, 7 Dec 2017 14:18:48 +0000 (14:18 +0000)]
[X86] Tag RDRAND/RDSEED instruction scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320045
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Simon Pilgrim [Thu, 7 Dec 2017 14:07:18 +0000 (14:07 +0000)]
[X86][X87] X87 math binop pseudo instructions don't need scheduling info
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320044
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Simon Pilgrim [Thu, 7 Dec 2017 13:52:07 +0000 (13:52 +0000)]
[X86][SSE42] SSE42 string pseudo instructions don't need scheduling info
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320043
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Simon Pilgrim [Thu, 7 Dec 2017 13:50:29 +0000 (13:50 +0000)]
[X86] Regenerate RDTSC codegen tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320042
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Dan Gohman [Thu, 7 Dec 2017 13:49:27 +0000 (13:49 +0000)]
[WebAssemby] Support main functions with alternate signatures.
WebAssembly requires caller and callee signatures to match, so the usual
C runtime trick of calling main and having it just work regardless of
whether main is defined as '()' or '(int argc, char *argv[])' doesn't
work. Extend the FixFunctionBitcasts pass to rewrite main to use the
latter form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320041
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Simon Pilgrim [Thu, 7 Dec 2017 13:47:17 +0000 (13:47 +0000)]
[X86][RDSEED] Add rdseed scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320040
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Simon Pilgrim [Thu, 7 Dec 2017 13:46:47 +0000 (13:46 +0000)]
[X86][RDRAND] Add rdrand scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320039
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Alex Bradbury [Thu, 7 Dec 2017 13:19:57 +0000 (13:19 +0000)]
[RISCV] MC layer support for the jump/branch instructions of the RVC extension
Differential Revision: https://reviews.llvm.org/D40002
Patch by Shiva Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320038
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Alex Bradbury [Thu, 7 Dec 2017 12:50:32 +0000 (12:50 +0000)]
[RISCV] MC layer support for load/store instructions of the C (compressed) extension
Differential Revision: https://reviews.llvm.org/D40001
Patch by Shiva Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320037
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Alex Bradbury [Thu, 7 Dec 2017 12:45:05 +0000 (12:45 +0000)]
[RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in storeRegToStackSlot/loadReadFromStackSlot
Simply checking for register class equality will break once additional
register classes are added (as is done for the RVC instruction set extension).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320036
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Nikolai Bozhenov [Thu, 7 Dec 2017 12:35:02 +0000 (12:35 +0000)]
[Nios2] final infrastructure to provide compilation of a return from a function
This patch includes all missing functionality needed to provide first
compilation of a simple program that just returns from a function.
I've added a test case that checks for "ret" instruction printed in assembly
output.
Patch by Andrei Grischenko (andrei.l.grischenko@intel.com)
Differential revision: https://reviews.llvm.org/D39688
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320035
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Andrew V. Tischenko [Thu, 7 Dec 2017 11:19:49 +0000 (11:19 +0000)]
Add proper BTVER2 sched support for MOV instr.
Differential Revision: https://reviews.llvm.org/D40345
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320034
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Jonas Devlieghere [Thu, 7 Dec 2017 11:17:19 +0000 (11:17 +0000)]
[dsymutil] Add -verify option to run DWARF verifier after linking.
This patch adds support for running the DWARF verifier on the linked
debug info files. If the -verify options is specified and verification
fails, dsymutil exists with abort with non-zero exit code. This behavior
is *not* enabled by default.
Differential revision: https://reviews.llvm.org/D40777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320033
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Igor Laevsky [Thu, 7 Dec 2017 11:10:11 +0000 (11:10 +0000)]
[FuzzMutate] Allow only sized pointers for the GEP instruction
Differential Revision: https://reviews.llvm.org/D40837
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320032
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Alex Bradbury [Thu, 7 Dec 2017 11:05:38 +0000 (11:05 +0000)]
[RISCV] Add missed tests for RV64D MC layer support
Add tests missed in r320029.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320031
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Alex Bradbury [Thu, 7 Dec 2017 11:04:18 +0000 (11:04 +0000)]
[RISCV] MC layer support for the standard RV64D instruction set extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320029
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Alex Bradbury [Thu, 7 Dec 2017 11:02:55 +0000 (11:02 +0000)]
[RISCV] MC layer support for the standard RV64F instruction set extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320028
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Alex Bradbury [Thu, 7 Dec 2017 10:59:12 +0000 (10:59 +0000)]
[RISCV] MC layer support for the standard RV64A instruction set extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320027
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Alex Bradbury [Thu, 7 Dec 2017 10:56:07 +0000 (10:56 +0000)]
[RISCV] MC layer support for the standard RV64M instruction set extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320026
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Pavel Labath [Thu, 7 Dec 2017 10:54:23 +0000 (10:54 +0000)]
[Testing/Support] Make matchers work with Expected<T&>
Summary:
This did not work because the ExpectedHolder was trying to hold the
value in an Optional<T*>. Instead of trying to mimic the behavior of
Expected and try to make ExpectedHolder work with references and
non-references, I simply store the reference to the Expected object in
the holder.
I also add a bunch of tests for these matchers, which have helped me
flesh out some problems in my initial implementation of this patch, and
uncovered the fact that we are not consistent in quoting our values in
the matcher output (which I also fix).
Reviewers: zturner, chandlerc
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D40904
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320025
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Alex Bradbury [Thu, 7 Dec 2017 10:53:48 +0000 (10:53 +0000)]
[RISCV] MC layer support for the standard RV64I instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320024
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Alex Bradbury [Thu, 7 Dec 2017 10:46:23 +0000 (10:46 +0000)]
[RISCV] MC layer support for the standard RV32D instruction set extension
As the FPR32 and FPR64 registers have the same names, use
validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an
FPR64 when necessary. The rest of this patch is very similar to the RV32F
patch.
Differential Revision: https://reviews.llvm.org/D39895
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320023
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Francis Visoiu Mistrih [Thu, 7 Dec 2017 10:40:31 +0000 (10:40 +0000)]
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
Work towards the unification of MIR and debug output by refactoring the
interfaces.
For MachineOperand::print, keep a simple version that can be easily called
from `dump()`, and a more complex one which will be called from both the
MIRPrinter and MachineInstr::print.
Add extra checks inside MachineOperand for detached operands (operands
with getParent() == nullptr).
https://reviews.llvm.org/D40836
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+)<def> ([^ ]+)/kill: \1 def \2 \3/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: \1 \2 def \3/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: def ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: def \1 \2 def \3/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/<def>//g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<kill>/killed \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use,kill>/implicit killed \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<dead>/dead \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<def[ ]*,[ ]*dead>/dead \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def[ ]*,[ ]*dead>/implicit-def dead \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def>/implicit-def \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use>/implicit \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<internal>/internal \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<undef>/undef \1/g'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320022
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Alex Bradbury [Thu, 7 Dec 2017 10:26:05 +0000 (10:26 +0000)]
[RISCV] MC layer support for the standard RV32F instruction set extension
The most interesting part of this patch is probably the handling of
rounding mode arguments. Sadly, the RISC-V assembler handles floating point
rounding modes as a special "argument" when it would be more consistent to
handle them like the atomics, opcode suffixes. This patch supports parsing
this optional parameter, using InstAlias to allow parsing these floating point
instructions when no rounding mode is specified.
Differential Revision: https://reviews.llvm.org/D39893
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320020
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Alex Bradbury [Thu, 7 Dec 2017 09:51:55 +0000 (09:51 +0000)]
[TableGen] Give the option of tolerating duplicate register names
A number of architectures re-use the same register names (e.g. for both 32-bit
FPRs and 64-bit FPRs). They are currently unable to use the tablegen'erated
MatchRegisterName and MatchRegisterAltName, as tablegen (when built with
asserts enabled) will fail.
When the AllowDuplicateRegisterNames in AsmParser is set, duplicated register
names will be tolerated. A backend can then coerce registers to the desired
register class by (for instance) implementing validateTargetOperandClass.
At least the in-tree Sparc backend could benefit from this, as does RISC-V
(single and double precision floating point registers).
Differential Revision: https://reviews.llvm.org/D39845
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320018
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Gadi Haber [Thu, 7 Dec 2017 09:16:34 +0000 (09:16 +0000)]
[X86][FMA][FMA4]: Adding full coverage of MC encoding for the FMA, FMA4 isa sets.<NFC>
NFC.
Adding MC regressions tests to cover the FMA and FMA4 ISA sets.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets starting revision https://reviews.llvm.org/D39952
Reviewers: craig.topper, RKSimon, zvi
Differential Revision: https://reviews.llvm.org/D40880
Change-Id: Ie39c0edce69ad647076b3d4e816948b2b6e1a9e4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320016
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Gadi Haber [Thu, 7 Dec 2017 09:00:19 +0000 (09:00 +0000)]
[X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>
NFC.
Currently, not all the X86 ISA Sets are covered by the MC regressions tests for X86.
A full coverage needs to be added for each ISA set and for both 32bit and 64bit instructions + registers.
This patch includes MC assembly tests for the X87 32bit and 64bit.
Reviewers: craigt, RKSimon, zvi
Differential Revision: https://reviews.llvm.org/D39952
Change-Id: I55e1719c09a70644a6a4073c720cb5341c80fee9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320015
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Igor Laevsky [Thu, 7 Dec 2017 08:52:24 +0000 (08:52 +0000)]
[InstSimplify] Add tests for the rL319894
Differential Revision: https://reviews.llvm.org/D40650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320014
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Craig Topper [Thu, 7 Dec 2017 08:04:34 +0000 (08:04 +0000)]
[SelectionDAG] In SplitVecOp_EXTRACT_VECTOR_ELT, simplify the code that makes the type byte addressable.
We can just extend the original vector to vXi1 and trust that the legalization process will revisit it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320013
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Craig Topper [Thu, 7 Dec 2017 08:04:33 +0000 (08:04 +0000)]
[SelectionDAG] Use TLI.getVectorIdxTy to determine type for an EXTRACT_VECTOR_ELT index instead of hardcoding MVT::i8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320012
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Mikael Holmen [Thu, 7 Dec 2017 07:01:21 +0000 (07:01 +0000)]
Skip DBG instr in OptimizePHIs when looking for dead PHI cycles
Summary:
Changed use_instructions() to use_nodbg_instructions() when
building an instruction set.
We don't want the presence of debug info to affect the code
we generate.
Reviewers: dblaikie, Eugene.Zelenko, chandlerc, aprantl
Reviewed By: aprantl
Subscribers: aprantl, llvm-commits
Differential Revision: https://reviews.llvm.org/D40882
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320010
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Leslie Zhai [Thu, 7 Dec 2017 06:56:09 +0000 (06:56 +0000)]
[AVR] Override ParseDirective
Reviewers: dylanmckay, kparzysz
Reviewed By: dylanmckay
Differential Revision: https://reviews.llvm.org/D38029
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320009
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Sam Clegg [Thu, 7 Dec 2017 03:05:45 +0000 (03:05 +0000)]
Revert "[WebAssembly] Import the linear memory and function table."
We need to a little time to prepare and lld-side change that
supports this.
Original change: https://reviews.llvm.org/D40875
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320003
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Sam Clegg [Thu, 7 Dec 2017 02:55:51 +0000 (02:55 +0000)]
[WebAssembly] section kind can be code
Currently, when creating a named section, the Wasm
frontend forces it to use `SectionKind::Data`, whereas
in fact C++ does generate code sections with custom
names.
Patch by Nicholas Wilson
Differential Revision: https://reviews.llvm.org/D40906
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320002
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Evgeniy Stepanov [Thu, 7 Dec 2017 01:38:20 +0000 (01:38 +0000)]
Update BitCodeFormat.
Add 2 recently added attributes to list of well-known attributes
in BitCodeFormat.rst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319999
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Davide Italiano [Thu, 7 Dec 2017 01:22:10 +0000 (01:22 +0000)]
[DebugInfo] Explicitly pass a triple to this test.
As we emit different linetables format on different operating
systems, this currently fails on linux. Speculative commit
to fix the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319997
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Davide Italiano [Thu, 7 Dec 2017 00:57:25 +0000 (00:57 +0000)]
[MC/Dwarf] Use the older DWARF linetables format on Darwin.
dsymutil doesn't yet understand the new format and the change,
among others, breaks a large fraction of the debugger tests on
mac OS.
rdar://problem/
35856354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319995
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Alina Sbirlea [Thu, 7 Dec 2017 00:43:19 +0000 (00:43 +0000)]
[ModRefInfo] Replace remaining bit-wise operations with wrappers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319993
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Dan Gohman [Thu, 7 Dec 2017 00:14:30 +0000 (00:14 +0000)]
[WebAssembly] Don't try to emit size information for unsized types
Patch by John Sully!
Fixes PR35164.
Differential Revision: https://reviews.llvm.org/D39519
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319991
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Vedant Kumar [Thu, 7 Dec 2017 00:01:15 +0000 (00:01 +0000)]
[Coverage] Scan ahead for the most-recent completed count (PR35495)
This extends r319391. It teaches the segment builder to emit the right
completed segment when more than one region ends at the same location.
Fixes PR35495.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319990
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Dan Gohman [Wed, 6 Dec 2017 23:57:11 +0000 (23:57 +0000)]
[WebAssembly] Import the linear memory and function table.
Instead of having .o files contain linear-memory and function table
definitions, use imports. This is more consistent with the stack pointer
being imported, and it's consistent with the linker being the one to
decide whether linear memory and function table are imported or defined
in the linked output. This implements tool-conventions #23.
Differential Revision: https://reviews.llvm.org/D40875
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319989
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Matt Morehouse [Wed, 6 Dec 2017 23:32:46 +0000 (23:32 +0000)]
[CMake] Use PRIVATE when linking LLVM fuzzers.
More fuzzers missed by r319840.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319987
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Alina Sbirlea [Wed, 6 Dec 2017 23:12:43 +0000 (23:12 +0000)]
[ModRefInfo] Use ModRefInfo wrappers in FunctionModRefBehavior
when testing for info found only in ModRefInfo [NFC].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319985
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Florian Hahn [Wed, 6 Dec 2017 22:48:36 +0000 (22:48 +0000)]
[AArch64] Add patterns to replace fsub fmul with fma fneg.
Summary:
This patch adds MachineCombiner patterns for transforming
(fsub (fmul x y) z) into (fma x y (fneg z)). This has a lower
latency on micro architectures where fneg is cheap.
Patch based on work by George Steed.
Reviewers: rengolin, joelkevinjones, joel_k_jones, evandro, efriedma
Reviewed By: evandro
Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D40306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319980
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Adam Nemet [Wed, 6 Dec 2017 22:42:24 +0000 (22:42 +0000)]
[LV] Interleaved access vectorization: fix computing new alias info
As a new access is generated spanning across multiple fields, we need to
propagate alias info from all the fields to form the most generic alias info.
rdar://
35602528
Differential Revision: https://reviews.llvm.org/D40617
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319979
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Krzysztof Parzyszek [Wed, 6 Dec 2017 22:41:49 +0000 (22:41 +0000)]
[Hexagon] Recognize vdealb, vdealh, vshuffb and vshuffh specifically
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319978
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Krzysztof Parzyszek [Wed, 6 Dec 2017 21:25:03 +0000 (21:25 +0000)]
[Hexagon] Handle perfect shuffles on single vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319965
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Sanjay Patel [Wed, 6 Dec 2017 21:22:57 +0000 (21:22 +0000)]
[InstCombine] canonicalize constant-minus-boolean to select-of-constants
This restores the half of:
https://reviews.llvm.org/rL75531
that was reverted at:
https://reviews.llvm.org/rL159230
For the x86 case mentioned there, we now produce:
leal 1(%rdi), %eax
subl %esi, %eax
We have target hooks to invert this in DAGCombiner (and x86 is enabled) with:
https://reviews.llvm.org/rL296977
https://reviews.llvm.org/rL311731
AArch64 and possibly other targets would probably benefit from enabling those hooks too.
See PR30327:
https://bugs.llvm.org/show_bug.cgi?id=30327#c2
Differential Revision: https://reviews.llvm.org/D40612
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319964
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Matthew Simpson [Wed, 6 Dec 2017 21:22:54 +0000 (21:22 +0000)]
[PGO] Make indirect call promotion a utility
This patch factors out the main code transformation utilities in the pgo-driven
indirect call promotion pass and places them in Transforms/Utils. The change is
intended to be a non-functional change, letting non-pgo-driven passes share a
common implementation with the existing pgo-driven pass.
The common utilities are used to conditionally promote indirect call sites to
direct call sites. They perform the underlying transformation, and do not
consider profile information. The pgo-specific details (e.g., the computation
of branch weight metadata) have been left in the indirect call promotion pass.
Differential Revision: https://reviews.llvm.org/D40658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319963
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Dan Gohman [Wed, 6 Dec 2017 21:16:04 +0000 (21:16 +0000)]
[WebAssembly] Commit a file I accidentally omitted from r319956.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319962
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Dan Gohman [Wed, 6 Dec 2017 20:56:40 +0000 (20:56 +0000)]
[WebAssembly] Remove WASM_STACK_POINTER.
WASM_STACK_POINTER and the .stack_pointer directive are no longer needed
now that the stack pointer global is an import.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319956
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Florian Hahn [Wed, 6 Dec 2017 20:27:33 +0000 (20:27 +0000)]
[MachineCombiner] Add up latencies of all instructions in new pattern.
Summary:
When calculating the RootLatency, we add up all the latencies of the
deleted instructions. But for NewRootLatency we only add the latency of
the new root instructions, ignoring the latencies of the other
instructions inserted. This leads the combiner to underestimate the cost
of patterns which add multiple instructions. This patch fixes that by
summing up the latencies of all new instructions. For NewRootNode, the
more complex getLatency function is used.
Note that we may be slightly more precise than just summing up
all latencies. For example, consider a pattern like
r1 = INS1 ..
r2 = INS2 ..
r3 = INS3 r1, r2
I think in some other places, the total latency of the pattern would be
estimated as lat(INS3) + max(lat(INS1), lat(INS2)). If you consider
that worth changing, I think it would be best to do in a follow-up
patch.
Reviewers: Gerolf, sebpop, spop, fhahn
Reviewed By: fhahn
Subscribers: evandro, llvm-commits
Differential Revision: https://reviews.llvm.org/D40307
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319951
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Alina Sbirlea [Wed, 6 Dec 2017 19:56:37 +0000 (19:56 +0000)]
[ModRefInfo] Do not use ModRefInfo result in if conditions as this makes
assumptions about the values in the enum. Replace with wrapper returning
bool [NFC].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319949
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Florian Hahn [Wed, 6 Dec 2017 19:47:24 +0000 (19:47 +0000)]
[InlineFunction] Only replace call if there are VarArgs to forward.
Summary:
There is no need to replace the original call instruction if no
VarArgs need to be forwarded.
Reviewers: davide, rnk, majnemer, efriedma
Reviewed By: efriedma
Subscribers: eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D40412
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319947
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Sanjay Patel [Wed, 6 Dec 2017 19:37:00 +0000 (19:37 +0000)]
[LoopUtils] simplify createTargetReduction(); NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319946
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Simon Pilgrim [Wed, 6 Dec 2017 19:36:00 +0000 (19:36 +0000)]
[X86][AVX512] Tag mask reg op instruction scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319945
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Tim Shen [Wed, 6 Dec 2017 19:33:42 +0000 (19:33 +0000)]
[Hexagon] Suppress more warnings on unused variables defined for asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319944
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Alina Sbirlea [Wed, 6 Dec 2017 19:23:03 +0000 (19:23 +0000)]
[ModRefInfo] Use createModRefInfo wrapper to create a ModRefInfo from FunctionModRefBehavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319941
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Tim Shen [Wed, 6 Dec 2017 19:22:19 +0000 (19:22 +0000)]
[Hexagon] Suppress warnings on unused variables defind for asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319940
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Rui Ueyama [Wed, 6 Dec 2017 19:18:24 +0000 (19:18 +0000)]
[COFF] Ignore semicolons in module definition identifiers
Patch by David Major.
The NSS project's .def files make heavy use of semicolons in a
frightening attempt at portability:
https://hg.mozilla.org/projects/nss/raw-file/tip/lib/ckfw/capi/nsscapi.def
lld-link was treating the semicolon as part of the export name,
resulting in unresolved symbols. This patch includes ';' in the list of
characters to split on.
Differential Revision: https://reviews.llvm.org/D39968
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319933
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Sanjay Patel [Wed, 6 Dec 2017 19:11:23 +0000 (19:11 +0000)]
[LoopUtils] fix variable name to match FMF vocabulary; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319928
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Zachary Turner [Wed, 6 Dec 2017 18:58:48 +0000 (18:58 +0000)]
Update obj2yaml and yaml2obj for .debug$H section.
Differential Revision: https://reviews.llvm.org/D40842
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319925
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Davide Italiano [Wed, 6 Dec 2017 18:54:17 +0000 (18:54 +0000)]
[Target] dumpr() is defined only in debug builds.
This fixes the clang build on macOS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319923
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Simon Pilgrim [Wed, 6 Dec 2017 18:47:37 +0000 (18:47 +0000)]
[X86][SSE] Regenerate vpmovm2*/vpmov*2m avx512 schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319921
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Simon Pilgrim [Wed, 6 Dec 2017 18:46:06 +0000 (18:46 +0000)]
[X86][AVX512] Tag scalar insert/extract instruction scheduler classes
Classes don't look great but match what we're doing on SSE/AVX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319920
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Craig Topper [Wed, 6 Dec 2017 18:40:46 +0000 (18:40 +0000)]
[X86] Simplify the TTI code for getInterleavedMemoryOpCost around for AVX512BW. NFCI
Previously the lambda for AVX512 passed out a flag that indicated whether AVX512BW was required and that was checked against the AVX512BW subtarget flag outside.
This patch changes the interface to pass the AVX512BW subtarget bit in and return its value if we detect 16 or 8 bit types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319919
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Shoaib Meenai [Wed, 6 Dec 2017 18:33:07 +0000 (18:33 +0000)]
[cmake] Remove unnecessary header include in atomics check
The header include was required to work around PR19898, as noted in that
comment. That PR has since been marked resolved fixed, and the
configuration check passes without the header inclusion both when
compiling on Windows with cl and when cross-compiling on Linux using
clang-cl.
I noticed this because the inclusion was cased incorrectly (Intrin.h
instead of intrin.h), which when cross-compiling on a case sensitive
file system would cause the intrin.h from the Windows SDK to be included
(which LLVM can't handle) instead of the one from clang's resource
directory, making the check fail. This is the same issue as r309980.
Correcting the case of the inclusion makes the check pass when cross
compiling, but it seems better to get rid of the inclusion entirely,
since it appears to be unnecessary now.
Differential Revision: https://reviews.llvm.org/D40910
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319917
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Simon Pilgrim [Wed, 6 Dec 2017 18:24:48 +0000 (18:24 +0000)]
[X86][AVX2] Tag MASKMOV instruction scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319915
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Craig Topper [Wed, 6 Dec 2017 18:04:39 +0000 (18:04 +0000)]
[X86] Regenerate test for r319778
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319914
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Simon Pilgrim [Wed, 6 Dec 2017 17:59:26 +0000 (17:59 +0000)]
[X86][AVX512] Tag aligned/unaligned move instruction scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319913
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Simon Pilgrim [Wed, 6 Dec 2017 17:57:18 +0000 (17:57 +0000)]
[X86][AVX] Regenerate vpmovm2*/vpmov*2m avx512 schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319912
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 6 Dec 2017 17:54:07 +0000 (17:54 +0000)]
[X86] Attempt to fix a ubsan failure in the autoupgrade of kunpck intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319911
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Zvi Rackover [Wed, 6 Dec 2017 17:51:46 +0000 (17:51 +0000)]
InstructionSimplify: 'extractelement' with an undef index is undef
Summary:
An undef extract index can be arbitrarily chosen to be an
out-of-range index value, which would result in the instruction being undef.
This change closes a gap identified while working on lowering vector permute intrinsics
with variable index vectors to pure LLVM IR.
Reviewers: arsenm, spatel, majnemer
Reviewed By: arsenm, spatel
Subscribers: fhahn, nhaehnle, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D40231
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319910
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Artem Belevich [Wed, 6 Dec 2017 17:50:05 +0000 (17:50 +0000)]
[NVPTX,CUDA] Added llvm.nvvm.fns intrinsic and matching __nvvm_fns builtin in clang.
Differential Revision: https://reviews.llvm.org/D40872
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319909
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Zvi Rackover [Wed, 6 Dec 2017 17:40:09 +0000 (17:40 +0000)]
AMDGPU Tests: Change a case to be run with -O0
D40231 requires to run case with -O0 to prevent InstructionSimplify from
transforming an extractelement with undef index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319907
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Jonas Paulsson [Wed, 6 Dec 2017 17:01:08 +0000 (17:01 +0000)]
[SystemZ] Add IntrWriteMem flag to int_s390_tabort intrinsic
Tabort (transaction abort) does not load from memory.
mayLoad flag removed from corresponding TABORT machine instruction.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319905
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Adam Nemet [Wed, 6 Dec 2017 16:50:50 +0000 (16:50 +0000)]
[opt-viewer] Suppress noisy Swift remarks
Most likely, this is not how we want to handle this in the long term. This
code should probably be in the Swift repo and somehow plugged into the
opt-viewer. This is still however very experimental at this point so I don't
want to over-engineer it at this point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319902
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Krzysztof Parzyszek [Wed, 6 Dec 2017 16:40:37 +0000 (16:40 +0000)]
[Hexagon] Generate HVX code for vector construction and access
Support for:
- build vector,
- extract vector element, subvector,
- insert vector element, subvector,
- shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319901
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Simon Pilgrim [Wed, 6 Dec 2017 15:48:40 +0000 (15:48 +0000)]
[X86][AVX512] Tag BROADCAST instruction scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319900
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Nirav Dave [Wed, 6 Dec 2017 15:30:13 +0000 (15:30 +0000)]
[ARM][AArch64][DAG] Reenable post-legalize store merge
Reenable post-legalize stores with constant merging computation and
corresponding test case.
* Properly truncate store merge constants
* Disable merging of truncated stores floating points
* Ensure merges of constant stores into a single vector are
constructed from legal elements.
Reviewers: eastig, efriedma
Reviewed By: eastig
Subscribers: spatel, rengolin, aemerson, javed.absar, kristof.beyls, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D40701
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319899
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Don Hinton [Wed, 6 Dec 2017 15:25:14 +0000 (15:25 +0000)]
[cmake] Move CMAKE_(C|CXX)_COMPILER variables before CROSS_TOOLCHAIN_FLAGS so
they can be overridden when cross compiling.
Summary:
Since CROSS_TOOLCHAN_FLAGS can set CMAKE_(C|CXX)_COMPILER
variables, move the compiler variables up front so they can be
overridden.
This is a followup to https://reviews.llvm.org/D40229 committed in rL319620.
Thanks to Pavel Labath for reporting this issue.
Reviewers: labath, beanz
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D40896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319898
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Simon Pilgrim [Wed, 6 Dec 2017 14:07:38 +0000 (14:07 +0000)]
[X86][AVX512] Regenerate vpmovm2*/vpmov*2m avx512 schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319895
91177308-0d34-0410-b5e6-
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Igor Laevsky [Wed, 6 Dec 2017 14:04:45 +0000 (14:04 +0000)]
[InstSimplify] Fold insertelement into undef if index is out of bounds
Differential Revision: https://reviews.llvm.org/D40650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319894
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Jonas Paulsson [Wed, 6 Dec 2017 13:53:24 +0000 (13:53 +0000)]
[SystemZ] Bugfix in expandRxSBG()
Csmith discovered a program that caused wrong code generation with -O0:
When handling a SIGN_EXTEND in expandRxSBG(), RxSBG.BitSize may be less than
the Input width (if a truncate was previously traversed), so maskMatters()
should be called with a masked based on the width of the sign extend result
instead.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319892
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Benjamin Kramer [Wed, 6 Dec 2017 13:32:36 +0000 (13:32 +0000)]
[X86] Avoid unused variable warning in Release builds. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319891
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 6 Dec 2017 13:14:44 +0000 (13:14 +0000)]
[X86][AVX512] Drop default NoItinerary arguments that aren't needed
Requires reordering of AVX512_maskable_common arguments, but helps track what is still missing itinerary tags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319890
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Max Kazantsev [Wed, 6 Dec 2017 12:44:56 +0000 (12:44 +0000)]
[SCEV][NFC] Check NoWrap flags before lexicographical comparison of SCEVs
Lexicographical comparison of SCEV trees is potentially expensive for big
expression trees. We can define ordering between them for AddRecs and
N-ary operations by SCEV NoWrap flags to make non-equality check
cheaper.
This change does not prevent grouping eqivalent SCEVs together and is
not supposed to have any meaningful impact on behavior of any transforms.
Reviewed By: sanjoy
Differential Revision: https://reviews.llvm.org/D40645
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319889
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Simon Dardis [Wed, 6 Dec 2017 12:42:49 +0000 (12:42 +0000)]
[mips] Fix definition of 'bc' instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319888
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 6 Dec 2017 11:59:05 +0000 (11:59 +0000)]
[X86][AVX512] Tag Mask<->Vector instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319887
91177308-0d34-0410-b5e6-
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Francis Visoiu Mistrih [Wed, 6 Dec 2017 11:57:53 +0000 (11:57 +0000)]
[CodeGen] Fix formatting error from r319885
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319886
91177308-0d34-0410-b5e6-
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Francis Visoiu Mistrih [Wed, 6 Dec 2017 11:55:42 +0000 (11:55 +0000)]
[CodeGen] Better handling of detached MachineOperands
Basically use getMFIfAvailable to check if we can crawl up to the
function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319885
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Simon Pilgrim [Wed, 6 Dec 2017 11:23:13 +0000 (11:23 +0000)]
[X86][AVX512] Cleanup scalar move scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319884
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Mikael Holmen [Wed, 6 Dec 2017 09:27:48 +0000 (09:27 +0000)]
[[Machine]Dominators] Improved printout when verifyDomTree fails [NFC]
Include the function name in the printout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319882
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