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Fangrui Song [Sat, 27 Oct 2018 22:56:04 +0000 (22:56 +0000)]
[utils] Fix _run_benchmark in collect_and_build_with_pgo.py
Summary: Also fix a FIXME in _build_stage1_clang: clang llvm-profdata profile are sufficient
Reviewers: george.burgess.iv
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53795
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345466
91177308-0d34-0410-b5e6-
96231b3b80d8
Renato Golin [Sat, 27 Oct 2018 22:13:43 +0000 (22:13 +0000)]
Revert r344172: [LV] Add a new reduction pattern match
This patch has caused fast-math issues in the reduction pattern.
Will re-work and land again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345465
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Sat, 27 Oct 2018 20:46:30 +0000 (20:46 +0000)]
AMD BdVer2 (Piledriver) Initial Scheduler model
Summary:
# Overview
This is somewhat partial.
* Latencies are good {
F7371125}
* All of these remaining inconsistencies //appear// to be noise/noisy/flaky.
* NumMicroOps are somewhat good {
F7371158}
* Most of the remaining inconsistencies are from `Ld` / `Ld_ReadAfterLd` classes
* Actual unit occupation (pipes, `ResourceCycles`) are undiscovered lands, i did not really look there.
They are basically verbatum copy from `btver2`
* Many `InstRW`. And there are still inconsistencies left...
To be noted:
I think this is the first new schedule profile produced with the new next-gen tools like llvm-exegesis!
# Benchmark
I realize that isn't what was suggested, but i'll start with some "internal" public real-world benchmark i understand - [[ https://github.com/darktable-org/rawspeed | RawSpeed raw image decoding library ]].
Diff (the exact clang from trunk without/with this patch):
```
Comparing /home/lebedevri/rawspeed/build-old/src/utilities/rsbench/rsbench to /home/lebedevri/rawspeed/build-new/src/utilities/rsbench/rsbench
Benchmark Time CPU Time Old Time New CPU Old CPU New
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Canon/EOS 5D Mark II/09.canon.sraw1.cr2/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 25 vs 25
Canon/EOS 5D Mark II/09.canon.sraw1.cr2/threads:8/real_time_mean -0.0607 -0.0604 234 219 233 219
Canon/EOS 5D Mark II/09.canon.sraw1.cr2/threads:8/real_time_median -0.0630 -0.0626 233 219 233 219
Canon/EOS 5D Mark II/09.canon.sraw1.cr2/threads:8/real_time_stddev +0.2581 +0.2587 1 2 1 2
Canon/EOS 5D Mark II/10.canon.sraw2.cr2/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 25 vs 25
Canon/EOS 5D Mark II/10.canon.sraw2.cr2/threads:8/real_time_mean -0.0770 -0.0767 144 133 144 133
Canon/EOS 5D Mark II/10.canon.sraw2.cr2/threads:8/real_time_median -0.0767 -0.0763 144 133 144 133
Canon/EOS 5D Mark II/10.canon.sraw2.cr2/threads:8/real_time_stddev -0.4170 -0.4156 1 0 1 0
Canon/EOS 5DS/2K4A9927.CR2/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 25 vs 25
Canon/EOS 5DS/2K4A9927.CR2/threads:8/real_time_mean -0.0271 -0.0270 463 450 463 450
Canon/EOS 5DS/2K4A9927.CR2/threads:8/real_time_median -0.0093 -0.0093 453 449 453 449
Canon/EOS 5DS/2K4A9927.CR2/threads:8/real_time_stddev -0.7280 -0.7280 13 4 13 4
Canon/EOS 5DS/2K4A9928.CR2/threads:8/real_time_pvalue 0.0004 0.0004 U Test, Repetitions: 25 vs 25
Canon/EOS 5DS/2K4A9928.CR2/threads:8/real_time_mean -0.0065 -0.0065 569 565 569 565
Canon/EOS 5DS/2K4A9928.CR2/threads:8/real_time_median -0.0077 -0.0077 569 564 569 564
Canon/EOS 5DS/2K4A9928.CR2/threads:8/real_time_stddev +1.0077 +1.0068 2 5 2 5
Canon/EOS 5DS/2K4A9929.CR2/threads:8/real_time_pvalue 0.0220 0.0199 U Test, Repetitions: 25 vs 25
Canon/EOS 5DS/2K4A9929.CR2/threads:8/real_time_mean +0.0006 +0.0007 312 312 312 312
Canon/EOS 5DS/2K4A9929.CR2/threads:8/real_time_median +0.0031 +0.0032 311 312 311 312
Canon/EOS 5DS/2K4A9929.CR2/threads:8/real_time_stddev -0.7069 -0.7072 4 1 4 1
Canon/EOS 10D/CRW_7673.CRW/threads:8/real_time_pvalue 0.0004 0.0004 U Test, Repetitions: 25 vs 25
Canon/EOS 10D/CRW_7673.CRW/threads:8/real_time_mean -0.0015 -0.0015 141 141 141 141
Canon/EOS 10D/CRW_7673.CRW/threads:8/real_time_median -0.0010 -0.0011 141 141 141 141
Canon/EOS 10D/CRW_7673.CRW/threads:8/real_time_stddev -0.1486 -0.1456 0 0 0 0
Canon/EOS 40D/_MG_0154.CR2/threads:8/real_time_pvalue 0.6139 0.8766 U Test, Repetitions: 25 vs 25
Canon/EOS 40D/_MG_0154.CR2/threads:8/real_time_mean -0.0008 -0.0005 60 60 60 60
Canon/EOS 40D/_MG_0154.CR2/threads:8/real_time_median -0.0006 -0.0002 60 60 60 60
Canon/EOS 40D/_MG_0154.CR2/threads:8/real_time_stddev -0.1467 -0.1390 0 0 0 0
Canon/EOS 77D/IMG_4049.CR2/threads:8/real_time_pvalue 0.0137 0.0137 U Test, Repetitions: 25 vs 25
Canon/EOS 77D/IMG_4049.CR2/threads:8/real_time_mean +0.0002 +0.0002 275 275 275 275
Canon/EOS 77D/IMG_4049.CR2/threads:8/real_time_median -0.0015 -0.0014 275 275 275 275
Canon/EOS 77D/IMG_4049.CR2/threads:8/real_time_stddev +3.3687 +3.3587 0 2 0 2
Canon/PowerShot G1/crw_1693.crw/threads:8/real_time_pvalue 0.4041 0.3933 U Test, Repetitions: 25 vs 25
Canon/PowerShot G1/crw_1693.crw/threads:8/real_time_mean +0.0004 +0.0004 67 67 67 67
Canon/PowerShot G1/crw_1693.crw/threads:8/real_time_median -0.0000 -0.0000 67 67 67 67
Canon/PowerShot G1/crw_1693.crw/threads:8/real_time_stddev +0.1947 +0.1995 0 0 0 0
Fujifilm/GFX 50S/20170525_0037TEST.RAF/threads:8/real_time_pvalue 0.0074 0.0001 U Test, Repetitions: 25 vs 25
Fujifilm/GFX 50S/20170525_0037TEST.RAF/threads:8/real_time_mean -0.0092 +0.0074 547 542 25 25
Fujifilm/GFX 50S/20170525_0037TEST.RAF/threads:8/real_time_median -0.0054 +0.0115 544 541 25 25
Fujifilm/GFX 50S/20170525_0037TEST.RAF/threads:8/real_time_stddev -0.4086 -0.3486 8 5 0 0
Fujifilm/X-Pro2/_DSF3051.RAF/threads:8/real_time_pvalue 0.3320 0.0000 U Test, Repetitions: 25 vs 25
Fujifilm/X-Pro2/_DSF3051.RAF/threads:8/real_time_mean +0.0015 +0.0204 218 218 12 12
Fujifilm/X-Pro2/_DSF3051.RAF/threads:8/real_time_median +0.0001 +0.0203 218 218 12 12
Fujifilm/X-Pro2/_DSF3051.RAF/threads:8/real_time_stddev +0.2259 +0.2023 1 1 0 0
GoPro/HERO6 Black/GOPR9172.GPR/threads:8/real_time_pvalue 0.0000 0.0001 U Test, Repetitions: 25 vs 25
GoPro/HERO6 Black/GOPR9172.GPR/threads:8/real_time_mean -0.0209 -0.0179 96 94 90 88
GoPro/HERO6 Black/GOPR9172.GPR/threads:8/real_time_median -0.0182 -0.0155 95 93 90 88
GoPro/HERO6 Black/GOPR9172.GPR/threads:8/real_time_stddev -0.6164 -0.2703 2 1 2 1
Kodak/DCS Pro 14nx/
D7465857.DCR/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 25 vs 25
Kodak/DCS Pro 14nx/
D7465857.DCR/threads:8/real_time_mean -0.0098 -0.0098 176 175 176 175
Kodak/DCS Pro 14nx/
D7465857.DCR/threads:8/real_time_median -0.0126 -0.0126 176 174 176 174
Kodak/DCS Pro 14nx/
D7465857.DCR/threads:8/real_time_stddev +6.9789 +6.9157 0 2 0 2
Nikon/D850/Nikon-D850-14bit-lossless-compressed.NEF/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 25 vs 25
Nikon/D850/Nikon-D850-14bit-lossless-compressed.NEF/threads:8/real_time_mean -0.0237 -0.0238 474 463 474 463
Nikon/D850/Nikon-D850-14bit-lossless-compressed.NEF/threads:8/real_time_median -0.0267 -0.0267 473 461 473 461
Nikon/D850/Nikon-D850-14bit-lossless-compressed.NEF/threads:8/real_time_stddev +0.7179 +0.7178 3 5 3 5
Olympus/E-M1MarkII/Olympus_EM1mk2__HIRES_50MP.ORF/threads:8/real_time_pvalue 0.6837 0.6554 U Test, Repetitions: 25 vs 25
Olympus/E-M1MarkII/Olympus_EM1mk2__HIRES_50MP.ORF/threads:8/real_time_mean -0.0014 -0.0013 1375 1373 1375 1373
Olympus/E-M1MarkII/Olympus_EM1mk2__HIRES_50MP.ORF/threads:8/real_time_median +0.0018 +0.0019 1371 1374 1371 1374
Olympus/E-M1MarkII/Olympus_EM1mk2__HIRES_50MP.ORF/threads:8/real_time_stddev -0.7457 -0.7382 11 3 10 3
Panasonic/DC-G9/P1000476.RW2/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 25 vs 25
Panasonic/DC-G9/P1000476.RW2/threads:8/real_time_mean -0.0080 -0.0289 22 22 10 10
Panasonic/DC-G9/P1000476.RW2/threads:8/real_time_median -0.0070 -0.0287 22 22 10 10
Panasonic/DC-G9/P1000476.RW2/threads:8/real_time_stddev +1.0977 +0.6614 0 0 0 0
Panasonic/DC-GH5/_T012014.RW2/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 25 vs 25
Panasonic/DC-GH5/_T012014.RW2/threads:8/real_time_mean +0.0132 +0.0967 35 36 10 11
Panasonic/DC-GH5/_T012014.RW2/threads:8/real_time_median +0.0132 +0.0956 35 36 10 11
Panasonic/DC-GH5/_T012014.RW2/threads:8/real_time_stddev -0.0407 -0.1695 0 0 0 0
Panasonic/DC-GH5S/P1022085.RW2/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 25 vs 25
Panasonic/DC-GH5S/P1022085.RW2/threads:8/real_time_mean +0.0331 +0.1307 13 13 6 6
Panasonic/DC-GH5S/P1022085.RW2/threads:8/real_time_median +0.0430 +0.1373 12 13 6 6
Panasonic/DC-GH5S/P1022085.RW2/threads:8/real_time_stddev -0.9006 -0.8847 1 0 0 0
Pentax/645Z/IMGP2837.PEF/threads:8/real_time_pvalue 0.0016 0.0010 U Test, Repetitions: 25 vs 25
Pentax/645Z/IMGP2837.PEF/threads:8/real_time_mean -0.0023 -0.0024 395 394 395 394
Pentax/645Z/IMGP2837.PEF/threads:8/real_time_median -0.0029 -0.0030 395 394 395 393
Pentax/645Z/IMGP2837.PEF/threads:8/real_time_stddev -0.0275 -0.0375 1 1 1 1
Phase One/P65/
CF027310.IIQ/threads:8/real_time_pvalue 0.0232 0.0000 U Test, Repetitions: 25 vs 25
Phase One/P65/
CF027310.IIQ/threads:8/real_time_mean -0.0047 +0.0039 114 113 28 28
Phase One/P65/
CF027310.IIQ/threads:8/real_time_median -0.0050 +0.0037 114 113 28 28
Phase One/P65/
CF027310.IIQ/threads:8/real_time_stddev -0.0599 -0.2683 1 1 0 0
Samsung/NX1/2016-07-23-142101_sam_9364.srw/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 25 vs 25
Samsung/NX1/2016-07-23-142101_sam_9364.srw/threads:8/real_time_mean +0.0206 +0.0207 405 414 405 414
Samsung/NX1/2016-07-23-142101_sam_9364.srw/threads:8/real_time_median +0.0204 +0.0205 405 414 405 414
Samsung/NX1/2016-07-23-142101_sam_9364.srw/threads:8/real_time_stddev +0.2155 +0.2212 1 1 1 1
Samsung/NX30/2015-03-07-163604_sam_7204.srw/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 25 vs 25
Samsung/NX30/2015-03-07-163604_sam_7204.srw/threads:8/real_time_mean -0.0109 -0.0108 147 145 147 145
Samsung/NX30/2015-03-07-163604_sam_7204.srw/threads:8/real_time_median -0.0104 -0.0103 147 145 147 145
Samsung/NX30/2015-03-07-163604_sam_7204.srw/threads:8/real_time_stddev -0.4919 -0.4800 0 0 0 0
Samsung/NX3000/_3184416.SRW/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 25 vs 25
Samsung/NX3000/_3184416.SRW/threads:8/real_time_mean -0.0149 -0.0147 220 217 220 217
Samsung/NX3000/_3184416.SRW/threads:8/real_time_median -0.0173 -0.0169 221 217 220 217
Samsung/NX3000/_3184416.SRW/threads:8/real_time_stddev +1.0337 +1.0341 1 3 1 3
Sony/DSLR-A350/DSC05472.ARW/threads:8/real_time_pvalue 0.0001 0.0001 U Test, Repetitions: 25 vs 25
Sony/DSLR-A350/DSC05472.ARW/threads:8/real_time_mean -0.0019 -0.0019 194 193 194 193
Sony/DSLR-A350/DSC05472.ARW/threads:8/real_time_median -0.0021 -0.0021 194 193 194 193
Sony/DSLR-A350/DSC05472.ARW/threads:8/real_time_stddev -0.4441 -0.4282 0 0 0 0
Sony/ILCE-7RM2/14-bit-compressed.ARW/threads:8/real_time_pvalue 0.0000 0.4263 U Test, Repetitions: 25 vs 25
Sony/ILCE-7RM2/14-bit-compressed.ARW/threads:8/real_time_mean +0.0258 -0.0006 81 83 19 19
Sony/ILCE-7RM2/14-bit-compressed.ARW/threads:8/real_time_median +0.0235 -0.0011 81 82 19 19
Sony/ILCE-7RM2/14-bit-compressed.ARW/threads:8/real_time_stddev +0.1634 +0.1070 1 1 0 0
```
{
F7443905}
If we look at the `_mean`s, the time column, the biggest win is `-7.7%` (`Canon/EOS 5D Mark II/10.canon.sraw2.cr2`),
and the biggest loose is `+3.3%` (`Panasonic/DC-GH5S/P1022085.RW2`);
Overall: mean `-0.7436%`, median `-0.23%`, `cbrt(sum(time^3))` = `-8.73%`
Looks good so far i'd say.
llvm-exegesis details:
{
F7371117} {
F7371125}
{
F7371128} {
F7371144} {
F7371158}
Reviewers: craig.topper, RKSimon, andreadb, courbet, avt77, spatel, GGanesh
Reviewed By: andreadb
Subscribers: javed.absar, gbedwell, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D52779
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345463
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Sat, 27 Oct 2018 20:36:11 +0000 (20:36 +0000)]
[NFC][X86] Baseline tests for AMD BdVer2 (Piledriver) Scheduler model
Adding the baseline tests in a preparatory NFC commit,
so that the actual commit shows the *diff*.
Yes, i'm aware that a few of these codegen-based sched tests
are testing wrong instructions, i will fix that afterwards.
For https://reviews.llvm.org/D52779
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345462
91177308-0d34-0410-b5e6-
96231b3b80d8
George Burgess IV [Sat, 27 Oct 2018 20:02:06 +0000 (20:02 +0000)]
[utils] Run tests in the proper directory.
The intent here was to run check-llvm/check-clang in the instrumented
clang's build directory, not the maybe-not-yet-created uninstrumented
clang's. Oops. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345461
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 27 Oct 2018 18:37:59 +0000 (18:37 +0000)]
[X86][SSE] LowerVSELECT - pull out repeated getOperand(). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345458
91177308-0d34-0410-b5e6-
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Vlad Tsyrklevich [Sat, 27 Oct 2018 17:39:13 +0000 (17:39 +0000)]
Revert "DebugInfo: reduce DIE range verification on object files"
This reverts commits r345441 and r345444, they were causing msan
buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345457
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Sat, 27 Oct 2018 16:53:45 +0000 (16:53 +0000)]
[Local] Keep K's range if K does not move when combining metadata.
As K has to dominate I, IIUC I's range metadata must be a subset of
K's. After Eli's recent clarification to the LangRef, loading a value
outside of the range is undefined behavior.
Therefore if I's range contains elements outside of K's range and we would load
one such value, K would cause undefined behavior.
In cases like hoisting/sinking, we still want the most generic range
over all code paths to/from the hoist/sink point. As suggested in the
patches related to D47339, I will refactor the handling of those
scenarios and try to decouple it from this function as follow up, once
we switched to a similar handling of metadata in most of
combineMetadata.
I updated some tests checking mostly the merging of metadata to keep the
metadata of to dominating load. The most interesting one is probably test8 in
test/Transforms/JumpThreading/thread-loads.ll. It contained a comment
about the alias metadata preventing us to eliminate the branch, but it
seem like the actual problem currently is that we merge the ranges of
both loads and cannot eliminate the icmp afterwards. With this patch, we
manage to eliminate the icmp, as the range of the first load excludes 8.
Reviewers: efriedma, nlopes, davide
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D51629
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345456
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sat, 27 Oct 2018 16:46:10 +0000 (16:46 +0000)]
[x86] make test immune to improved extraction in D53784; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345455
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 27 Oct 2018 15:14:42 +0000 (15:14 +0000)]
Fix -Wdocumentation warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345454
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 27 Oct 2018 15:00:38 +0000 (15:00 +0000)]
Regenerate FP_TO_INT tests.
Precursor to fix for PR17686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345453
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 27 Oct 2018 12:15:58 +0000 (12:15 +0000)]
[TargetLowering] Move LegalizeDAG FP_TO_UINT handling to TargetLowering::expandFP_TO_UINT. NFCI.
First step towards fixing PR17686 and adding vector support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345452
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 27 Oct 2018 07:10:48 +0000 (07:10 +0000)]
Revert rL345395: [X86][SSE] Move 2-input limit up from getFauxShuffleMask to resolveTargetShuffleInputs
Makes no difference to actual shuffle decoding yet, but merges all the existing limits in one place for when proper support is fixed.
........
Its been reported that this is causing out of trunk failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345451
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjin Sijaric [Sat, 27 Oct 2018 06:13:06 +0000 (06:13 +0000)]
[ARM64][Windows] MCLayer support for exception handling
Add ARM64 unwind codes to MCLayer, as well SEH directives that will be emitted
by the frame lowering patch to follow. We only emit unwind codes into object
object files for now.
Differential Revision: https://reviews.llvm.org/D50166
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345450
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 27 Oct 2018 05:35:20 +0000 (05:35 +0000)]
[X86] Add some isel patterns for scalar_to_vector/extract_vector_element that use the avx512 extended register classes when they are available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345448
91177308-0d34-0410-b5e6-
96231b3b80d8
Alina Sbirlea [Sat, 27 Oct 2018 04:51:12 +0000 (04:51 +0000)]
Revert r345169 [along with its llvm counterpart r345170] as it makes Halide builds timeout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345447
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Saleem Abdulrasool [Sat, 27 Oct 2018 02:27:38 +0000 (02:27 +0000)]
test: add missing -triple
Ensure that the test builds for x86_64 as it is an assembly test. This
should repair the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345444
91177308-0d34-0410-b5e6-
96231b3b80d8
Brendon Cahoon [Sat, 27 Oct 2018 00:50:29 +0000 (00:50 +0000)]
[Hexagon] Add missing assignment to Itinerary in Call_nr
The class definition for Call_nr has the itinerary as a
parameter, but the value is never assigned to the Itinerary
field for the instruction. This means the compiler is unable
to schedule and packetize the instruction correctly because
these instrution will not have any resource descritions.
I don't have a specific test case, but the ps_call_nr.ll
test failed with a proposed patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345442
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Sat, 27 Oct 2018 00:49:33 +0000 (00:49 +0000)]
DebugInfo: reduce DIE range verification on object files
Relocatable content may have overlapping ranges until the sections are
finalized. This reduces the amount of verification that is done on an object
file so that invalid errors are not raised.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345441
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Fri, 26 Oct 2018 23:50:23 +0000 (23:50 +0000)]
Further split cpus test
On GreenDragon, CodeGen/X86/cpus-no-x86_64.ll was still timing out even
after breaking up the original test. I further split off the intel and
AMD cpus which hopefully resolves this.
http://green.lab.llvm.org/green/job/clang-stage2-cmake-RgSan/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345438
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 26 Oct 2018 23:06:28 +0000 (23:06 +0000)]
[x86] adjust tests to preserve behavior; NFC
I'm planning a binop optimization that would subvert the
domain forcing ops in these tests, so turning them into
zexts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345437
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Ryan Prichard [Fri, 26 Oct 2018 23:01:54 +0000 (23:01 +0000)]
[llvm-readobj] Fix bugs with unrecognized types in switch statements
Summary:
Add missing breaks. Several functions used nested switch statements,
where the outer switch branches based on the architecture, and the inner
switch handles architecture-specific types. If the type isn't
architecture-specific, break out to the generic types rather than fall
through.
getElfPtType: For GNU-style output, llvm-readobj prints
"<unknown>: 0xnnnnnnnn" for an unrecognized segment type, unless the
architecture is EM_ARM, EM_MIPS, or EM_MIPS_RS3_LE, in which case it
prints "". This behavior appears accidental, so instead, always print
the "<unknown>: 0xnnnnnnnn" string.
Reviewers: pcc, grimar
Reviewed By: grimar
Subscribers: sdardis, javed.absar, arichardson, kristof.beyls, atanasyan, llvm-commits
Differential Revision: https://reviews.llvm.org/D53730
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345436
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Leonard Chan [Fri, 26 Oct 2018 22:51:51 +0000 (22:51 +0000)]
Revert "[PassManager/Sanitizer] Enable usage of ported AddressSanitizer passes with -fsanitize=address"
This reverts commit
8d6af840396f2da2e4ed6aab669214ae25443204 and commit
b78d19c287b6e4a9abc9fb0545de9a3106d38d3d which causes slower build times
by initializing the AddressSanitizer on every function run.
The corresponding revisions are https://reviews.llvm.org/D52814 and
https://reviews.llvm.org/D52739.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345433
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Volodymyr Sapsai [Fri, 26 Oct 2018 22:14:33 +0000 (22:14 +0000)]
[VFS] Add property 'fallthrough' that controls fallback to real file system.
Default property value 'true' preserves current behavior. Value 'false' can be
used to create VFS "root", file system that gives better control over which
files compiler can use during compilation as there are no unpredictable
accesses to real file system.
Non-fallthrough use case changes how we treat multiple VFS overlay
files. Instead of all of them being at the same level just above a real
file system, now they are nested and subsequent overlays can refer to
files in previous overlays.
rdar://problem/
39465552
Reviewers: bruno, benlangmuir
Reviewed By: bruno
Subscribers: dexonsmith, cfe-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D50539
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345431
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Sanjay Patel [Fri, 26 Oct 2018 21:32:04 +0000 (21:32 +0000)]
[DAGCombiner] rearrange code in narrowExtractedVectorBinOp(); NFC
We can extend this code to handle many more cases
if an extract is cheap, so prepping for that change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345430
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Sanjay Patel [Fri, 26 Oct 2018 21:05:14 +0000 (21:05 +0000)]
[ValueTracking] peek through shuffles in ComputeNumSignBits (PR37549)
The motivating case is from PR37549:
https://bugs.llvm.org/show_bug.cgi?id=37549
The analysis improvement allows us to form a vector 'select' out of
bitwise logic (the use of ComputeNumSignBits was added at rL345149).
The smaller test shows another InstCombine improvement - we use
ComputeNumSignBits to add 'nsw' to shift-left. But the negative
test shows an example where we must not add 'nsw' - when the shuffle
mask contains undef elements.
Differential Revision: https://reviews.llvm.org/D53659
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345429
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Craig Topper [Fri, 26 Oct 2018 20:59:55 +0000 (20:59 +0000)]
[LegalizeTypes] Stop DAGTypeLegalizer::getSETCCWidenedResultTy from creating illegal setccs. Add checks for valid setccs
The DAGTypeLegalizer::getSETCCWidenedResultTy was widening the MaskVT, but the code in convertMask called after getSETCCWidenedResultTy had no idea this widening had occurred. So none of the operands were widened when convertMask created new setccs with the widened VT.
This patch removes the widening and adds some asserts to getNode to validate the types of setccs to prevent issues like this in the future.
Differential Revision: https://reviews.llvm.org/D53743
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345428
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George Burgess IV [Fri, 26 Oct 2018 20:56:03 +0000 (20:56 +0000)]
Add docs+a script for building clang/LLVM with PGO
Depending on who you ask, PGO grants a 15%-25% improvement in build
times when using clang. Sadly, hooking everything up properly to
generate a profile and apply it to clang isn't always straightforward.
This script (and the accompanying docs) aim to make this process easier;
ideally, a single invocation of the given script.
In terms of testing, I've got a cronjob on my Debian box that's meant to
run this a few times per week, and I tried manually running it on a puny
Gentoo box I have (four whole Atom cores!). Nothing obviously broke.
¯\_(ツ)_/¯
I don't know if we have a Python style guide, so I just shoved this
through yapf with all the defaults on.
Finally, though the focus is clang at the moment, the hope is that this
is easily applicable to other LLVM-y tools with minimal effort (e.g.
lld, opt, ...). Hence, this lives in llvm/utils and tries to be somewhat
ambiguous about naming.
Differential Revision: https://reviews.llvm.org/D53598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345427
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Reid Kleckner [Fri, 26 Oct 2018 20:26:36 +0000 (20:26 +0000)]
[Spectre] Fix MIR verifier errors in retpoline thunks
Summary:
The main challenge here is that X86InstrInfo::AnalyzeBranch doesn't
understand the way we're using a CALL instruction as a branch, so we
can't list the CallTarget MBB as a successor of the entry block. If we
don't list it as a successor, then the AsmPrinter doesn't print a label
for the MBB.
Fix the issue by inserting our own label at the beginning of the call
target block. We can rely on the AsmPrinter to always emit it, even
though the block appears to be unreachable, but address-taken.
Fixes PR38391.
Reviewers: thegameg, chandlerc, echristo
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D53653
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345426
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Eli Friedman [Fri, 26 Oct 2018 19:32:24 +0000 (19:32 +0000)]
[ARM] Make InstrEmitter mark CPSR defs dead for Thumb1.
The "dead" markings allow existing target-independent optimizations,
like MachineSink, to trigger more frequently. The CPSR defs would have
eventually been marked dead by LiveVariables, so this only affects
optimizations before regalloc.
The ARMBaseInstrInfo.cpp change is fixing a bug which is only visible
with this change: the transform adds a use to an otherwise dead def
of CPSR. This is covered by existing regression tests.
thumb2-tbh.ll breaks for Thumb1 due to MachineLICM changing the
generated code; I'll fix it in D53452.
Differential Revision: https://reviews.llvm.org/D53453
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345420
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Yi Kong [Fri, 26 Oct 2018 18:25:27 +0000 (18:25 +0000)]
[XRay] Use std::errc::invalid_argument instead of std::errc::bad_message
This change should appease the mingw32 builds.
Similar to r293725.
Differential Revision: https://reviews.llvm.org/D53742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345416
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Lei Huang [Fri, 26 Oct 2018 18:09:36 +0000 (18:09 +0000)]
[PowerPC] Improve BUILD_VECTOR of 4 i32s
Currently, for this node:
vector int test(int a, int b, int c, int d) {
return (vector int) { a, b, c, d };
}
we get this on Power9:
mtvsrdd 34, 5, 3
mtvsrdd 35, 6, 4
vmrgow 2, 3, 2
and this on Power8:
mtvsrwz 0, 3
mtvsrwz 1, 5
mtvsrwz 2, 4
mtvsrwz 3, 6
xxmrghd 34, 1, 0
xxmrghd 35, 3, 2
vmrgow 2, 3, 2
This can be improved to this on LE Power9:
rldimi 3, 4, 32, 0
rldimi 5, 6, 32, 0
mtvsrdd 34, 5, 3
and this on LE Power8
rldimi 3, 4, 32, 0
rldimi 5, 6, 32, 0
mtvsrd 34, 3
mtvsrd 35, 5
xxpermdi 34, 35, 34, 0
This patch updates the TD pattern to generate the optimized sequence for both
Power8 and Power9 on LE and BE.
Differential Revision: https://reviews.llvm.org/D53494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345414
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Christy Lee [Fri, 26 Oct 2018 18:02:06 +0000 (18:02 +0000)]
Pointer types were treated as zero-size by MergeICmps
Summary:
The visitICmp analysis function would record compares of pointer types, as size 0. This causes the resulting memcmp() call to have the wrong total size.
Found with "self-build" of clang/LLVM on Windows.
Reviewers: christylee, trentxintong, courbet
Reviewed By: courbet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345413
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Lang Hames [Fri, 26 Oct 2018 17:48:50 +0000 (17:48 +0000)]
[ADT] Use explicit constructors for DenseMapPair to work around compiler issues.
Inheriting constructors from std::pair caused clang-3.8 to treat some DenseMap
initializer_list constructor calls as ambiguous, which broke several bots. This
commit explicitly defines DenseMapPair's constructos to work around the issue.
https://reviews.llvm.org/D53726
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345411
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Fangrui Song [Fri, 26 Oct 2018 17:38:27 +0000 (17:38 +0000)]
[llvm-ar] Strip trailing \r and format
Reviewers: mstorsjo, rupprecht, gbreynoo
Reviewed By: rupprecht
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345410
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Craig Topper [Fri, 26 Oct 2018 17:21:26 +0000 (17:21 +0000)]
[X86] Stop promoting vector and/or/xor/andn to vXi64.
These promotions add additional bitcasts to the SelectionDAG that can pessimize computeKnownBits/computeNumSignBits. It also seems to interfere with broadcast formation.
This patch removes the promotion and adds isel patterns instead.
The increased table size is more than I would like, but hopefully we can find some canonicalizations or other tricks to start pruning out patterns going forward.
Differential Revision: https://reviews.llvm.org/D53268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345408
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Craig Topper [Fri, 26 Oct 2018 17:21:19 +0000 (17:21 +0000)]
[X86] Add -LABEL to some FileCheck checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345407
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Fangrui Song [Fri, 26 Oct 2018 17:15:52 +0000 (17:15 +0000)]
[llvm-ar] Add a dependency to BinaryFormat after rL345383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345405
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Wolfgang Pieb [Fri, 26 Oct 2018 17:14:46 +0000 (17:14 +0000)]
[DWARF][NFC] cleanup (mostly leftovers from the implementation of string offsets tables)
Majority of the patch by David Blaikie.
Differential Revision: https://reviews.llvm.org/D53741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345404
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Andrea Di Biagio [Fri, 26 Oct 2018 16:22:26 +0000 (16:22 +0000)]
[tblgen] Improve comments in TargetInstrPredicate.td. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345399
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Vlad Tsyrklevich [Fri, 26 Oct 2018 16:07:50 +0000 (16:07 +0000)]
Revert "UBSan blacklist workaround for bot timeouts"
This reverts commit r335525. This workaround is no longer necessary
because PR37929 has been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345397
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Francis Visoiu Mistrih [Fri, 26 Oct 2018 16:00:29 +0000 (16:00 +0000)]
[MIR] Simplify and move MIR test
Also fixes a Machine Verifier issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345396
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Simon Pilgrim [Fri, 26 Oct 2018 15:19:02 +0000 (15:19 +0000)]
[X86][SSE] Move 2-input limit up from getFauxShuffleMask to resolveTargetShuffleInputs
Makes no difference to actual shuffle decoding yet, but merges all the existing limits in one place for when proper support is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345395
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Sanjay Patel [Fri, 26 Oct 2018 14:58:13 +0000 (14:58 +0000)]
[x86] commute blendvb with constant condition op to allow load folding
This is a narrow fix for 1 of the problems mentioned in PR27780:
https://bugs.llvm.org/show_bug.cgi?id=27780
I looked at more general solutions, but it's a mess. We canonicalize shuffle masks
based on the number of elements accessed from each operand, and that's not optional.
If you remove that, we'll crash because we fail to match isel patterns. So I'm
waiting until we're sure that we have blendvb with constant condition and then
commuting based on the load potential. Other cases like blend-with-immediate are
already handled elsewhere, so this is probably not a common problem anyway.
I didn't use "MayFoldLoad" because that checks for one-use and in these cases, we've
screwed that up by creating a temporary PSHUFB using these operands that we're counting
on to be killed later. Undoing that didn't look like a simple task because it's
intertwined with determining if we actually use both operands of the shuffle or not.a
Differential Revision: https://reviews.llvm.org/D53737
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345390
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Simon Pilgrim [Fri, 26 Oct 2018 14:39:28 +0000 (14:39 +0000)]
[X86] Use existing pulled out VT variables. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345388
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Max Kazantsev [Fri, 26 Oct 2018 14:20:11 +0000 (14:20 +0000)]
[SimpleLoopUnswitch] Unswitch by experimental.guard intrinsics
This patch adds support of `llvm.experimental.guard` intrinsics to non-trivial
simple loop unswitching. These intrinsics represent implicit control flow which
has pretty much the same semantics as usual conditional branches. The
algorithm of dealing with them is following:
- Consider guards as unswitching candidates;
- If a guard is considered the best candidate, turn it into a branch;
- Apply normal unswitching algorithm on this branch.
The patch has no compile time effect on code that does not contain any guards.
Differential Revision: https://reviews.llvm.org/D53744
Reviewed By: chandlerc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345387
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Sjoerd Meijer [Fri, 26 Oct 2018 14:19:57 +0000 (14:19 +0000)]
[ARM] Fix ARMCodeGenPrepare test cases
While working on FileCheck producing better diagnostics in D53710, I noticed
that our test case is broken in a few different ways. The test was running, but
results were not checked as prefix CHECK-COMMON wasn't defined (which is what
FileCheck should warn about). Also, the output was different in 2 cases because
of recent changes in ARMCodeGenPrepare.
Differential Revision: https://reviews.llvm.org/D53746
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345386
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Francis Visoiu Mistrih [Fri, 26 Oct 2018 13:37:25 +0000 (13:37 +0000)]
[CodeGen] Remove out operands from PATCHABLE_OP
The current model requires 1 out operand, but it is not used nor created.
This fixed an x86 machine verifier issue.
Part of PR27481.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345384
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Owen Reynolds [Fri, 26 Oct 2018 13:34:38 +0000 (13:34 +0000)]
[llvm-ar] Access ADDLIB in llvm-ar via command line
ADDLIB is called to add the contents of an archive to another archive.
Previously this was only accessible through the use of an MRI script.
With the use of a new "L" modifier, archive files can treated in the
manner above when using quick append.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345383
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Scott Linder [Fri, 26 Oct 2018 13:18:36 +0000 (13:18 +0000)]
[AMDGPU] Add a pass to promote bitcast calls
AMDGPU currently only supports direct calls, but at lower optimisation levels it
fails to lower statically direct calls which appear indirect due to a bitcast.
Add a pass to visit all CallSites and use CallPromotionUtils to "devirtualize"
calls.
Differential Revision: https://reviews.llvm.org/D52741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345382
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Simon Pilgrim [Fri, 26 Oct 2018 12:33:56 +0000 (12:33 +0000)]
Regenerate test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345379
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Sam McCall [Fri, 26 Oct 2018 12:19:48 +0000 (12:19 +0000)]
[llvm-mca] Fix -wreorder and -Wunused-private-field after r345376. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345378
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George Rimar [Fri, 26 Oct 2018 11:25:12 +0000 (11:25 +0000)]
[Codegen] - Implement basic .debug_loclists section emission (DWARF5).
.debug_loclists is the DWARF 5 version of the .debug_loc.
With that patch, it will be emitted when DWARF 5 is used.
Differential revision: https://reviews.llvm.org/D53365
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345377
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Andrea Di Biagio [Fri, 26 Oct 2018 10:48:04 +0000 (10:48 +0000)]
[llvm-mca] Removed dependency on mca::SourcMgr in some Views. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345376
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Max Kazantsev [Fri, 26 Oct 2018 09:52:58 +0000 (09:52 +0000)]
[SimpleLoopUnswitch] Make all checks before actual non-trivial unswitch
We should be able to make all relevant checks before we actually start the non-trivial
unswitching, so that we could guarantee that once we have started the transform,
it will always succeed.
Reviewed By: chandlerc
Differential Revision: https://reviews.llvm.org/D53747
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345375
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Fangrui Song [Fri, 26 Oct 2018 06:59:08 +0000 (06:59 +0000)]
[SystemZ] Fix -Wcovered-switch-default as coding standard regulates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345369
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Kristina Brooks [Fri, 26 Oct 2018 06:57:02 +0000 (06:57 +0000)]
[NFC] Add periods to CREDITS.txt (testing git-llvm)
NFC commit to test git-llvm bridge for current GitHub monorepo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345368
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Fangrui Song [Fri, 26 Oct 2018 06:56:51 +0000 (06:56 +0000)]
[llvm-nm] Simplify. NFC
Change a \t to spaces
Change some zero-filling memcpy to aggregate initialization
Delete redundant ArchiveName.clear() after declaration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345367
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Li Jia He [Fri, 26 Oct 2018 06:48:53 +0000 (06:48 +0000)]
[PowerPC] Fix some missed optimization opportunities in combineSetCC
For both operands are bool, short, int, long, long long, add the following optimization.
1. 0-x == y --> x+y ==0
2. 0-x != y --> x+y != 0
Review: nemanjai
Differential Revision: https://reviews.llvm.org/D53360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345366
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Li Jia He [Fri, 26 Oct 2018 05:02:10 +0000 (05:02 +0000)]
[PowerPC][NFC] Add tests for some missed optimization opportunities in combineSetCC
For both operands are bool, short, int, long, long long, add the following optimization test case.
1. 0-x == y --> x+y ==0
2. 0-x != y --> x+y != 0
Review: nemanjai
Differential Revision: https://reviews.llvm.org/D53358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345365
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Li Jia He [Fri, 26 Oct 2018 04:54:56 +0000 (04:54 +0000)]
This reverts commit r345357, It is wrong to create a new directory and put the test file into it. I am sorry for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345364
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Nemanja Ivanovic [Fri, 26 Oct 2018 03:30:28 +0000 (03:30 +0000)]
[NFC] Fix the regular expression for BE PPC in update_llc_test_checks.py
Currently, the regular expression that matches the lines of assembly for PPC LE
(ELFv2) does not work for the assembly for BE (ELFv1). This patch fixes it.
Differential revision: https://reviews.llvm.org/D53059
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345363
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Nemanja Ivanovic [Fri, 26 Oct 2018 03:19:13 +0000 (03:19 +0000)]
[PowerPC] Keep vector int to fp conversions in vector domain
At present a v2i16 -> v2f64 convert is implemented by extracts to scalar,
scalar converts, and merge back into a vector. Use vector converts instead,
with the int data permuted into the proper position and extended if necessary.
Patch by RolandF.
Differential revision: https://reviews.llvm.org/D53346
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345361
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Fangrui Song [Fri, 26 Oct 2018 03:15:56 +0000 (03:15 +0000)]
[Pipeliner] Mark swp-art-deps-rec.ll as REQUIRES: asserts after rL345319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345359
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Fangrui Song [Fri, 26 Oct 2018 03:04:54 +0000 (03:04 +0000)]
Add dependency from SystemZAsmParser to SystemZAsmPrinter after rL345349
This fixes -DBUILD_SHARED_LIBS=on build. The dependency is similar to that of X86's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345358
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Li Jia He [Fri, 26 Oct 2018 02:34:57 +0000 (02:34 +0000)]
[PowerPC][NFC] Add tests for some missed optimization opportunities in combineSetCC
For both operands are bool, short, int, long, long long, add the following optimization test case.
1. 0-x == y --> x+y ==0
2. 0-x != y --> x+y != 0
Review: nemanjai
Differential Revision: https://reviews.llvm.org/D53358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345357
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Vlad Tsyrklevich [Fri, 26 Oct 2018 02:00:14 +0000 (02:00 +0000)]
Revert "[AArch64] Create proper memoperand for multi-vector stores"
This reverts commit r345315, it was causing test failures on
sanitizer-x86_64-linux-fast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345356
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Li Jia He [Fri, 26 Oct 2018 01:58:23 +0000 (01:58 +0000)]
add myself to the CREDITS.TXT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345355
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Chijun Sima [Fri, 26 Oct 2018 01:28:36 +0000 (01:28 +0000)]
Teach the DominatorTree fallback to recalculation when applying updates to speedup JT (PR37929)
Summary:
This patch makes the dominatortree recalculate when applying updates with the size of the update vector larger than a threshold. Directly applying updates is usually slower than recalculating the whole domtree in this case. This patch fixes an issue which causes JT running slowly on some inputs.
In bug 37929, the dominator tree is trying to apply 19,000+ updates several times, which takes several minutes.
After this patch, the time used by DT.applyUpdates:
| Input | Before (s) | After (s) | Speedup |
| the 2nd Reproducer in 37929 | 297 | 0.15 | 1980x |
| clang-5.0.0.0.bc | 9.7 | 4.3 | 2.26x |
| clang-5.0.0.4.bc | 11.6 | 2.6 | 4.46x |
Reviewers: kuhar, brzycki, trentxintong, davide, dmgreen, grosser
Reviewed By: kuhar, brzycki
Subscribers: kristina, llvm-commits
Differential Revision: https://reviews.llvm.org/D53245
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345353
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Jonas Paulsson [Fri, 26 Oct 2018 00:36:00 +0000 (00:36 +0000)]
[SystemZ] Implement SystemZOperand::print()
SystemZAsmParser can now handle -debug by printing the operands neatly to the
output stream. Before this patch this lead to an llvm_unreachable().
It seems that now '-mllvm -debug' does not cause any crashes anywhere (at
least not on SPEC).
Review: Ulrich Weigand
https://reviews.llvm.org/D53328
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345349
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Zachary Turner [Fri, 26 Oct 2018 00:17:31 +0000 (00:17 +0000)]
Dump public symbol records in pdb2yaml mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345348
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Jonas Paulsson [Fri, 26 Oct 2018 00:02:33 +0000 (00:02 +0000)]
[SystemZ] Pass the DAG pointer from SystemZAddressingMode::dump().
In order to print the IR slot number for the memory operand, the DAG pointer
must be passed to SDNode::dump().
The isel-debug.ll test updated to also check for the IR Value reference being
printed correctly.
Review: Ulrich Weigand
https://reviews.llvm.org/D53333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345347
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Heejin Ahn [Thu, 25 Oct 2018 23:55:10 +0000 (23:55 +0000)]
Reland "[WebAssembly] LSDA info generation"
Summary:
This adds support for LSDA (exception table) generation for wasm EH.
Wasm EH mostly follows the structure of Itanium-style exception tables,
with one exception: a call site table entry in wasm EH corresponds to
not a call site but a landing pad.
In wasm EH, the VM is responsible for stack unwinding. After an
exception occurs and the stack is unwound, the control flow is
transferred to wasm 'catch' instruction by the VM, after which the
personality function is called from the compiler-generated code. (Refer
to WasmEHPrepare pass for more information on this part.)
This patch:
- Changes wasm.landingpad.index intrinsic to take a token argument, to
make this 1:1 match with a catchpad instruction
- Stores landingpad index info and catch type info MachineFunction in
before instruction selection
- Lowers wasm.lsda intrinsic to an MCSymbol pointing to the start of an
exception table
- Adds WasmException class with overridden methods for table generation
- Adds support for LSDA section in Wasm object writer
Reviewers: dschuff, sbc100, rnk
Subscribers: mgorny, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52748
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345345
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Heejin Ahn [Thu, 25 Oct 2018 23:45:48 +0000 (23:45 +0000)]
[WebAssembly] Support EH instructions in InstPrinter
Summary: This adds support for exception handling instructions to InstPrinter.
Reviewers: dschuff, aardappel
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345343
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Jonas Paulsson [Thu, 25 Oct 2018 23:39:07 +0000 (23:39 +0000)]
Fix in MachineOperand::printIRValueReference().
Handle the case where getCurrentFunction() returns nullptr by passing -1 to
printIRSlotNumber(). This will result in <badref> being printed instead of an
assertion failure.
Review: Francis Visoiu Mistrih
https://reviews.llvm.org/D53333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345342
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Bryan Chan [Thu, 25 Oct 2018 23:36:41 +0000 (23:36 +0000)]
[AArch64] Implement FP16FML intrinsics
Add LLVM intrinsics for the ARMv8.2-A FP16FML vector-form instructions. Add a
DAG pattern to define the indexed-form intrinsics in terms of the vector-form
ones, similarly to how the Dot Product intrinsics were implemented.
Based on a patch by Gao Yiling.
Differential Revision: https://reviews.llvm.org/D53632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345337
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Heejin Ahn [Thu, 25 Oct 2018 23:35:15 +0000 (23:35 +0000)]
Delete test case. Assertions can't be tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345336
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Heejin Ahn [Thu, 25 Oct 2018 23:35:15 +0000 (23:35 +0000)]
Tidy up test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345335
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Heejin Ahn [Thu, 25 Oct 2018 23:35:14 +0000 (23:35 +0000)]
Address comments
- Add llvm-mc test case (and delete the old one)
- Change report_fatal_error to assertions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345334
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Heejin Ahn [Thu, 25 Oct 2018 23:35:13 +0000 (23:35 +0000)]
[WebAssembly] Error out when block/loop markers mismatch
Summary:
Currently InstPrinter ignores if there are mismatches between block/loop
and end markers by skipping the case if ControlFlowStack is empty. I
guess it is better to explicitly error out in this case, because this
signals invalid input.
Reviewers: aardappel
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53620
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345333
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Jonas Paulsson [Thu, 25 Oct 2018 22:53:27 +0000 (22:53 +0000)]
[SystemZ] NFC reformatting in SystemZTargetTransformInfo.cpp
Some lines more than 80 characters long reformatted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345331
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Jonas Paulsson [Thu, 25 Oct 2018 22:28:25 +0000 (22:28 +0000)]
[SystemZ] Improve getMemoryOpCost() to find foldable loads that are converted.
The SystemZ backend can do arithmetic of memory by loading and then extending
one of the operands. Similarly, a load + truncate can be folded into an
operand.
This patch improves the SystemZ TTI cost function to recognize this.
Review: Ulrich Weigand
https://reviews.llvm.org/D52692
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345327
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David Blaikie [Thu, 25 Oct 2018 22:26:25 +0000 (22:26 +0000)]
DebugInfo: Explain why DW_LLE_(GNU_)startx_length is used
This isn't the most object-size efficient encoding, but it's the only
one GDB supports for the pre-standard fission format. I've written fixes
for this twice now... - so perhaps this comment will help me remember
why neither of these have been committed and why I shouldn't try to
write a third fix another year from now...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345326
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Sanjay Patel [Thu, 25 Oct 2018 22:23:27 +0000 (22:23 +0000)]
[x86] add tests for missed load folding; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345325
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Jonas Paulsson [Thu, 25 Oct 2018 21:47:22 +0000 (21:47 +0000)]
[SystemZ] Improve handling and cost estimates of vector integer div/rem
Enable the DAG optimization that converts vector div/rem with constants into
multiply+shifts sequences by expanding them early. This is needed since
ISD::SMUL_LOHI is 'Custom' lowered on SystemZ, and will therefore not be
available to BuildSDIV after legalization.
Better cost values for these instructions based on how they will be
implemented (a constant divisor is cheaper).
Review: Ulrich Weigand
https://reviews.llvm.org/D53196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345321
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David Blaikie [Thu, 25 Oct 2018 21:35:59 +0000 (21:35 +0000)]
llvm-dwarfdump: loclists: Don't expect an (albeit empty) expression for LLE_base_address
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345320
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Sumanth Gundapaneni [Thu, 25 Oct 2018 21:27:08 +0000 (21:27 +0000)]
[Pipeliner] Ignore Artificial dependences while computing recurrences.
The artificial dependencies are not real dependencies. In some cases, they
form circuits with bigger MII. However, they are used to schedule instructions
better.
Differential Revision: https://reviews.llvm.org/D53450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345319
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Sumanth Gundapaneni [Thu, 25 Oct 2018 21:25:30 +0000 (21:25 +0000)]
[Pipeliner] Remove the unneeded include header(NFC).
Differential Revision: https://reviews.llvm.org/D53451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345318
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Craig Topper [Thu, 25 Oct 2018 21:16:06 +0000 (21:16 +0000)]
[X86] Change X86 backend to look for 'min-legal-vector-width' attribute instead of 'required-vector-width' when determining whether 512-bit vectors should be legal.
The required-vector-width attribute was only used for backend testing and has never been generated by clang.
I believe clang is now generating min-legal-vector-width for vector uses in user code.
With this I believe passing -mprefer-vector-width=256 to clang should prevent use of zmm registers in the generated assembly unless the user used a 512-bit intrinsic in their source code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345317
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Francis Visoiu Mistrih [Thu, 25 Oct 2018 21:12:15 +0000 (21:12 +0000)]
[CodeGen] Remove operands from FENTRY_CALL
FENTRY_CALL is actually not taking any input / output operands. The
machine verifier complains now because the target description says that:
* It needs 1 unknown output
* It needs 1 or more variable inputs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345316
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David Greene [Thu, 25 Oct 2018 21:10:39 +0000 (21:10 +0000)]
[AArch64] Create proper memoperand for multi-vector stores
Include all of the store's source vector operands when creating the
MachineMemOperand. Previously, we were missing the first operand,
making the store size seem smaller than it really is.
Differential Revision: https://reviews.llvm.org/D52816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345315
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Volkan Keles [Thu, 25 Oct 2018 20:01:19 +0000 (20:01 +0000)]
[AArch64][GlobalISel] Simplify a legalizer test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345307
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Thomas Lively [Thu, 25 Oct 2018 19:06:13 +0000 (19:06 +0000)]
[WebAssembly] Use target-independent saturating add
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53721
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345299
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Craig Topper [Thu, 25 Oct 2018 18:23:48 +0000 (18:23 +0000)]
[X86] Add some non-AVX512VL command lines to the *vl-vec-test-testn.ll tests.
This will expose some regressions in the WIP and/or/xor promotion removal patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345297
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Cameron McInally [Thu, 25 Oct 2018 18:09:33 +0000 (18:09 +0000)]
[FPEnv] Last BinaryOperator::isFNeg(...) to m_FNeg(...) changes
Replacing BinaryOperator::isFNeg(...) to avoid regressions when we
separate FNeg from the FSub IR instruction.
Differential Revision: https://reviews.llvm.org/D53650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345295
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Craig Topper [Thu, 25 Oct 2018 18:06:25 +0000 (18:06 +0000)]
[X86] Add KNL command lines to movmsk-cmp.ll.
Some of this code looks pretty bad and we should probably still be using movmskb more with avx512f.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345293
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Volkan Keles [Thu, 25 Oct 2018 17:52:19 +0000 (17:52 +0000)]
[GlobalISel] LegalizerHelper: Fix the incorrect alignment when splitting loads/stores in narrowScalar
Reviewers: dsanders, bogner, jpaquette, aemerson, ab, paquette
Reviewed By: dsanders
Subscribers: rovka, kristof.beyls, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D53664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345292
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Simon Pilgrim [Thu, 25 Oct 2018 17:43:36 +0000 (17:43 +0000)]
[LegalizeDAG] Remove dead SINT_TO_FP legalization code
As noticed on D52965, the SINT_TO_FP i64 to f32 legalization code has been dead for years - protected by an assert.
Differential Revision: https://reviews.llvm.org/D53703
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345290
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Volkan Keles [Thu, 25 Oct 2018 17:37:07 +0000 (17:37 +0000)]
[GISel] LegalizerInfo: Rename MemDesc::Size to SizeInBits to make the value clearer
Requested in D53679.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345288
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Craig Topper [Thu, 25 Oct 2018 17:29:00 +0000 (17:29 +0000)]
[X86] Remove ProcIntelKNL and replace with a SlowPMADDWD flag to use in the one place it was checked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345286
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