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Ian Romanick [Sun, 18 Jun 2017 01:56:13 +0000 (18:56 -0700)]
r200: Enable NV_fog_distance
With the previous fixes in place, it appears to just work.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Sat, 17 Jun 2017 02:15:56 +0000 (19:15 -0700)]
i965: Enable NV_fog_distance
With the previous fixes in place, it appears to just work.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Sat, 17 Jun 2017 02:02:48 +0000 (19:02 -0700)]
ffvertex: Don't try to read output registers in fog calculation
Gallium drivers use _mesa_remove_output_reads() via st_program to lower
output reads away. It seems better to just generate the right thing in
the first place.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Sat, 17 Jun 2017 01:48:22 +0000 (18:48 -0700)]
mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)
Found by inspection, so I made a piglit test too.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Mon, 22 May 2017 22:21:00 +0000 (15:21 -0700)]
mesa: Silence an unused parameter warning
main/framebuffer.c: In function ‘update_color_draw_buffers’:
main/framebuffer.c:629:46: warning: unused parameter ‘ctx’ [-Wunused-parameter]
update_color_draw_buffers(struct gl_context *ctx, struct gl_framebuffer *fb)
^~~
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Gert Wollny [Fri, 27 Apr 2018 16:04:01 +0000 (18:04 +0200)]
mesa/main/readpix: Correct handling of packed floating point values
Make sure that clamping in the pixel transfer operations is enabled/disabled
for packed floating point values just like it is done for single normal and
half precision floating point values.
This fixes a series of CTS tests with virgl that use r11f_g11f_b10f
buffers as target, and where virglrenderer reads these surfaces back
using the format GL_UNSIGNED_INT_10F_11F_11F_REV.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Scott D Phillips [Wed, 2 May 2018 16:01:02 +0000 (09:01 -0700)]
util/set: add a set_clear function
Clear a set back to the state of having zero entries.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tapani Pälli [Fri, 4 May 2018 05:28:50 +0000 (08:28 +0300)]
egl: add EGL_BAD_MATCH error case for surfaceless and android
Just like is done for other backends when suitable config is not
found (added in
fd4eba4929).
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Nicolai Hähnle [Tue, 1 May 2018 09:06:18 +0000 (11:06 +0200)]
amd/common: use llvm.amdgcn.wqm for explicit derivatives
To comply with an upcoming change in LLVM, see
https://reviews.llvm.org/D46051
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Rhys Perry [Thu, 3 May 2018 17:02:14 +0000 (18:02 +0100)]
nv50/ir: fix printing of pixld
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Drew Davenport [Fri, 27 Apr 2018 15:34:58 +0000 (09:34 -0600)]
st/va: Support YUV formats in vaCreateSurfaces
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Mark Janes [Thu, 3 May 2018 21:28:22 +0000 (14:28 -0700)]
Revert "anv/device: expose shaderInt16 support in gen8+"
This reverts commit
0ba0ac815e078185c1f408ec7078fd1efac1a634.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106393
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Mark Janes [Thu, 3 May 2018 21:28:00 +0000 (14:28 -0700)]
Revert "i965/compiler: handle conversion to smaller type in the lowering pass for that"
This reverts commit
96b51537908cd2aace85f54b437eeb72e6346b7e.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106393
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Vinson Lee [Tue, 1 May 2018 06:57:23 +0000 (23:57 -0700)]
swr/rast: Fix WriteBitcodeToFile usage with llvm-7.0.
Fix build error after llvm-7.0svn r325155 ("Pass a reference to a module
to the bitcode writer.").
CXX rasterizer/jitter/libmesaswr_la-JitManager.lo
rasterizer/jitter/JitManager.cpp:548:30: error: reference to type 'const llvm::Module' could not bind to an lvalue of type 'const llvm::Module *'
llvm::WriteBitcodeToFile(M, bitcodeStream);
^
Suggested-by: George Kyriazis <george.kyriazis@intel.com>
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
Deepak Rawat [Tue, 24 Apr 2018 18:50:59 +0000 (11:50 -0700)]
egl/x11: Send invalidate to driver on copy_region path in swap_buffer
Similar to swap_available path send invalidate to the driver because
egl/X11 is not watching for for server's invalidate events. The
dri2_copy_region path is trigerred when server supports DRI2 version
minor 1.
Tested with piglit egl tests for regression.
V2: Move invalidate from dri2_copy_region to swap_buffer common.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Deepak Rawat <drawat@vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Juan A. Suarez Romero [Wed, 2 May 2018 16:20:16 +0000 (16:20 +0000)]
egl: check if colorspace/surface type is supported
According to EGL 1.4 spec, section 3.5.1 ("Creating On-Screen Rendering
Surfaces"), if config does not support the colorspace or alpha format
attributes specified in attrib_list (as defined for
eglCreateWindowSurface), an EGL_BAD_MATCH error is generated.
This fixes dEQP-EGL.functional.wide_color.*_888_colorspace_srgb (still
not merged,
https://android-review.googlesource.com/c/platform/external/deqp/+/667322),
which is crashing when trying to create a windows surface with RGB888
configuration and sRGB colorspace.
v2: Handle the fix in other backends (Tapani)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Iago Toral Quiroga [Fri, 2 Mar 2018 09:58:58 +0000 (10:58 +0100)]
anv/device: expose shaderInt16 support in gen8+
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Fri, 2 Mar 2018 10:12:38 +0000 (11:12 +0100)]
anv/pipeline: support SpvCapabilityInt16 in gen8+
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Fri, 2 Mar 2018 10:08:52 +0000 (11:08 +0100)]
compiler/spirv: add implementation to check for SpvCapabilityInt16 support
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Tue, 17 Apr 2018 08:23:47 +0000 (10:23 +0200)]
intel/compiler: implement 16-bit pack/unpack opcodes
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Tue, 17 Apr 2018 08:22:43 +0000 (10:22 +0200)]
compiler/spirv: implement 16-bit bitcasts
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Fri, 27 Apr 2018 07:28:48 +0000 (09:28 +0200)]
compiler/lower_64bit_packing: rename the pass to be more generic
It can do 32-bit packing too now.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Tue, 17 Apr 2018 08:09:03 +0000 (10:09 +0200)]
nir/lower_64bit_packing: extend the pass to handle packing from / to 16-bit.
With 16-bit support we can now do 32-bit packing, a follow-up patch will
rename the pass to something more generic.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Tue, 17 Apr 2018 08:07:40 +0000 (10:07 +0200)]
nir: add opcodes for 16-bit packing and unpacking
Noitice that we don't need 'split' versions of the 64-bit to / from
16-bit opcodes which we require during pack lowering to implement these
operations. This is because these operations can be expressed as a
collection of 32-bit from / to 16-bit and 64-bit to / from 32-bit
operations, so we don't need new opcodes specifically for them.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Thu, 19 Apr 2018 08:06:43 +0000 (10:06 +0200)]
intel/compiler: fix 16-bit comparisons
NIR assumes that booleans are always 32-bit, but Intel hardware produces
16-bit booleans for 16-bit comparisons. This means that we need to convert
the 16-bit result to 32-bit.
In the future we want to add an optimization pass to clean this up and
hopefully remove the conversions.
v2 (Jason): use the type of the source for the temporary and use
brw_reg_type_from_bit_size for the conversion to 32-bit.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Thu, 26 Apr 2018 08:07:56 +0000 (10:07 +0200)]
intel/compiler: lower some 16-bit integer operations to 32-bit
These are not supported in hardware for 16-bit integers.
We do the lowering pass after the optimization loop to ensure that we
lower ALU operations injected by algebraic optimizations too.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Thu, 26 Apr 2018 08:02:04 +0000 (10:02 +0200)]
compiler/nir: add a lowering pass to convert the bit size of ALU operations
Not all bit-sizes may be supported natively in hardware for all operations.
This pass allows drivers to lower such operations to a bit-size that is
actually supported and then converts the result back to the original
bit-size.
Compiler backends control which operations and wich bit-sizes require
the lowering through a callback function.
v2: generalize this pass and make it available in NIR core (Rob, Jason)
v3: remove some temporaries and reduce nesting in instruction loop using
a continue statement (Jason)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Thu, 3 May 2018 00:18:37 +0000 (02:18 +0200)]
intel/compiler: support negate and abs of half float immediates
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Wed, 2 May 2018 23:38:47 +0000 (01:38 +0200)]
intel/compiler: fix brw_imm_w for negative 16-bit integers
16-bit immediates need to replicate the 16-bit immediate value
in both words of the 32-bit value. This needs to be careful
to avoid sign-extension, which the previous implementation was
not handling properly.
For example, with the previous implementation, storing the value
-3 would generate imm.d = 0xfffffffd due to signed integer sign
extension, which is not correct. Instead, we should cast to
uint16_t, which gives us the correct result: imm.ud = 0xfffdfffd.
We only had a couple of cases hitting this path in the driver
until now, one with value -1, which would work since all bits are
one in this case, and another with value -2 in brw_clip_tri(),
which would hit the aforementioned issue (this case only affects
gen4 although we are not aware of whether this was causing an
actual bug somewhere).
v2: Make explicit uint32_t casting for left shift (Jason Ekstrand)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "18.0 18.1" <mesa-stable@lists.freedesktop.org>
Jose Maria Casanova Crespo [Wed, 2 May 2018 23:44:11 +0000 (01:44 +0200)]
intel/compiler: fix 16-bit int brw_negate_immediate and brw_abs_immediate
From Intel Skylake PRM, vol 07, "Immediate" section (page 768):
"For a word, unsigned word, or half-float immediate data,
software must replicate the same 16-bit immediate value to both
the lower word and the high word of the 32-bit immediate field
in a GEN instruction."
This fixes the int16/uint16 negate and abs immediates that weren't
taking into account the replication in lower and upper words.
v2: Integer cases are different to Float cases. (Jason Ekstrand)
Included reference to PRM (Jose Maria Casanova)
v3: Make explicit uint32_t casting for left shift (Jason Ekstrand)
Split half float implementation. (Jason Ekstrand)
Fix brw_abs_immediate (Jose Maria Casanova)
Cc: "18.0 18.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Tue, 10 Apr 2018 08:02:29 +0000 (10:02 +0200)]
intel/compiler: implement nir_instr_type_load_const for 16-bit constants
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Wed, 7 Mar 2018 10:12:18 +0000 (11:12 +0100)]
intel/compiler: implement conversions from 16-bit int/float to bool
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Tue, 6 Mar 2018 12:35:49 +0000 (13:35 +0100)]
intel/compiler: implement conversion between float/int 16-bit types
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Tue, 6 Mar 2018 11:14:05 +0000 (12:14 +0100)]
i965/compiler: handle conversion to smaller type in the lowering pass for that
The lowering pass was specialized to act on 64-bit to 32-bit conversions only,
but the implementation is valid for other cases.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Tue, 6 Mar 2018 07:57:26 +0000 (08:57 +0100)]
intel/compiler: fix isign for 16-bit integers
We need to use 16-bit constants with 16-bit instructions,
otherwise we get the following validation error:
"Destination stride must be equal to the ratio of the sizes of
the execution data type to the destination type"
Because the execution data type is 4B due to the 32-bit integer
constant.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Chris Wilson [Fri, 15 Dec 2017 13:42:25 +0000 (13:42 +0000)]
i965: Always try to create a logical context
Always enable use of HW logical contexts to preserve GPU state between
batches when the kernel supports such constructs, continuing to enforce
the required support for gen6+.
At runtime, this effectively removes the BRW_NEW_CONTEXT flag (and the
upload of invariant state) from the start of every batch for any kernel
supporting contexts. So long as the older atoms are correctly listening
to the right flag (NEW_CONTEXT rather than NEW_BATCH) this should
eliminate a few redundant state uploads for the older platforms.
No piglits were harmed on ctg and ilk, both with and without logical
contexts.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Neil Roberts [Wed, 2 May 2018 16:10:00 +0000 (18:10 +0200)]
spirv: Apply OriginUpperLeft to FragCoord
This behaviour was changed in
1e5b09f42f694687ac. The commit message
for that says it is just a “tidy up” so my assumption is that the
behaviour change was a mistake. It’s a little hard to decipher looking
at the diff, but the previous code before that patch was:
if (builtin == SpvBuiltInFragCoord || builtin == SpvBuiltInSamplePosition)
nir_var->data.origin_upper_left = b->origin_upper_left;
if (builtin == SpvBuiltInFragCoord)
nir_var->data.pixel_center_integer = b->pixel_center_integer;
After the patch the code was:
case SpvBuiltInSamplePosition:
nir_var->data.origin_upper_left = b->origin_upper_left;
/* fallthrough */
case SpvBuiltInFragCoord:
nir_var->data.pixel_center_integer = b->pixel_center_integer;
break;
Before the patch origin_upper_left affected both builtins and
pixel_center_integer only affected FragCoord. After the patch
origin_upper_left only affects SamplePosition and pixel_center_integer
affects both variables.
This patch tries to restore the previous behaviour by changing the
code to:
case SpvBuiltInFragCoord:
nir_var->data.pixel_center_integer = b->pixel_center_integer;
/* fallthrough */
case SpvBuiltInSamplePosition:
nir_var->data.origin_upper_left = b->origin_upper_left;
break;
This change will be important for ARB_gl_spirv which is meant to
support OriginLowerLeft.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Fixes:
1e5b09f42f694687ac "spirv: Tidy some repeated if checks..."
Samuel Iglesias Gonsálvez [Wed, 25 Apr 2018 09:55:49 +0000 (11:55 +0200)]
spirv: convert some operands for bitwise shift and bitwise ops to uint32
SPIR-V allows to define the shift, offset and count operands for
shift and bitfield opcodes with a bit-size different than 32 bits,
but in NIR the opcodes have that limitation. As agreed in the
mailing list, this patch adds a conversion to 32 bits to fix this.
For more info, see:
https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html
v2:
- src_bit_size will have zero value for variable bit-size operands (Jason).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Wed, 2 May 2018 09:55:59 +0000 (19:55 +1000)]
mesa: enable geom shaders in OpenGL 3.2 Compat profile
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bas Nieuwenhuizen [Tue, 1 May 2018 20:46:41 +0000 (22:46 +0200)]
radv: UseEnumerateInstanceVersion for the default version.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Tue, 1 May 2018 20:44:42 +0000 (22:44 +0200)]
radv: Don't check the incoming apiVersion on CreateInstance.
This fixes
dEQP-VK.api.device_init.create_instance_invalid_api_version
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Tue, 1 May 2018 16:02:45 +0000 (18:02 +0200)]
radv: Allow vkEnumerateInstanceVersion ProcAddr without instance.
Apparently the somewhere between 1.1.70 and 1.1.73 the loader started
depending on this. The loader then creates a 1.0 instance, which gets
into funny situation because we have a 1.1 device.
No idea how to do line wrapping in Mako though, my random guesses
did not work.
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Wed, 2 May 2018 17:40:28 +0000 (18:40 +0100)]
intel: aubinator: add an option to limit the number of decoded VBO lines
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Wed, 2 May 2018 17:39:20 +0000 (18:39 +0100)]
intel: decoder: limit to the number decoded lines from VBO
By default we set no limit, but the debug batch decoder in i965 sets
it to 100.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Thu, 8 Feb 2018 17:03:03 +0000 (09:03 -0800)]
anv: Advertise variableMultisampleRate
Initially, I didn't understand this feature. Turns out that all it
means is that you can switch multisample rates in the middle of a
zero-attachment subpass. We've been able to do this since forever.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Rob Clark [Wed, 2 May 2018 16:43:50 +0000 (12:43 -0400)]
nir: add missing dependency in meson.build
nir_builder_opcodes.h also depends on nir_intrinsics.py for generating
the system-value builders.
Reported-by: Christoph Haag <haagch@frickel.club>
Reported-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matthew Nicholls [Wed, 2 May 2018 12:03:52 +0000 (14:03 +0200)]
radv: fix multisample image copies
Previously before
fb077b0728, the LOD parameter was being used in place of the
sample index, which would only copy the first sample to all samples in the
destination image. After that multisample image copies wouldn't copy anything
from my observations.
This fixes some copy_and_blit CTS tests.
v3.1: - set lod to 0 for nir_txf_ms (Samuel)
v2: - use GLSL_SAMPLER_DIM_MS instead of 2D (Samuel)
- updated commit description (Samuel)
Fix this properly by copying each sample in a separate radv_CmdDraw and using a
pipeline with the correct rasterizationSamples for the destination image.
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kenneth Graunke [Wed, 2 May 2018 16:43:27 +0000 (09:43 -0700)]
intel: Fix 3DSTATE_CONSTANT buffer decoding.
First, this was iterating over the 3DSTATE_CONSTANT_* instruction
but trying to process fields of the 3DSTATE_CONSTANT_BODY substructure.
Secondly, the fields have been called Buffer[0] and Read Length[0],
for a while now, and we were not handling the subscripts correctly.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Lionel Landwerlin [Wed, 2 May 2018 16:51:03 +0000 (17:51 +0100)]
intel: fix aubinator include
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
7c22c150c40b3 ("intel: Move batch decoder/disassembler from tools/ to common/")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Wed, 2 May 2018 00:16:06 +0000 (17:16 -0700)]
i965: Reuse batch decoder infrastructure rather than open coding it.
With the new callback, Jason's newer batch decoder infrastructure
should be able to do just as well as the old open coded INTEL_DEBUG=bat
handling, with much less code. If there are any limitations, we'd like
to improve the common code rather than doing one-off hacks here.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Wed, 2 May 2018 04:49:17 +0000 (21:49 -0700)]
intel: Give the batch decoder a callback to ask about state size.
Given an arbitrary batch, we don't always know what the size of certain
things are, such as how many entries are in a binding table. But it's
easy for the driver to track that information, so with a simple callback
we can calculate this correctly for INTEL_DEBUG=bat.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Wed, 2 May 2018 00:27:08 +0000 (17:27 -0700)]
intel: Move batch decoder/disassembler from tools/ to common/
Making these part of libintel_common allows us to use them in the DRI
driver. The standalone tool binaries already link against the common
library, too, so it's no harder for them.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Fri, 13 Apr 2018 22:35:56 +0000 (15:35 -0700)]
i965: Allocate shadow batches to explicitly be the BO size.
This unfortunately makes it malloc/realloc on every new batch, rather
than once at startup. But it ensures that the shadow buffer's size will
absolutely match the BO size. Otherwise, as we tune BATCH_SZ/STATE_SZ
or bufmgr cache bucket sizes, we may get a BO size that's rounded up,
and fail to allocate the shadow buffer large enough.
This doesn't fix any bugs today, as BATCH_SZ/STATE_SZ are the size of
a cache bucket, but it's better to be safe than sorry.
Reported-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Lionel Landwerlin [Tue, 1 May 2018 23:17:19 +0000 (00:17 +0100)]
intel: batch-decoder: iterate VERTEX_BUFFER_STATE fields
The gen_field_iterator only iterates the fields of a given gen_group.
If we want to iterate the fields of another gen_group contained as
field, we need to do it manually.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Tue, 1 May 2018 23:13:39 +0000 (00:13 +0100)]
intel: decoder: fix starting dword of struct fields
Struct fields might span several dwords, but iter_dword is incremented
up to the last dword of the current field before we print out the
struct's fields. We can't use iter_dword for computing the offset into
the pointer of data to decode.
v2: Fix displayed offset number (Ken)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Tue, 1 May 2018 21:18:11 +0000 (22:18 +0100)]
intel: decoder: document when fields should be used
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Tue, 1 May 2018 21:14:12 +0000 (22:14 +0100)]
intel: decoder: identify groups with fixed length
<register> & <struct> elements always have fixed length. The
get_length() method implies that we're dealing with an instruction in
which the length is encoded into the variable data but the field
iterator uses it without checking what kind of gen_group it is dealing
with.
Let's make get_length() report the correct length regardless of the
gen_group (register, struct or instruction).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Tue, 1 May 2018 21:12:56 +0000 (22:12 +0100)]
intel: decoder: make the field iterator use more natural
while (iter_next()) { ... }
instead of
do { ... } while (iter_next());
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Vlad Golovkin [Mon, 16 Apr 2018 20:50:24 +0000 (23:50 +0300)]
nv50: Extract needed value bits without shifting them before calling bitcount
This can save one instruction since bitcount doesn't care about specific
bits' positions.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Antia Puentes [Sat, 28 Apr 2018 12:09:22 +0000 (14:09 +0200)]
intel: activate the gl_BaseVertex lowering
Surplus code related to the basevertex is removed.
The Vertex Elements contain now:
* VE 1: <firstvertex, BaseInstance, VertexID, InstanceID>
* VE 2: <DrawID, is_indexed_draw, 0, 0>
Also fixes unreachable message.
Fixes OpenGL CTS tests:
* KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysInstancedParameters
* KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters
* KHR-GL46.shader_draw_parameters_tests.MultiDrawArraysIndirectCountParameters
* KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysParameters
* KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysIndirectParameters
Fixes Piglit tests:
* arb_shader_draw_parameters-drawid-indirect baseinstance
* arb_shader_draw_parameters-basevertex
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102678
Antia Puentes [Sat, 28 Apr 2018 12:09:21 +0000 (14:09 +0200)]
compiler/nir: Add conditional lowering for gl_BaseVertex
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Antia Puentes [Sat, 28 Apr 2018 12:09:20 +0000 (14:09 +0200)]
intel: emit is_indexed_draw in the same VE than gl_DrawID
The Vertex Elements are now:
* VE 1: <BaseVertex/firstvertex, BaseInstance, VertexID, InstanceID>
* VE 2: <DrawID, is-indexed-draw, 0, 0>
VE1 is it kept as it was before, VE2 additionally contains the new
system value.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Antia Puentes [Sat, 28 Apr 2018 12:09:19 +0000 (14:09 +0200)]
intel/compiler: Add uses_is_indexed_draw flag
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Antia Puentes [Sat, 28 Apr 2018 12:09:18 +0000 (14:09 +0200)]
compiler: Add SYSTEM_VALUE_IS_INDEXED_DRAW and instrinsics
This VS system value contains if the draw command used to start the
rendering was an indexed draw command or a non-indexed one
(~0/0 respectively). Useful to calculate the gl_BaseVertex as:
(SYSTEM_VALUE_IS_INDEXED_DRAW & SYSTEM_VALUE_FIRST_VERTEX).
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Samuel Pitoiset [Tue, 24 Apr 2018 15:06:19 +0000 (17:06 +0200)]
radv: enable out-of-order rasterization by default
As the implementation is conservative, we can now enable it
by default. It can be disabled with RADV_DEBUG=nooutoforder.
Don't expect much more than 1% of improvements, but the gain
seems consistent.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 24 Apr 2018 15:06:18 +0000 (17:06 +0200)]
radv: only disable out-of-order rast for perfect occlusion queries
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kenneth Graunke [Wed, 2 May 2018 06:03:00 +0000 (23:03 -0700)]
i965: Drop unused gen5 sampler default color struct.
Trivial.
Kenneth Graunke [Wed, 2 May 2018 06:02:16 +0000 (23:02 -0700)]
i965: Make brw_vs_outputs_written static.
Drop a prototype. Trivial.
Nanley Chery [Sat, 24 Feb 2018 09:26:20 +0000 (01:26 -0800)]
i965/tex_image: Avoid the ASTC LDR workaround on gen9lp
Both the internal documentation and the results of testing this in the
CI suggest that this is unnecessary. Add the fixes tag because this
reduces an internal benchmark's startup time by about 17 seconds
(reported by Eero).
Fixes:
710b1d2e665 "i965/tex_image: Flush certain subnormal ASTC channel values"
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 1 May 2018 20:07:21 +0000 (13:07 -0700)]
freedreno: Fix ir3_cmdline.c build.
Fixes:
6487e7a30c9e ("nir: move GL specific passes to src/compiler/glsl")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Jason Ekstrand [Tue, 1 May 2018 16:59:24 +0000 (09:59 -0700)]
anv: Allow lookup of vkEnumerateInstanceVersion without an instance
Fixes:
cbab2d1da5edfe9df27a010adf8b1aa9dbee473b
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Jason Ekstrand [Mon, 30 Apr 2018 22:15:37 +0000 (15:15 -0700)]
anv: Don't advertise Float64 or Int64 on HW without 64-bit types
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Samuel Pitoiset [Fri, 27 Apr 2018 08:53:13 +0000 (10:53 +0200)]
radv: compute the number of subpass attachments correctly
Only count color attachments twice if resolves are used, also
account for the depth stencil attachment if present.
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Dave Airlie [Tue, 1 May 2018 02:32:02 +0000 (12:32 +1000)]
radv: set fmask_surf_index on fmask surfaces.
This is needed for gfx9 and later for all fmask surface index.
(Mentioned by Marek on irc)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Brian Paul [Tue, 1 May 2018 15:51:45 +0000 (09:51 -0600)]
gallium/i915: fix PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE typo
Fixes:
fffe5e2d14f807c ("gallium: add initial support for conservative
rasterization")
Trivial.
Rhys Perry [Sat, 7 Apr 2018 22:15:00 +0000 (16:15 -0600)]
nvc0: add conservative rasterization support
Subpixel precision bias, dilation and the post-snap mode are supported on
GM200 and newer. The pre-snap mode is supported for triangle primitives on
GP100.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Rhys Perry [Fri, 27 Apr 2018 14:43:00 +0000 (08:43 -0600)]
st/mesa: add support for nvidia conservative rasterization extensions
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Rhys Perry [Sat, 7 Apr 2018 22:15:00 +0000 (16:15 -0600)]
gallium: add initial support for conservative rasterization
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rhys Perry [Fri, 27 Apr 2018 17:35:00 +0000 (11:35 -0600)]
mesa: add support for nvidia conservative rasterization extensions
Although the specs are written against compatibility GL 4.3 and allows core
profile and GLES2+, it is exposed for GL 1.0+ and GLES1 and GLES2+.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Thu, 26 Apr 2018 17:55:46 +0000 (11:55 -0600)]
glsl/tests: add GLSL_TYPE_UINT8, GLSL_TYPE_INT8 cases to switch statements
To silence warnings about unhandled switch values.
Untested otherwise.
v2: move the INT/UINT8 cases after the INT/UINT16 cases, per Eric.
Reviewed-by: Eric Anholt <eric@anholt.net>
Brian Paul [Thu, 26 Apr 2018 17:55:16 +0000 (11:55 -0600)]
tgsi: use enums instead of unsigned in ureg code
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Timothy Arceri [Mon, 30 Apr 2018 10:39:43 +0000 (20:39 +1000)]
nir: move GL specific passes to src/compiler/glsl
With this we should have no passes in src/compiler/nir with any
dependencies on headers from core GL Mesa.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Andres Rodriguez [Mon, 30 Apr 2018 22:05:49 +0000 (18:05 -0400)]
radv/winsys: fix leaking resources from bo's imported by fd
A bo's ref_count was not being initialized when imported from an fd.
Therefore, we would fail to free the resource during VkFreeMemory().
This patch fixes applications like hifi VR in threaded mode, which
perform frequent imports/releases of IPC shared memory.
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Scott D Phillips [Mon, 30 Apr 2018 17:25:47 +0000 (10:25 -0700)]
i965/tiled_memcpy: ytiled_to_linear a cache line at a time
Similar to the transformation applied to linear_to_ytiled, also align
each readback from the ytiled source to a cacheline (i.e. transfer a
whole cacheline from the source before moving on to the next column).
This will allow us to utilize movntqda (_mm_stream_si128) in a
subsequent patch to obtain near WB readback performance when accessing
the uncached ytiled memory, an order of magnitude improvement.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Chris Wilson [Mon, 30 Apr 2018 17:25:46 +0000 (10:25 -0700)]
i965: Record mipmap resolver for unmapping
When mapping a region of the mipmap_tree, record which complementary
method to use to unmap it afterwards. By doing so we can avoid
duplicating the decision tree used when mapping and thereby eliminate
trivial errors that can be introduced if the two if-chains become out of
sync.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:45 +0000 (10:25 -0700)]
i965: Move unmap_depthstencil before map_depthstencil
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:44 +0000 (10:25 -0700)]
i965: Move unmap_etc before map_etc
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:43 +0000 (10:25 -0700)]
i965: Move unmap_s8 before map_s8
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:42 +0000 (10:25 -0700)]
i965: Move unmap_movntdqa before map_movntdqa
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:41 +0000 (10:25 -0700)]
i965: Move unmap_blit before map_blit
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:40 +0000 (10:25 -0700)]
i965: Move unmap_gtt before map_gtt
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Dave Airlie [Mon, 30 Apr 2018 02:45:14 +0000 (12:45 +1000)]
ac/nir: expand 64-bit vec3 loads to fix shuffling.
If loading 64-bit vec3 values, a 4 component load would be followed
by a 2 component load and the resulting shuffle would fail as it
requires 2 4 components. This just expands the second results
vector out to 4 components.
This fixes 100 CTS tests:
dEQP-VK.spirv_assembly.type.vec3.*64*
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kenneth Graunke [Tue, 10 Apr 2018 23:01:50 +0000 (16:01 -0700)]
i965: Don't stomp initial kflags for program cache.
We want to flag EXEC_OBJECT_CAPTURE, but we ought to preserve any
existing kflags. Today, there are none (as the program cache doesn't
support 48-bit addressing), but once we start using softpin, we'll
need to preserve EXEC_OBJECT_PINNED.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Tue, 10 Apr 2018 08:23:15 +0000 (01:23 -0700)]
i965: Let batchbuffers be placed anywhere in the 48-bit address space.
We were trying to mark batch buffers with EXEC_OBJECT_CAPTURE, and
accidentally stomped EXEC_OBJECT_SUPPORTS_48B_ADDRESS in the process.
There's no reason to restrict batch buffers to the lower 4GB.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Scott D Phillips [Thu, 19 Apr 2018 14:54:28 +0000 (07:54 -0700)]
intel: fix check for 48b ppgtt support
The previous logic of the supports_48b_addresses wasn't actually
checking if i915.ko was running with full_48bit_ppgtt. The ENOENT
it was checking for was actually coming from the invalid context
id provided in the test execbuffer. There is no path in the
kernel driver where the presence of
EXEC_OBJECT_SUPPORTS_48B_ADDRESS leads to an error.
Instead, check the default context's GTT_SIZE param for a value
greater than 4 GiB
v2 (Ken): Fix in i965 as well.
v3 Check GTT_SIZE instead of HAS_ALIASING_PPGTT (Chris Wilson)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Leo Liu [Fri, 27 Apr 2018 12:32:41 +0000 (08:32 -0400)]
st/omx/enc: fix blit setup for YUV LoadImage
The blit here involves scaling since it's copying from I8 format to R8G8 format.
Half of source will be filtered out with PIPE_TEX_FILTER_NEAREST instruction, it
looks that GPU always uses the second half as source. Currently we use "1" as
the start point of x for R, then causing 1 source pixel of U component shift to
right. So "-1" should be the start point for U component.
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Juan A. Suarez Romero [Fri, 27 Apr 2018 08:38:09 +0000 (10:38 +0200)]
autotools, meson: bump up required VA version
Due using a new VP9 config we use, required VA API 0.39
Fixes:
413c5ca3727 ("travis: update libva required version")
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Juan A. Suarez Romero [Sat, 28 Apr 2018 17:01:48 +0000 (17:01 +0000)]
docs: update calendar, add news and link release notes to 18.0.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Juan A. Suarez Romero [Sat, 28 Apr 2018 16:57:30 +0000 (16:57 +0000)]
docs: add sha256 checksums for 18.0.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit
b3eed3ad03fd1eb61474cd0a8a173ad40fb8a876)
Juan A. Suarez Romero [Sat, 28 Apr 2018 16:22:11 +0000 (16:22 +0000)]
docs: add release notes for 18.0.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit
d38da7bd2d4387635fac8bc7f45e64f50dc43c43)