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Rui Ueyama [Mon, 31 Oct 2016 17:38:56 +0000 (17:38 +0000)]
Define DbiStreamBuilder::addSectionMap.
This change enables LLD to construct a Section Map stream in a PDB file.
I do not understand all these fields in the Section Map yet, but it seems
like a copy of a COFF section header in another format.
With this patch, DbiStreamBuilder can emit a Section Map which
llvm-pdbdump can dump.
Differential Revision: https://reviews.llvm.org/D26112
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285606
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David Majnemer [Mon, 31 Oct 2016 17:20:43 +0000 (17:20 +0000)]
SingleLinkedListIterator::operator++(int) shouldn't return a reference
The returned reference is to a local object. Instead, make a copy.
Found by PVS-Studio.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285603
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David Majnemer [Mon, 31 Oct 2016 17:11:31 +0000 (17:11 +0000)]
Fix an unconditional break in checkMachOAndArchFlags
Found by PVS-Studio.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285598
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David Majnemer [Mon, 31 Oct 2016 17:11:23 +0000 (17:11 +0000)]
SymbolRef::Type is not a bitfield and must be compared directly
Found by PVS-Studio.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285597
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Greg Clayton [Mon, 31 Oct 2016 16:46:02 +0000 (16:46 +0000)]
Modify DWARFFormValue to remember the DWARFUnit that it was decoded with.
Modifying DWARFFormValue to remember the DWARFUnit that it was encoded with can simplify the usage of instances of this class. Previously users would have to try and pass in the same DWARFUnit that was used to decode the form value and there was a possibility that a different DWARFUnit might be supplied to the functions that extract values (strings, CU relative references, addresses) and cause problems. This fixes this potential issue by storing the DWARFUnit inside the DWARFFormValue so that this mistake can't be made. Instances of DWARFFormValue are not stored permanently and are used as temporary values, so the increase in size of an instance of DWARFFormValue isn't a big deal. This makes decoding form values more bullet proof and is a change that will be used by future modifications.
https://reviews.llvm.org/D26052
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285594
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Davide Italiano [Mon, 31 Oct 2016 16:21:48 +0000 (16:21 +0000)]
[lli] Don't strip away const qualifier. Unbreak the gcc6 build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285592
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Michael Zuckerman [Mon, 31 Oct 2016 16:19:58 +0000 (16:19 +0000)]
[x86][inline-asm][AVX512][llvm][PART-2]
Introducing "k" and "Yk" constraints for extended inline assembly, enabling use of AVX512 masked vectorized instructions.
Commit on behalf of mharoush
Extending inline assembly support, compatible with GCC as folowing:
"k" constraint hints the compiler to select any of AVX512 k0-k7 registers.
"Yk" constraint is a subset of "k" excluding k0 which is not allowd to be used as a mask.
Reviewer: 1. rnk
Differential Revision: https://reviews.llvm.org/D25062
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285591
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Artem Tamazov [Mon, 31 Oct 2016 16:07:39 +0000 (16:07 +0000)]
[AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions.
Fixes Bug 30808.
Note that passing subtarget information to predicates seems too complicated, so gfx8-specific def smrd_offset_20 introduced.
Old gfx6/7-specific def renamed to smrd_offset_8 for clarity.
Lit tests updated.
Differential Revision: https://reviews.llvm.org/D26085
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285590
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Krzysztof Parzyszek [Mon, 31 Oct 2016 15:45:09 +0000 (15:45 +0000)]
[Hexagon] Don't expand mux instructions with both sources identical
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285588
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George Rimar [Mon, 31 Oct 2016 15:33:00 +0000 (15:33 +0000)]
Recommit r285285 - [Object/ELF] - Fixed behavior when SectionHeaderTable->sh_size is too large.
with fix: edited invalid-section-index2.elf input to pass the new check and
fail on the same place it was intended to fail.
Original commit message:
Elf.h already has code checking that section table does not go past end of file.
Problem is that this check may not work on values greater than UINT64_MAX / Header->e_shentsize
because of calculation overflow.
Parch fixes the issue.
Differential revision: https://reviews.llvm.org/D25432
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285586
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Ulrich Weigand [Mon, 31 Oct 2016 14:33:29 +0000 (14:33 +0000)]
[SystemZ] Rework processor feature definitions and add -mcpu=archX support
This patch implements two changes:
- Move processor feature definition into a new file SystemZFeatures.td,
and provide explicit lists of supported and unsupported features for
each level of the z/Architecture. This allows specifying unsupported
features in the scheduler definition files for each processor.
- Add optional aliases for the -mcpu processor names according to the
level of the z/Architecture, for compatibility with other compilers
on the platform. The supported aliases are:
-mcpu=arch8 equals -mcpu=z10
-mcpu=arch9 equals -mcpu=z196
-mcpu=arch10 equals -mcpu=zEC12
-mcpu=arch11 equals -mcpu=z13
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285577
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Ulrich Weigand [Mon, 31 Oct 2016 14:28:43 +0000 (14:28 +0000)]
[SystemZ] Guard LEFR/LFER with FeatureVector
The LEFR/LFER pseudos are aliases for vector instructions and should
therefore be guared by FeatureVector. If they aren't, the TableGen
scheduler definition checking might complain that there is no data
for those pseudos for pre-z13 machines.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285576
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Ulrich Weigand [Mon, 31 Oct 2016 14:25:05 +0000 (14:25 +0000)]
[SystemZ] Correctly diagnose missing features in AsmParser
Currently, when using an instruction that is not supported on the
currently selected architecture, the LLVM assembler is likely to
diagnose an "invalid operand" instead of a "missing feature".
This is because many operands require a custom parser in order to
be processed correctly, and if an instruction is not available
according to the current feature set, the generated parser code
will also not detect the associated custom operand parsers.
Fixed by temporarily enabling all features while parsing operands.
The missing features will then be correctly detected when actually
parsing the instruction itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285575
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Ulrich Weigand [Mon, 31 Oct 2016 14:21:36 +0000 (14:21 +0000)]
[SystemZ] Fix encoding of MVCK and .insn ss
LLVM currently treats the first operand of MVCK as if it were a
regular base+index+displacement address. However, it is in fact
a base+displacement combined with a length register field.
While the two might look syntactically similar, there are two
semantic differences:
- %r0 is a valid length register, even though it cannot be used
as an index register.
- In an expression with just a single register like 0(%rX), the
register is treated as base with normal addresses, while it is
treated as the length register (with an empty base) for MVCK.
Fixed by adding a new operand parser class BDRAddr and reworking
the assembler parser to distinguish between address + length
register operands and regular addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285574
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Dorit Nuzman [Mon, 31 Oct 2016 13:17:31 +0000 (13:17 +0000)]
Second attempt at r285517.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285568
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Jonas Paulsson [Mon, 31 Oct 2016 13:05:48 +0000 (13:05 +0000)]
[SystemZ] Model 2 VBU units (not 1) in SystemZScheduleZ13.td.
NFC.
Review: Ulrich Weigand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285566
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Alexey Bataev [Mon, 31 Oct 2016 12:10:53 +0000 (12:10 +0000)]
Improved cost model for FDIV and FSQRT, by Andrew Tischenko
There is a bug describing poor cost model for floating point operations:
Bug 29083 - [X86][SSE] Improve costs for floating point operations. This
patch is the second one in series of patches dealing with cost model.
Differential Revision: https://reviews.llvm.org/D25722
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285564
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Manuel Klimek [Mon, 31 Oct 2016 11:40:14 +0000 (11:40 +0000)]
Add triple to test so it does not fail on windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285560
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Manuel Klimek [Mon, 31 Oct 2016 11:18:39 +0000 (11:18 +0000)]
Delete .s file that did not test anything, and check in test that works.
In D26098, Davide Italiano submitted a .s file instead of the .ll file
that was the last stage of the review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285559
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Eugene Leviant [Mon, 31 Oct 2016 11:03:01 +0000 (11:03 +0000)]
Add getOffset to ELFSectionRef
Differential revision: https://reviews.llvm.org/D26074
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285558
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Craig Topper [Mon, 31 Oct 2016 05:55:57 +0000 (05:55 +0000)]
[AVX-512] Add missing patterns for selecting masked vector extracts that started from shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285546
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Sanjoy Das [Mon, 31 Oct 2016 03:32:45 +0000 (03:32 +0000)]
Make a test case more rigorous; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285536
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Sanjoy Das [Mon, 31 Oct 2016 03:32:43 +0000 (03:32 +0000)]
[SCEV] Try to order n-ary expressions in CompareValueComplexity
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285535
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Sanjoy Das [Mon, 31 Oct 2016 03:32:39 +0000 (03:32 +0000)]
[SCEV] Reduce boilerplate in unit tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285534
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Sanjoy Das [Sun, 30 Oct 2016 23:52:56 +0000 (23:52 +0000)]
[SCEV] In CompareValueComplexity, order global values by their name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285529
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Sanjoy Das [Sun, 30 Oct 2016 23:52:53 +0000 (23:52 +0000)]
[SCEV] Use auto for consistency with an upcoming change; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285528
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Sanjoy Das [Sun, 30 Oct 2016 23:52:50 +0000 (23:52 +0000)]
Clean up test a little bit; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285527
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Sanjay Patel [Sun, 30 Oct 2016 18:19:35 +0000 (18:19 +0000)]
[DAG] x | x --> x
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285522
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Sanjay Patel [Sun, 30 Oct 2016 18:13:30 +0000 (18:13 +0000)]
[DAG] x & x --> x
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285521
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Sanjay Patel [Sun, 30 Oct 2016 18:04:19 +0000 (18:04 +0000)]
[x86] add tests for basic logic op folds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285520
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Dorit Nuzman [Sun, 30 Oct 2016 14:34:57 +0000 (14:34 +0000)]
Revert r285517 due to build failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285518
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Dorit Nuzman [Sun, 30 Oct 2016 12:23:26 +0000 (12:23 +0000)]
[LoopVectorize] Make interleaved-accesses analysis less conservative about
possible pointer-wrap-around concerns, in some cases.
Before this patch, collectConstStridedAccesses (part of interleaved-accesses
analysis) called getPtrStride with [Assume=false, ShouldCheckWrap=true] when
examining all candidate pointers. This is too conservative. Instead, this
patch makes collectConstStridedAccesses use an optimistic approach, calling
getPtrStride with [Assume=true, ShouldCheckWrap=false], and then, once the
candidate interleave groups have been formed, revisits the pointer-wrapping
analysis but only where it matters: namely, in groups that have gaps, and where
the gaps are not at the very end of the group (in which case the loop is
peeled). This second time getPtrStride is called with [Assume=false,
ShouldCheckWrap=true], but this could further be improved to using Assume=true,
once we also add the logic to track that we are not going to meet the scev
runtime checks threshold.
Differential Revision: https://reviews.llvm.org/D25276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285517
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Craig Topper [Sun, 30 Oct 2016 06:56:16 +0000 (06:56 +0000)]
[X86] Use intrinsics table for PMADDUBSW and PMADDWD so that we can use the legacy intrinsics to select EVEX encoded instructions when available.
This removes a couple tablegen classes that become unused after this change. Another class gained an additional parameter to allow PMADDUBSW to specify a different result type from its input type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285515
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Hongbin Zheng [Sun, 30 Oct 2016 06:07:59 +0000 (06:07 +0000)]
[Polly] Remove the unused POLLY_LINK_LIBS for linking polly into
tools
Differential Revision: https://reviews.llvm.org/D25861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285514
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Teresa Johnson [Sun, 30 Oct 2016 05:40:44 +0000 (05:40 +0000)]
[ThinLTO] Use per-summary flag to prevent exporting locals used in inline asm
Summary:
Instead of using the workaround of suppressing the entire index for
modules that call inline asm that may reference locals, use the
NoRename flag on the summary for any locals in the llvm.used set, and
add a reference edge from any functions containing inline asm.
This avoids issues from having no summaries despite the module defining
global values, which was preventing more aggressive index-based
optimization. It will be followed by a subsequent patch to make a
similar fix for local references in module level asm (to fix PR30610).
Reviewers: mehdi_amini
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26121
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285513
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Teresa Johnson [Sun, 30 Oct 2016 05:15:23 +0000 (05:15 +0000)]
[ThinLTO] Correctly resolve linkonce when importing aliasee
Summary:
When we have an aliasee that is linkonce, while we can't convert
the non-prevailing copies to available_externally, we still need to
convert the prevailing copy to weak. If a reference to the aliasee
is exported, not converting a copy to weak will result in undefined
references when the linkonce is removed in its original module.
Add a new test and update existing tests.
Reviewers: mehdi_amini
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285512
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Craig Topper [Sun, 30 Oct 2016 00:02:55 +0000 (00:02 +0000)]
[X86] Don't use loadv2i64 on SSE version of PMULHRSW. Use memopv2i64 instead.
This bug was introduced in r285501.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285510
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NAKAMURA Takumi [Sat, 29 Oct 2016 23:14:18 +0000 (23:14 +0000)]
NativeFormatting.cpp: Fix build for mingw. Where would writePadding() be?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285509
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Teresa Johnson [Sat, 29 Oct 2016 21:52:23 +0000 (21:52 +0000)]
[ThinLTO] Rename doPromoteLocalToGlobal to shouldPromoteLocalToGlobal (NFC)
Rename as suggested in code review for D26063.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285508
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Teresa Johnson [Sat, 29 Oct 2016 21:31:48 +0000 (21:31 +0000)]
[ThinLTO] Use NoPromote flag in summary during promotion
Summary:
Replace the check of whether a GV has a section with the flag check
in the summary. This is in preparation for using the NoPromote flag
to convey other situations when we can't promote (e.g. locals used in
inline asm).
Reviewers: mehdi_amini
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26063
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285507
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Peter Collingbourne [Sat, 29 Oct 2016 20:57:12 +0000 (20:57 +0000)]
IR: Remove a no longer needed assert.
This assert was checking for a miscompile in a version of GCC that
we no longer support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285506
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Craig Topper [Sat, 29 Oct 2016 18:41:45 +0000 (18:41 +0000)]
[X86] Use intrinsics table for VPMULHRSW intrincis so that the legacy intrinsics can select EVEX encoded instructions when available.
This requires a minor rename of the instructions due to the use of different tablegen classes and how the names are concatenated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285501
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Sanjay Patel [Sat, 29 Oct 2016 16:21:19 +0000 (16:21 +0000)]
[ValueTracking] recognize more variants of smin/smax
Try harder to detect obfuscated min/max patterns: the initial pattern was added with D9352 / rL236202.
There was a bug fix for PR27137 at rL264996, but I think we can do better by folding the corresponding
smax pattern and commuted variants.
The codegen tests demonstrate the effect of ValueTracking on the backend via SelectionDAGBuilder. We
can't expose these differences minimally in IR because we don't have smin/smax intrinsics for IR.
Differential Revision: https://reviews.llvm.org/D26091
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285499
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Sanjay Patel [Sat, 29 Oct 2016 16:02:57 +0000 (16:02 +0000)]
[x86] add tests for smin/smax matchSelPattern (D26091)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285498
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Sanjay Patel [Sat, 29 Oct 2016 15:22:04 +0000 (15:22 +0000)]
[InstCombine] re-use bitcasted compare operands in selects (PR28001)
These mixed bitcast patterns show up with SSE/AVX intrinsics because we bitcast function parameters to <2 x i64>.
The bitcasts obfuscate the expected min/max forms as shown in PR28001:
https://llvm.org/bugs/show_bug.cgi?id=28001#c6
Differential Revision: https://reviews.llvm.org/D25943
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285495
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Simon Pilgrim [Sat, 29 Oct 2016 11:29:39 +0000 (11:29 +0000)]
[DAGCombiner] (REAPPLIED) Add vector demanded elements support to computeKnownBits
Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements.
This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1.
The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used.
I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course.
DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit.
This looked like this had caused compile time regressions on some buildbots (and was reverted in rL285381), but appears to have just been a harmless bystander!
Differential Revision: https://reviews.llvm.org/D25691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285494
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Elena Demikhovsky [Sat, 29 Oct 2016 08:44:46 +0000 (08:44 +0000)]
Fixed FMA + FNEG combine.
Masked form of FMA should be omitted in this optimization.
Differential Revision: https://reviews.llvm.org/D25984
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285492
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Matt Arsenault [Sat, 29 Oct 2016 04:05:06 +0000 (04:05 +0000)]
AMDGPU: Use 1/2pi inline imm on VI
I'm guessing at how it is supposed to be printed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285490
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Matthias Braun [Sat, 29 Oct 2016 01:03:41 +0000 (01:03 +0000)]
AArch64DeadRegisterDefinitionsPass: Cleanup; NFC
- Fix doxygen file comment
- reduce indentation in loop
- Factor out some common subexpressions
- Move independent helper function out of class
- Fix Changed flag (this is not strictly NFC but a bugfix, but the flag
seems ignored anyway)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285488
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Rui Ueyama [Sat, 29 Oct 2016 00:56:44 +0000 (00:56 +0000)]
Define calculateDbgStreamSize for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285487
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Tim Shen [Sat, 29 Oct 2016 00:51:41 +0000 (00:51 +0000)]
[APFloat] Remove the redundent function body of uninitialized ctor, which should be done in r285468
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285486
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Zachary Turner [Sat, 29 Oct 2016 00:27:22 +0000 (00:27 +0000)]
Resubmit "Add support for advanced number formatting."
This resubmits r284436 and r284437, which were reverted in
r284462 as they were breaking the AArch64 buildbot.
The breakage on AArch64 turned out to be a miscompile which is
still not fixed, but is actively tracked at llvm.org/pr30748.
This resubmission re-writes the code in a way so as to make the
miscompile not happen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285483
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Rui Ueyama [Fri, 28 Oct 2016 23:57:37 +0000 (23:57 +0000)]
Do not print out Flags field twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285481
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Davide Italiano [Fri, 28 Oct 2016 23:55:32 +0000 (23:55 +0000)]
[DAGCombiner] Fix a crash visiting `AND` nodes.
Instead of asserting that the shift count is != 0 we just bail out
as it's not profitable trying to optimize a node which will be
removed anyway.
Differential Revision: https://reviews.llvm.org/D26098
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285480
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Tom Stellard [Fri, 28 Oct 2016 23:53:48 +0000 (23:53 +0000)]
AMDGPU/SI: Don't use non-0 waitcnt values when waiting on Flat instructions
Summary:
Flat instruction can return out of order, so we need always need to wait
for all the outstanding flat operations.
Reviewers: tony-tye, arsenm
Subscribers: kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl
Differential Revision: https://reviews.llvm.org/D25998
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285479
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Matt Arsenault [Fri, 28 Oct 2016 23:00:38 +0000 (23:00 +0000)]
AMDGPU: Fix instruction flags for s_endpgm
Set isReturn, remove hasSideEffects. Also remove
hasCtrlDep, I'm not really sure what that does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285476
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Adrian Prantl [Fri, 28 Oct 2016 22:57:02 +0000 (22:57 +0000)]
Refactor DW_LNE_* into Dwarf.def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285475
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Adrian Prantl [Fri, 28 Oct 2016 22:56:59 +0000 (22:56 +0000)]
Refactor DW_LNS_* into Dwarf.def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285474
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Adrian Prantl [Fri, 28 Oct 2016 22:56:56 +0000 (22:56 +0000)]
Refactor DW_APPLE_PROPERTY_* into Dwarf.def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285473
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Adrian Prantl [Fri, 28 Oct 2016 22:56:53 +0000 (22:56 +0000)]
Refactor DW_CFA_* into Dwarf.def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285472
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Adrian Prantl [Fri, 28 Oct 2016 22:56:50 +0000 (22:56 +0000)]
Remove whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285471
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Adrian Prantl [Fri, 28 Oct 2016 22:56:45 +0000 (22:56 +0000)]
Refactor all DW_FORM_* constants into Dwarf.def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285470
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Tim Shen [Fri, 28 Oct 2016 22:45:33 +0000 (22:45 +0000)]
[APFloat] Fix memory bugs revealed by MSan
Reviewers: eugenis, hfinkel, kbarton, iteratee, echristo
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D26102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285468
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Justin Bogner [Fri, 28 Oct 2016 22:42:54 +0000 (22:42 +0000)]
SDAG: Make sure we use an allocatable reg class when we create this vreg
As per the discussion on r280783, if constrainRegClass fails we need
to call getAllocatableClass like we did before that commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285467
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Kostya Serebryany [Fri, 28 Oct 2016 22:03:54 +0000 (22:03 +0000)]
[libFuzzer] mention one more trophie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285465
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Justin Lebar [Fri, 28 Oct 2016 21:56:07 +0000 (21:56 +0000)]
Add missing lit.local.cfg to llvm/test/Transforms/CodeGenPrepare/NVPTX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285464
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Matt Arsenault [Fri, 28 Oct 2016 21:55:15 +0000 (21:55 +0000)]
AMDGPU: Add definitions for scalar store instructions
Also add glc bit to the scalar loads since they exist on VI
and change the caching behavior.
This currently has an assembler bug where the glc bit is incorrectly
accepted on SI/CI which do not have it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285463
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Matt Arsenault [Fri, 28 Oct 2016 21:55:08 +0000 (21:55 +0000)]
AMDGPU: Rename glc operand type
While trying to add the glc bit to SMEM instructions on VI
with the new refactoring I ran into some kind of shadowing
problem for the glc operand when using the pseudoinstruction
as a multiclass parameter.
Everywhere that currently uses it defines the operand to have the same
name as its type, i.e. glc:$glc which works. For some reason now it
conflicts, and its up evaluating to the wrong thing. For the
real encoding classes,
let Inst{16} = !if(ps.has_glc, glc, ?); was not being evaluated
and still visible in the Inst initializer in the expanded td file.
In other cases I got a a different error about an illegal operand
where this was using { 0 } initializer from the bits<1> glc initializer
instead of evaluating it as false in the if.
For consistency all of the operand types should probably
be captialized to avoid conflicting with the variable names
unless somebody has a better idea of how to fix this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285462
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Justin Lebar [Fri, 28 Oct 2016 21:44:00 +0000 (21:44 +0000)]
[NVPTX] Compute 'rem' using the result of 'div', if possible.
Summary:
In isel, transform
Num % Den
into
Num - (Num / Den) * Den
if the result of Num / Den is already available.
Reviewers: tra
Subscribers: hfinkel, llvm-commits, jholewinski
Differential Revision: https://reviews.llvm.org/D26090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285461
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Justin Lebar [Fri, 28 Oct 2016 21:43:54 +0000 (21:43 +0000)]
Don't leave unused divs/rems sitting around in BypassSlowDivision.
Summary:
This "pass" eagerly creates div and rem instructions even when only one
is needed -- it relies on a later pass (machine DCE?) to clean them up.
This is problematic not just from a cleanliness perspective (this pass
is running during CodeGenPrepare, so should leave the IR in a better
state), but it also creates a problem for instruction selection. If we
always have a div+rem, isel will always select a divrem instruction (if
possible), even when a single div or rem would do.
Specifically, in NVPTX, we want to compute rem from the output of div,
if available. But if a div is not available, we want to leave the rem
alone. This transformation is overeager if div is always available.
Because this code runs as part of CodeGenPrepare, it's nontrivial to
write a test for this change. But this will effectively be tested by
a later patch which adds the aforementioned change to NVPTX isel.
Reviewers: tra
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285460
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Justin Lebar [Fri, 28 Oct 2016 21:43:51 +0000 (21:43 +0000)]
Don't claim the udiv created in BypassSlowDivision is exact.
Summary:
In BypassSlowDivision's short-dividend path, we would create e.g.
udiv exact i32 %a, %b
"exact" here means that we are asserting that %a is a multiple of %b.
But we have no reason to believe this must be true -- this is just a
bug, as far as I can tell.
Reviewers: tra
Subscribers: jholewinski, llvm-commits
Differential Revision: https://reviews.llvm.org/D26097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285459
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Justin Bogner [Fri, 28 Oct 2016 20:48:47 +0000 (20:48 +0000)]
cmake: Enable the lto cache when building with -flto=thin on darwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285450
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Matt Arsenault [Fri, 28 Oct 2016 20:33:01 +0000 (20:33 +0000)]
AMDGPU: Change check prefix in test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285449
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Adrian Prantl [Fri, 28 Oct 2016 20:32:17 +0000 (20:32 +0000)]
Fix a copy&paste error in the macro definition for HANDLE_DW_MACRO and
HANDLE_DE_RLE. Caught by the LLDB build bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285448
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Matt Arsenault [Fri, 28 Oct 2016 20:31:47 +0000 (20:31 +0000)]
AMDGPU: Diagnose using too many SGPRs
This is possible when using inline asm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285447
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Adrian Prantl [Fri, 28 Oct 2016 20:18:26 +0000 (20:18 +0000)]
Remove redundant prefixes from constants and unbreak the LLDB bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285444
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Tim Shen [Fri, 28 Oct 2016 20:13:06 +0000 (20:13 +0000)]
[APFloat] Use std::move() in move assignment operator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285442
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Krzysztof Parzyszek [Fri, 28 Oct 2016 20:06:37 +0000 (20:06 +0000)]
Handle non-~0 lane masks on live-in registers in LivePhysRegs
When LivePhysRegs adds live-in registers, it recognizes ~0 as a special
lane mask indicating the entire register. If the lane mask is not ~0,
it will only add the subregisters that overlap the specified lane mask.
The problem is that if a live-in register does not have subregisters,
and the lane mask is not ~0, it will not be added to the live set.
(The given lane mask may simply be the lane mask of its register class.)
If a register does not have subregisters, add it to the live set if
the lane mask is non-zero.
Differential Revision: https://reviews.llvm.org/D26094
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285440
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Matt Arsenault [Fri, 28 Oct 2016 20:00:33 +0000 (20:00 +0000)]
SpeculativeExecution: Allow speculating more inst types
Partial step towards removing the whitelist and only
using TTI's cost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285438
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Matt Arsenault [Fri, 28 Oct 2016 19:43:31 +0000 (19:43 +0000)]
AMDGPU: Fix using incorrect private resource with no allocation
It's possible to have a use of the private resource descriptor or
scratch wave offset registers even though there are no allocated
stack objects. This would result in continuing to use the maximum
number reserved registers. This could go over the number of SGPRs
available on VI, or violate the SGPR limit requested by
the function attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285435
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Nemanja Ivanovic [Fri, 28 Oct 2016 19:38:24 +0000 (19:38 +0000)]
Implement vector count leading/trailing bytes with zero lsb and vector parity
builtins - llvm portion
This patch corresponds to review https://reviews.llvm.org/D26003.
Committing on behalf of Zaara Syeda.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285434
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Teresa Johnson [Fri, 28 Oct 2016 19:36:00 +0000 (19:36 +0000)]
[ThinLTO] Use flags from summary when writing variable summary (NFC)
We already read the flags out of the summary when writing the summary
records for functions and aliases, do the same for variables.
This is an NFC change for now since the flags computed on the fly from
the GlobalValue currently will always match those in the summary
already, but once I send a follow-on patch to set the NoRename flag for
locals in the llvm.used set this becomes a necessary change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285433
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George Burgess IV [Fri, 28 Oct 2016 19:22:46 +0000 (19:22 +0000)]
[MemorySSA] Add const to getClobberingMemoryAccess.
Thanks to bryant for the patch!
Differential Revision: https://reviews.llvm.org/D26086
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285432
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Arnold Schwaighofer [Fri, 28 Oct 2016 19:18:09 +0000 (19:18 +0000)]
Make swift calling convention test specific to armv7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285431
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Sanjay Patel [Fri, 28 Oct 2016 19:08:20 +0000 (19:08 +0000)]
[x86] add tests for missed umin/umax
This is actually a deficiency in ValueTracking's matchSelectPattern(),
but a codegen test is the simplest way to expose the bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285429
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Lang Hames [Fri, 28 Oct 2016 18:24:15 +0000 (18:24 +0000)]
[Error] Unify +Asserts/-Asserts behavior for checked flags in Error/Expected<T>.
(1) Switches to raw pointer and bitmasking operations for Error payload.
(2) Always includes the 'unchecked' bitfield in Expected<T>, even in -Asserts.
(3) Always propagates checked bit status in move-ops for both classes, even in
-Asserts.
This should allow debug programs to link against release libraries without
encountering spurious 'unchecked error' terminations.
Error checks still aren't verified in release mode so this doesn't introduce
any new control flow, but it does require new bit-masking ops in release mode
to preserve the flag values during move ops. I expect the overhead to be
minimal, but if we discover any corner cases where it matters we could fix
this by making flag propagation conditional on a new build option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285426
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Adrian Prantl [Fri, 28 Oct 2016 18:21:39 +0000 (18:21 +0000)]
Move the DWARF attribute constants into Dwarf.def and delete 300 lines of silly code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285425
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Matthias Braun [Fri, 28 Oct 2016 18:05:09 +0000 (18:05 +0000)]
MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285423
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Matthias Braun [Fri, 28 Oct 2016 18:05:05 +0000 (18:05 +0000)]
TargetPassConfig: Move addPass of IPRA RegUsageInfoProp down.
TargetPassConfig::addMachinePasses() does some housekeeping first:
Handling the -print-machineinstrs flag and doing an initial printing
"After Instruction Selection". There is no reason for RegUsageInfoProp
to run before those two steps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285422
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Adrian Prantl [Fri, 28 Oct 2016 17:59:50 +0000 (17:59 +0000)]
Import/update constants from the DWARF 5 public review draft document.
https://reviews.llvm.org/D26051
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285421
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Arnold Schwaighofer [Fri, 28 Oct 2016 17:21:05 +0000 (17:21 +0000)]
More swift calling convention tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285417
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Kostya Serebryany [Fri, 28 Oct 2016 16:55:29 +0000 (16:55 +0000)]
[libFuzzer] a bit more docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285415
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Sanjay Patel [Fri, 28 Oct 2016 16:54:03 +0000 (16:54 +0000)]
[InstCombine] move/add tests for smin/smax folds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285414
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Lang Hames [Fri, 28 Oct 2016 16:52:34 +0000 (16:52 +0000)]
[lli] Pass command line arguments in to the orc-lazy JIT.
This brings the LLI orc-lazy JIT's behavior more closely in-line with LLI's
mcjit bahavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285413
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Krzysztof Parzyszek [Fri, 28 Oct 2016 15:50:22 +0000 (15:50 +0000)]
[Hexagon] Maintain kill flags through splitting in expand-condsets
Do not use LiveIntervals to recalculate kills, because that cannot be
done accurately without implicit uses on predicated instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285409
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Tom Stellard [Fri, 28 Oct 2016 15:32:28 +0000 (15:32 +0000)]
[Loads] Fix crash in is isDereferenceableAndAlignedPointer()
Summary:
We were trying to add APInt values with different bit sizes after
visiting an addrspacecast instruction which changed the bit width
of the pointer.
Reviewers: majnemer, hfinkel
Subscribers: hfinkel, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D24774
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285407
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Teresa Johnson [Fri, 28 Oct 2016 15:30:27 +0000 (15:30 +0000)]
[cmake] Temporarily revert enforcement of minimum GCC version increase
Summary:
This is temporary, until bot that builds public facing LLVM
documentation is upgraded. It reverts only the cmake change in r284497,
but leaves the doc changes in place to preserve intent.
Reviewers: aaron.ballman
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D26078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285406
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Matthew Simpson [Fri, 28 Oct 2016 14:27:45 +0000 (14:27 +0000)]
[LV] Correct misleading comments in test (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285402
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Simon Pilgrim [Fri, 28 Oct 2016 14:07:44 +0000 (14:07 +0000)]
[SelectionDAG] computeKnownBits - early-out if any BUILD_VECTOR element has no known bits
No need to check the remaining elements - no common known bits are available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285399
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Simon Pilgrim [Fri, 28 Oct 2016 13:42:23 +0000 (13:42 +0000)]
[SelectionDAG] Tidyup UDIV computeKnownBits implementation
No need to clear KnownOne2/KnownZero2 bits as the next call to computeKnownBits will overwrite them anyway
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285398
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