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6 years agobuild: add the ability to create a symlink for dsymutil
Saleem Abdulrasool [Wed, 28 Feb 2018 23:00:50 +0000 (23:00 +0000)]
build: add the ability to create a symlink for dsymutil

Add a `LLVM_INSTALL_CCTOOLS_SYMLINKS` to mirror
`LLVM_INSTALL_BINUTILS_SYMLINKS`.  For now, this allows us to create
symlinks for `dsymutil` to `llvm-dsymutil`.  This option is off by
default, but the user can enable it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326381 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Regenerate cmpxchg tests
Simon Pilgrim [Wed, 28 Feb 2018 22:57:23 +0000 (22:57 +0000)]
[X86] Regenerate cmpxchg tests

Add 64-bit cmpxchg8b tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326380 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] simplify code for X * -1.0 --> -X; NFC
Sanjay Patel [Wed, 28 Feb 2018 22:30:04 +0000 (22:30 +0000)]
[InstCombine] simplify code for X * -1.0 --> -X; NFC

I've added random FMF to one of the tests to show those are propagated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326377 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[GlobalOpt] don't change CC of musttail calle(e|r)
Jonas Devlieghere [Wed, 28 Feb 2018 22:28:44 +0000 (22:28 +0000)]
[GlobalOpt] don't change CC of musttail calle(e|r)

When the function has musttail call - its cc is fixed to be equal to the
cc of the musttail callee. In such case (and in the case of the musttail
callee), GlobalOpt should not change the cc to fastcc as it will break
the invariant.

This fixes PR36546

Patch by: Fedor Indutny (indutny)

Differential revision: https://reviews.llvm.org/D43859

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326376 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Lower extract_element from k-registers by bitcasting from v16i1 to i16 and...
Craig Topper [Wed, 28 Feb 2018 22:23:55 +0000 (22:23 +0000)]
[X86] Lower extract_element from k-registers by bitcasting from v16i1 to i16 and extending/truncating.

This is equivalent to what isel was doing anyway but by canonicalizing earlier we can remove some patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326375 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][AVX512] Improve support for signed saturation truncation stores
Simon Pilgrim [Wed, 28 Feb 2018 21:42:19 +0000 (21:42 +0000)]
[X86][AVX512] Improve support for signed saturation truncation stores

Matches what we already manage for unsigned saturation truncation stores

Differential Revision: https://reviews.llvm.org/D43629

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326372 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Implement target feature +reserved-r19
Krzysztof Parzyszek [Wed, 28 Feb 2018 20:29:36 +0000 (20:29 +0000)]
[Hexagon] Implement target feature +reserved-r19

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326364 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] Split the FP constant code out of lookThroughFPExtensions and use nullp...
Craig Topper [Wed, 28 Feb 2018 20:14:34 +0000 (20:14 +0000)]
[InstCombine] Split the FP constant code out of lookThroughFPExtensions and use nullptr as a sentinel

Currently this code's control flow very much assumes that there are no meaningful checks after determining that it's a ConstantFP. So whenever it wants to stop it just does "return V". But V is also the variable name it uses when it wants to return a new value. So 'return V' appears multiple times with different meanings.

This patch just moves all the code into a helper function and returns nullptr when it wants to stop.

I've split this from D43774 while I try to figure out how to best handle the vector case there. But this change by itself at least seemed like a readability improvement.

Differential Revision: https://reviews.llvm.org/D43833

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326361 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoLosen time contraint to accommodate system loads
Lei Huang [Wed, 28 Feb 2018 20:05:24 +0000 (20:05 +0000)]
Losen time contraint to accommodate system loads

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326359 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix llvm-config --system-libs output on FreeBSD and NetBSD
Dimitry Andric [Wed, 28 Feb 2018 20:04:21 +0000 (20:04 +0000)]
Fix llvm-config --system-libs output on FreeBSD and NetBSD

Summary:
For various reasons, CMake's detection mechanism for `backtrace()`
returns an absolute path `/usr/lib/libexecinfo.so` on FreeBSD and
NetBSD.

Since `tools/llvm-config/CMakeLists.txt` only checks if system
libraries start with `-`, this causes `llvm-config --system-libs` to
produce the following incorrect output:

```
-lrt -l/usr/lib/libexecinfo.so -ltinfo -lpthread -lz -lm
```

Fix it by removing the path and the `lib` prefix, to make it look like a
regular short library name, suitable for appending to a `-l` link flag.

This also fixes the `Bindings/Go/go.test` test case, since that always
died with "unable to find library -l/usr/lib/libexecinfo.so".

Reviewers: chandlerc, emaste, joerg, krytarowski

Reviewed By: krytarowski

Subscribers: hans, bdrewery, mgorny, hintonda, llvm-commits

Differential Revision: https://reviews.llvm.org/D42702

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326358 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AMDGPU] added writelane intrinsic
Tim Renouf [Wed, 28 Feb 2018 19:10:32 +0000 (19:10 +0000)]
[AMDGPU] added writelane intrinsic

Summary:
For use by LLPC SPV_AMD_shader_ballot extension.

The v_writelane instruction was already implemented for use by SGPR
spilling, but I had to add an extra dummy operand tied to the
destination, to represent that all lanes except the selected one keep
the old value of the destination register.

.ll test changes were due to schedule changes caused by that new
operand.

Differential Revision: https://reviews.llvm.org/D42838

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326353 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFixed spelling mistake in comments of LLVM Analysis passes
Vedant Kumar [Wed, 28 Feb 2018 19:08:52 +0000 (19:08 +0000)]
Fixed spelling mistake in comments of LLVM Analysis passes

Patch by Reshabh Sharma!

Differential Revision: https://reviews.llvm.org/D43861

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326352 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstrProfiling] Emit the runtime hook when no counters are lowered
Vedant Kumar [Wed, 28 Feb 2018 19:00:08 +0000 (19:00 +0000)]
[InstrProfiling] Emit the runtime hook when no counters are lowered

The API verification tool tapi has difficulty processing frameworks
which enable code coverage, but which have no code. The profile lowering
pass does not emit the runtime hook in this case because no counters are
lowered.

While the hook is not needed for program correctness (the profile
runtime doesn't have to be linked in), it's needed to allow tapi to
validate the exported symbol set of instrumented binaries.

It was not possible to add a workaround in tapi for empty binaries due
to an architectural issue: tapi generates its expected symbol set before
it inspects a binary. Changing that model has a higher cost than simply
forcing llvm to always emit the runtime hook.

rdar://36076904

Differential Revision: https://reviews.llvm.org/D43794

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326350 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[NVPTX] Removed always-true predicates in NVPTX.
Artem Belevich [Wed, 28 Feb 2018 18:51:22 +0000 (18:51 +0000)]
[NVPTX] Removed always-true predicates in NVPTX.

NVPTX stopped supporting GPUs older than sm_20 (Fermi) quite a while back.
Removal of support of pre-Fermi GPUs made a lot of predicates in the NVPTX
backend pointless as they can't ever be false any more.
It's time to retire them. NFC intended.

Differential Revision: https://reviews.llvm.org/D43843

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326349 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[GlobalISel] Print/Parse FailedISel MachineFunction property
Roman Tereshin [Wed, 28 Feb 2018 17:55:45 +0000 (17:55 +0000)]
[GlobalISel] Print/Parse FailedISel MachineFunction property

FailedISel MachineFunction property is part of the CodeGen pipeline
state as much as every other property, notably, Legalized,
RegBankSelected, and Selected. Let's make that part of the state also
serializable / de-serializable, so if GlobalISel aborts on some of the
functions of a large module, but not the others, it could be easily seen
and the state of the pipeline could be maintained through llc's
invocations with -stop-after / -start-after.

To make MIR printable and generally to not to break it too much too
soon, this patch also defers cleaning up the vreg -> LLT map until
ResetMachineFunctionPass.

To make MIR with FailedISel: true also machine verifiable, machine
verifier is changed so it treats a MIR-module as non-regbankselected and
non-selected if there is FailedISel property set.

Reviewers: qcolombet, ab

Reviewed By: dsanders

Subscribers: javed.absar, rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D42877

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326343 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[TLS] use emulated TLS if the target supports only this mode
Chih-Hung Hsieh [Wed, 28 Feb 2018 17:48:55 +0000 (17:48 +0000)]
[TLS] use emulated TLS if the target supports only this mode

Emulated TLS is enabled by llc flag -emulated-tls,
which is passed by clang driver.
When llc is called explicitly or from other drivers like LTO,
missing -emulated-tls flag would generate wrong TLS code for targets
that supports only this mode.
Now use useEmulatedTLS() instead of Options.EmulatedTLS to decide whether
emulated TLS code should be generated.
Unit tests are modified to run with and without the -emulated-tls flag.

Differential Revision: https://reviews.llvm.org/D42999

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326341 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[WebAssembly] Reorder symbol table to match MC order
Nicholas Wilson [Wed, 28 Feb 2018 17:19:48 +0000 (17:19 +0000)]
[WebAssembly] Reorder symbol table to match MC order

This removes a TODO introduced in rL325860

Differential Revision: https://reviews.llvm.org/D43685

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326334 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations
Pablo Barrio [Wed, 28 Feb 2018 17:13:07 +0000 (17:13 +0000)]
[ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations

Summary:
Expressions of the form x < 0 ? 0 :  x; and x < -1 ? -1 : x can be lowered using bit-operations instead of branching or conditional moves

In thumb-mode this results in a two-instruction sequence, a shift followed by a bic or or while in ARM/thumb2 mode that has flexible second operand the shift can be folded into a single bic/or instructions. In most cases this results in smaller code and possibly less branches, and in no case larger than before.

Patch by Martin Svanfeldt

Reviewers: fhahn, pbarrio, rogfer01

Reviewed By: pbarrio, rogfer01

Subscribers: chrib, yroux, eugenis, efriedma, rogfer01, aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D42574

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326333 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] auto-generate complete checks; NFC
Sanjay Patel [Wed, 28 Feb 2018 16:53:45 +0000 (16:53 +0000)]
[InstCombine] auto-generate complete checks; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326331 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] move invariant call out of loop; NFC
Sanjay Patel [Wed, 28 Feb 2018 16:50:51 +0000 (16:50 +0000)]
[InstCombine] move invariant call out of loop; NFC

We really shouldn't need a 2-loop here at all, but that's another cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326330 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] move constant check into foldBinOpIntoSelectOrPhi; NFCI
Sanjay Patel [Wed, 28 Feb 2018 16:36:24 +0000 (16:36 +0000)]
[InstCombine] move constant check into foldBinOpIntoSelectOrPhi; NFCI

Also, rename 'foldOpWithConstantIntoOperand' because that's annoyingly
vague. The constant check is redundant in some cases, but it allows
removing duplication for most of the calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326329 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[DEBUGINFO] Add flag for DWARF2 or less to use sections as references.
Alexey Bataev [Wed, 28 Feb 2018 15:02:59 +0000 (15:02 +0000)]
[DEBUGINFO] Add flag for DWARF2 or less to use sections as references.

Summary:
Some targets does not support labels inside debug sections, but support
references in form `section +|- offset`. Patch adds initial support
for this. Also, this patch disables emission of all additional debug
  sections that may have labels inside of it (like pub sections and
  string tables).

Reviewers: probinson, echristo

Subscribers: JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D43627

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326328 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[WebAssembly] Fix copy-paste error in debugging string
Nicholas Wilson [Wed, 28 Feb 2018 14:03:18 +0000 (14:03 +0000)]
[WebAssembly] Fix copy-paste error in debugging string

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326326 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[mips] Begin reworking instruction predicates for ISAs/encodings (1/N)
Simon Dardis [Wed, 28 Feb 2018 13:02:44 +0000 (13:02 +0000)]
[mips] Begin reworking instruction predicates for ISAs/encodings (1/N)

The MIPS backend has inconsistent usage of instruction predicates
for assembly and code generation. The issue arises from supporting three
encodings, two (MIPS and microMIPS) of which have a near 1:1 instruction
mapping across ISA revisions and a third encoding with a more restricted
set of instructions (MIPS16e).

To enforce consistent usage, each of the ISA_* adjectives has (or will
have) the relevant encoding attached to it along the relevant ISA revision
where the instruction is defined.

Each instruction, pattern or alias will then have the correct ISA adjective
attached to it, and the base instruction description classes will have any
predicates relating to ISA encoding or revision removed.

Pseudo instructions will also be guarded for the encoding or ABI that they are
supported in.

Finally, the hasStandardEncoding() / inMicroMipsMode() / inMips16Mode() methods
of MipsSubtarget will be changed such that only one can be true at any one time.

The result of this is that code generation and assembly will produce the
correct encoding up front, while code generated from pseudo instructions
and other inserted sequences of instructions will be able to rely on the mapping
tables to produce the correct encoding. This should fix numerous bugs where
the result 'happens' to be correct but has edge cases where microMIPS and MIPS
have subtle differences (e.g. microMIPSR6 using 'j', 'jal' instructions.)

This patch starts the process by changing most of the ISA adjectives to make
use of the EncodingPredicate member of PredicateControl. Follow on patches
will annotate instructions with their correct ISA adjective and eliminate
the usage of "let Predicates = [..]", "let AdditionalPredicates = [..]" and
"isCodeGenOnly = 1" in the cases where it was used to control instruction
availability.

Contributions from Nitesh Jain.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D41434

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326322 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[GlobalIsel][X86] Support G_INTTOPTR instruction.
Alexander Ivchenko [Wed, 28 Feb 2018 12:11:53 +0000 (12:11 +0000)]
[GlobalIsel][X86] Support G_INTTOPTR instruction.

Add legalization/selection for x86/x86_64 and
corresponding tests.

Reviewed By: igorb

Differential Revision: https://reviews.llvm.org/D43622

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326320 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix typo. NFC
Xin Tong [Wed, 28 Feb 2018 12:09:53 +0000 (12:09 +0000)]
Fix typo. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326319 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MergeICmp] Fix a bug in MergeICmp that can lead to a block being processed more...
Xin Tong [Wed, 28 Feb 2018 12:08:00 +0000 (12:08 +0000)]
[MergeICmp] Fix a bug in MergeICmp that can lead to a block being processed more than once.

Summary:
Fix a bug in MergeICmp that can lead to a BCECmp block being processed more than once and eventually lead to a broken LLVM module.
The problem is that if the non-constant value is not produced by the last block, the producer will be processed once when the its parent block
is processed and second time when the last block is processed.

We end up having 2 same BCECmpBlock in the merge queue. And eventually lead to a broken LLVM module.

Reviewers: courbet, davide

Reviewed By: courbet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D43825

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326318 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[IR] - Make User construction exception safe
Klaus Kretzschmar [Wed, 28 Feb 2018 11:32:23 +0000 (11:32 +0000)]
[IR] - Make User construction exception safe

There are many instruction ctors that call the setName method of the Value base class, which can throw a bad_alloc exception in OOM situations.
In such situations special User delete operators are called which are not implemented yet.

Example:
 Lets look at the construction of a CallInst instruction during IR generation:

static CallInst *Create(FunctionType *Ty, Value *Func, ArrayRef<Value *> Args, .. ){
...

return new (TotalOps, DescriptorBytes) CallInst(Ty, Func, Args, Bundles, NameStr, InsertBefore);

}

CallInst::CalInst(Value* Func, ...) {
...
Op<-1>() = Func;
....
setName(name); // throws
...
}
Op<-1>() returns a reference to a Use object of the CallInst instruction and the operator= inserts this use object into the UseList of Func.
The same object is removed from that UseList by calling the User::operator delete If the CallInst object is deleted.
Since setName can throw a bad_alloc exception (if LLVM_ENABLE_EXCEPTIONS is switched on), the unwind chain runs into assertions ("Constructor throws?") in
special User::operator deletes operators:

operator delete(void* Usr, unsigned)
operator delete(void* Usr, unsigned, bool)
This situation can be fixed by simlpy calling the User::operator delete(void*) in these unimplemented methods.

To ensure that this additional call succeeds all information that is necessary to calculate the storage pointer from the Usr address
must be restored in the special case that a sublass has changed this information, e.g. GlobalVariable can change the NumberOfOperands.

Reviewd by: rnk

Differential Revision: https://reviews.llvm.org/D42731

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326316 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Dominators] Remove verifyDomTree and add some verifying for Post Dom Trees
David Green [Wed, 28 Feb 2018 11:00:08 +0000 (11:00 +0000)]
[Dominators] Remove verifyDomTree and add some verifying for Post Dom Trees

Removes verifyDomTree, using assert(verify()) everywhere instead, and
changes verify a little to always run IsSameAsFreshTree first in order
to print good output when we find errors. Also adds verifyAnalysis for
PostDomTrees, which will allow checking of PostDomTrees it the same way
we check DomTrees and MachineDomTrees.

Differential Revision: https://reviews.llvm.org/D41298

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326315 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[GlobalIsel][X86] Support G_PTRTOINT instruction.
Alexander Ivchenko [Wed, 28 Feb 2018 09:18:47 +0000 (09:18 +0000)]
[GlobalIsel][X86] Support G_PTRTOINT instruction.

Add legalization/selection for x86/x86_64 and
corresponding tests.

Reviewed By: igorb

Differential Revision: https://reviews.llvm.org/D43617

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326311 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[RISCV] Update two tests after r326208
Alex Bradbury [Wed, 28 Feb 2018 08:20:47 +0000 (08:20 +0000)]
[RISCV] Update two tests after r326208

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326309 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Don't use EXTRACT_ELEMENT from v1i1 with i8/i32 result type when we need to...
Craig Topper [Wed, 28 Feb 2018 08:14:28 +0000 (08:14 +0000)]
[X86] Don't use EXTRACT_ELEMENT from v1i1 with i8/i32 result type when we need to guarantee zeroes in the upper bits of return.

An extract_element where the result type is larger than the scalar element type is semantically an any_extend of from the scalar element type to the result type. If we expect zeroes in the upper bits of the i8/i32 we need to mae sure those zeroes are explicit in the DAG.

For these cases the best way to accomplish this is use an insert_subvector to pad zeroes to the upper bits of the v1i1 first. We extend to either v16i1(for i32) or v8i1(for i8). Then bitcast that to a scalar and finish with a zero_extend up to i32 if necessary. We can't extend past v16i1 because that's the largest mask size on KNL. But isel is smarter enough to know that a zext of a bitcast from v16i1 to i16 can use a KMOVW instruction. The insert_subvectors will be dropped during isel because we can determine that the producing instruction already zeroed the upper bits of the k-register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326308 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Change the masked FPCLASS implementation to use AND instead of OR to combine...
Craig Topper [Wed, 28 Feb 2018 06:19:55 +0000 (06:19 +0000)]
[X86] Change the masked FPCLASS implementation to use AND instead of OR to combine the mask results.

While the description for the instruction does mention OR, its talking about how the individual classification test results are ORed together.

The incoming mask is used as a zeroing write mask. If the bit is 1 the classification is written to the output. The bit is 0 the output is 0. This equivalent to an AND.

Here is pseudocode from the intrinsics guide

FOR j := 0 to 1
        i := j*64
        IF k1[j]
                k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
        ELSE
                k[j] := 0
        FI
ENDFOR
k[MAX:2] := 0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326306 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ARM] Cortex-A57 scheduler fix for ARM backend (missed 16-bit, v8.1/v8.2/v8.3, thumb...
Andrew Zhogin [Wed, 28 Feb 2018 05:53:18 +0000 (05:53 +0000)]
[ARM] Cortex-A57 scheduler fix for ARM backend (missed 16-bit, v8.1/v8.2/v8.3, thumb and pseudo instructions)

Added missed scheduling info for ARM Cortex A57 (AArch32) to have CompleteModel with this checkCompleteness fix: https://reviews.llvm.org/D43235.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D43808

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326304 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SLP] Added new tests and updated existing for jumbled load, NFC.
Mohammad Shahid [Wed, 28 Feb 2018 04:19:34 +0000 (04:19 +0000)]
[SLP] Added new tests and updated existing for jumbled load, NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326303 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[RuntimeDyld][MachO] Support ARM64_RELOC_BRANCH26 for BL instructions by
Lang Hames [Wed, 28 Feb 2018 00:58:21 +0000 (00:58 +0000)]
[RuntimeDyld][MachO] Support ARM64_RELOC_BRANCH26 for BL instructions by
relaxing an assertion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326290 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoupdate_mir_test_checks: Use the regexes from UpdateTestChecks.common
Justin Bogner [Wed, 28 Feb 2018 00:56:24 +0000 (00:56 +0000)]
update_mir_test_checks: Use the regexes from UpdateTestChecks.common

Some of the update_*_test_checks regexes have been moved into a
library, so we might as well use them in update_mir_test_checks.
Also includes minor bugfixes to the regexes that are there so we
don't regress update_mir_test_checks

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326288 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoupdate_mir_test_checks: Drop support for vreg block checks
Justin Bogner [Wed, 28 Feb 2018 00:44:46 +0000 (00:44 +0000)]
update_mir_test_checks: Drop support for vreg block checks

Since vregs are printed in the instruction stream now, checking the
vreg block is always redundant. Remove the temporary feature that
allowed us to do that.

This reverts r316134

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326284 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[WebAssembly] Remove DataSize from linking metadata section
Sam Clegg [Tue, 27 Feb 2018 23:57:37 +0000 (23:57 +0000)]
[WebAssembly] Remove DataSize from linking metadata section

Neither the linker nor the runtime need this information
anymore.  We were originally using this to model BSS size
but the plan is now to use the segment metadata to allow
for BSS segments.

Differential Revision: https://reviews.llvm.org/D41366

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326267 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Recognize more sign-extensions as inputs to 32x32-bit multiply
Krzysztof Parzyszek [Tue, 27 Feb 2018 22:44:41 +0000 (22:44 +0000)]
[Hexagon] Recognize more sign-extensions as inputs to 32x32-bit multiply

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326263 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Pipeliner] Drop memrefs instead of creating ones with size UINT64_MAX
Krzysztof Parzyszek [Tue, 27 Feb 2018 22:40:52 +0000 (22:40 +0000)]
[Pipeliner] Drop memrefs instead of creating ones with size UINT64_MAX

Absence of memory operands is treated as "aliasing everything", so
dropping them is sufficient.

Recommit r326256 with a fixed testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326262 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CodeView] Lower __restrict and other pointer qualifiers correctly
Reid Kleckner [Tue, 27 Feb 2018 22:08:15 +0000 (22:08 +0000)]
[CodeView] Lower __restrict and other pointer qualifiers correctly

Qualifiers on a pointer or reference type may apply to either the
pointee or the pointer itself. Consider 'const char *' and 'char *
const'. In the first example, the pointee data may not be modified
without casts, and in the second example, the pointer may not be updated
to point to new data.

In the general case, qualifiers are applied to types with LF_MODIFIER
records, which support the usual const and volatile qualifiers as well
as the __unaligned extension qualifier.

However, LF_POINTER records, which are used for pointers, references,
and member pointers, have flags for qualifiers applying to the
*pointer*. In fact, this is the only way to represent the restrict
qualifier, which can only apply to pointers, and cannot qualify regular
data types.

This patch causes LLVM to correctly fold 'const' and 'volatile' pointer
qualifiers into the pointer record, as well as adding support for
'__restrict' qualifiers in the same place.

Based on a patch from Aaron Smith

Differential Revision: https://reviews.llvm.org/D43060

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326260 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert "[Pipeliner] Drop memrefs instead of creating ones with size UINT64_MAX"
Krzysztof Parzyszek [Tue, 27 Feb 2018 22:07:38 +0000 (22:07 +0000)]
Revert "[Pipeliner] Drop memrefs instead of creating ones with size UINT64_MAX"

This reverts r326256. One testcase needs to be updated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326259 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Pipeliner] Drop memrefs instead of creating ones with size UINT64_MAX
Krzysztof Parzyszek [Tue, 27 Feb 2018 22:00:32 +0000 (22:00 +0000)]
[Pipeliner] Drop memrefs instead of creating ones with size UINT64_MAX

Absence of memory operands is treated as "aliasing everything", so
dropping them is sufficient.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326256 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AsmPrinter] Handle qualified unnamed types in CodeView printer
Shoaib Meenai [Tue, 27 Feb 2018 21:48:41 +0000 (21:48 +0000)]
[AsmPrinter] Handle qualified unnamed types in CodeView printer

When attempting to compile the following Objective-C++ code with
CodeView debug info:

  void (^b)(void) = []() {};

The generated debug metadata contains a structure like the following:

  !43 = !DICompositeType(tag: DW_TAG_structure_type, name: "__block_literal_1", scope: !6, file: !6, line: 1, size: 168, elements: !44)
  !44 = !{!45, !46, !47, !48, !49, !52}
  ...
  !52 = !DIDerivedType(tag: DW_TAG_member, scope: !6, file: !6, line: 1, baseType: !53, size: 8, offset: 160, flags: DIFlagPublic)
  !53 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !54)
  !54 = !DICompositeType(tag: DW_TAG_class_type, file: !6, line: 1, flags: DIFlagFwdDecl)

Note that the member node (!52) is unnamed, but rather than pointing to
a DICompositeType directly, it points to a DIDerivedType with tag
DW_TAG_const_type, which then points to the DICompositeType. However,
the CodeView assembly printer currently assumes that the base type for
an unnamed member will always be a DICompositeType, and attempts to
perform that cast, which triggers an assertion failure, since in this
case the base type is actually a DIDerivedType, not a DICompositeType
(and we would have to get the base type of the DIDerivedType to reach
the DICompositeType). I think the debug metadata being generated by the
frontend is correct (or at least plausible), and the CodeView printer
needs to handle this case.

This patch teaches the CodeView printer to unwrap any qualifier types.
The qualifiers are just dropped for now. Ideally, they would be applied
to the added indirect members instead, but this occurs infrequently
enough that adding the logic to handle the qualifiers correctly isn't
worth it for now. A FIXME is added to note this.

Additionally, Reid pointed out that the underlying assumption that an
unnamed member must be a composite type is itself incorrect and may not
hold for all frontends. Therefore, after all qualifiers have been
stripped, check if the resulting type is in fact a DICompositeType and
just return if it isn't, rather than assuming the type and crashing if
that assumption is violated.

Differential Revision: https://reviews.llvm.org/D43803

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326255 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[codeview] Remove unused variable
Reid Kleckner [Tue, 27 Feb 2018 21:46:40 +0000 (21:46 +0000)]
[codeview] Remove unused variable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326253 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU: Add fast fmaf feature to gfx702
Konstantin Zhuravlyov [Tue, 27 Feb 2018 21:46:15 +0000 (21:46 +0000)]
AMDGPU: Add fast fmaf feature to gfx702

Differential Revision: https://reviews.llvm.org/D43790

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326252 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-cvtres] Update the help test after SVN r326244.
Martin Storsjo [Tue, 27 Feb 2018 21:11:03 +0000 (21:11 +0000)]
[llvm-cvtres] Update the help test after SVN r326244.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326248 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agollvm-cvtres: Mention ARM64 as a supported machine type in the help text. NFC.
Martin Storsjo [Tue, 27 Feb 2018 20:44:33 +0000 (20:44 +0000)]
llvm-cvtres: Mention ARM64 as a supported machine type in the help text. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326244 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstSimplify] add tests for FP with undef operand; NFC
Sanjay Patel [Tue, 27 Feb 2018 20:17:18 +0000 (20:17 +0000)]
[InstSimplify] add tests for FP with undef operand; NFC

Are any of these correct?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326241 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ValueTracking] Teach cannotBeOrderedLessThanZeroImpl to look through ExtractElement.
Craig Topper [Tue, 27 Feb 2018 19:53:45 +0000 (19:53 +0000)]
[ValueTracking] Teach cannotBeOrderedLessThanZeroImpl to look through ExtractElement.

This is similar to what's done in computeKnownBits and computeSignBits. Don't do anything fancy just collect information valid for any element.

Differential Revision: https://reviews.llvm.org/D43789

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326237 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ARM] Another f16 litpool fix
Sjoerd Meijer [Tue, 27 Feb 2018 19:26:02 +0000 (19:26 +0000)]
[ARM] Another f16 litpool fix

We were always setting the block alignment to 2 bytes in Thumb mode
and 4-bytes in ARM mode (r325754, and r325012), but this could cause
reducing the block alignment when it already had been aligned (e.g.
in Thumb mode when the block is a CPE that was already 4-byte aligned).

Patch by Momchil Velikov, I've only added a test.

Differential Revision: https://reviews.llvm.org/D43777

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326232 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[dsymutil] Skip DW_AT_sibling attributes.
Jonas Devlieghere [Tue, 27 Feb 2018 19:24:36 +0000 (19:24 +0000)]
[dsymutil] Skip DW_AT_sibling attributes.

Following DW_AT_sibling attributes completely defeats the pruning pass.
Although clang doesn't generate the DW_AT_sibling attribute we should
still handle it correctly.

Differential revision: https://reviews.llvm.org/D43439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326231 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert r326225 "[X86] Move the load folding tables to a separate .inc file"
Craig Topper [Tue, 27 Feb 2018 19:15:40 +0000 (19:15 +0000)]
Revert r326225 "[X86] Move the load folding tables to a separate .inc file"

The bots don't seem to like the .inc file. I must be missing some cmake incantation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326228 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR.
Peter Collingbourne [Tue, 27 Feb 2018 19:00:59 +0000 (19:00 +0000)]
ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR.

Differential Revision: https://reviews.llvm.org/D43807

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326226 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Move the load folding tables to a separate .inc file
Craig Topper [Tue, 27 Feb 2018 18:46:11 +0000 (18:46 +0000)]
[X86] Move the load folding tables to a separate .inc file

These tables add 3000 lines to X86InstrInfo.cpp. And if we ever manage to auto generate them they'll be a separate file anyway.

Differential Revision: https://reviews.llvm.org/D43806

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326225 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ARM] add loop vectorizer test based on 482.sphinx3 from SPEC2006; NFC
Sanjay Patel [Tue, 27 Feb 2018 18:33:24 +0000 (18:33 +0000)]
[ARM] add loop vectorizer test based on 482.sphinx3 from SPEC2006; NFC

This is a slight reduction of one of the benchmarks
that suffered with D43079. Cost model changes should
not cause this test to remain scalarized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326221 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Add patterns for compares of i1 values
Krzysztof Parzyszek [Tue, 27 Feb 2018 18:31:46 +0000 (18:31 +0000)]
[Hexagon] Add patterns for compares of i1 values

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326220 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AArch64] add SLP test based on TSVC; NFC
Sanjay Patel [Tue, 27 Feb 2018 18:06:15 +0000 (18:06 +0000)]
[AArch64] add SLP test based on TSVC; NFC

This is a slight reduction of one of the benchmarks
that suffered with D43079. Cost model changes should
not cause this test to remain scalarized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326217 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[GISel]: Print more fallback information when aborting
Aditya Nandakumar [Tue, 27 Feb 2018 18:04:23 +0000 (18:04 +0000)]
[GISel]: Print more fallback information when aborting

Currently when abort is enabled, we get a diagnostic saying "Fallback
path used .... " and the program terminates. To actually figure out what
the reason is, we need to run again with another verbose argument
"-pass-remarks-missed=gisel". Instead, when we are going to abort,
we might as well print expensive remarks.

https://reviews.llvm.org/D43796

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326215 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRe-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
Geoff Berry [Tue, 27 Feb 2018 16:59:10 +0000 (16:59 +0000)]
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"

Re-enable commit r323991 now that r325931 has been committed to make
MachineOperand::isRenamable() check more conservative w.r.t. code
changes and opt-in on a per-target basis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326208 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][AVX] combineLoopMAddPattern - support 256-bit cases on AVX1 via SplitBinaryOpsA...
Simon Pilgrim [Tue, 27 Feb 2018 12:20:37 +0000 (12:20 +0000)]
[X86][AVX] combineLoopMAddPattern - support 256-bit cases on AVX1 via SplitBinaryOpsAndApply

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326189 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoMake the LLParser accept call instructions of variables in the program AS
Alexander Richardson [Tue, 27 Feb 2018 11:15:11 +0000 (11:15 +0000)]
Make the LLParser accept call instructions of variables in the program AS

Summary:
Since r325479 the DataLayout includes a program address space. However, it
is not possible to use `call %foo` if foo is a `i8(...) addrspace(200)` and
the DataLayout specifies address space 200 as the address space for functions.
With this change the IR parser will still accept variables in the program
address space as well as address space 0 for call and invoke functions.

Reviewers: pcc, arsenm, bjope, dylanmckay, theraven

Reviewed By: dylanmckay

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43645

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326188 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoDon't output bitcode to stdout in 2002-07-31-SlashInString.ll test
Alexander Richardson [Tue, 27 Feb 2018 11:15:05 +0000 (11:15 +0000)]
Don't output bitcode to stdout in 2002-07-31-SlashInString.ll test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326187 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[dsymutil][test] Add PowerPC test
Jonas Devlieghere [Tue, 27 Feb 2018 10:28:43 +0000 (10:28 +0000)]
[dsymutil][test] Add PowerPC test

Add test that verifies that we don't follow DWARF values with a
reference form class, such as DW_AT_sibling.

Since clang doesn't generate the latter attribute, we added a PowerPC
test generated on an old PowerBook G4. (Thanks Adrian!)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326183 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ADT] Recognize ppc as valid architecture in target triple.
Jonas Devlieghere [Tue, 27 Feb 2018 10:09:58 +0000 (10:09 +0000)]
[ADT] Recognize ppc as valid architecture in target triple.

Until this patch, only `powerpc` and `ppc32` were recognized as valid
PowerPC 32-bit architectures in a target triple. This was incompatible
with the triple `ppc-apple-darwin` as returned for libObject. I found
out about this when working on a test case using a binary generated on
an old PowerBook G4.

We had the choice of either fix this in the Mach-O object parser or
in the Triple implementation. I chose the latter because it feels like
the most canonical place.

Differential revision: https://reviews.llvm.org/D43760

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326182 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[NewGVN] Update phi-of-ops def block when updating existing ValuePHI.
Florian Hahn [Tue, 27 Feb 2018 09:34:51 +0000 (09:34 +0000)]
[NewGVN] Update phi-of-ops def block when updating existing ValuePHI.

In case we update a ValuePHI node created earlier, we could update it
based on a different OpPHI which could be in a different block.
We need to update the TempToBlock mapping reflecting the new block,
otherwise we would end up placing the new phi node in a wrong block.

This problem is exposed by the test case in
https://bugs.llvm.org/show_bug.cgi?id=36504.

This patch fixes a slightly simpler problem than in the bug report. In
the bug's re-producer, the additional problem is that we are re-using a
ValuePHI node with to few incoming values for the new OpPHI. If this
patch makes sense, I will follow it up with a patch that creates a new
PHI node if the existing PHI node has a different number of incoming
values.

Reviewers: davide, dberlin

Reviewed By: dberlin

Differential Revision: https://reviews.llvm.org/D43770

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326181 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SystemZ] Make sure SelectCode() is not called on a target opcode.
Jonas Paulsson [Tue, 27 Feb 2018 07:53:23 +0000 (07:53 +0000)]
[SystemZ]  Make sure SelectCode() is not called on a target opcode.

Since getNode() might not always return the requsted opcode, for instance if
called with (ISD::AND, -1) arguments, there should be a check so that
SelectCode() is only called when appropriate.

Review: Ulrich Weigand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326178 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MemorySSA] Invalidate def caches on deletion
George Burgess IV [Tue, 27 Feb 2018 07:20:49 +0000 (07:20 +0000)]
[MemorySSA] Invalidate def caches on deletion

The only cases I can come up with where this invalidation needs to
happen is when there's a deletion somewhere. If we find more creative
test-cases, we can probably go with another approach mentioned on
PR36529.

Fixes PR36529.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326177 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MemorySSA] Call the correct dtors
George Burgess IV [Tue, 27 Feb 2018 06:43:19 +0000 (06:43 +0000)]
[MemorySSA] Call the correct dtors

It appears that there were many cases where we were directly (through
templates) calling the dtor of MemoryAccess, which is conceptually an
abstract class.

This hasn't been a problem, since the data members of all of the
subclasses of MemoryAccess have been POD. I'm planning on changing that.
:)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326175 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SCEV] Cleanup SCEVInitRewriter. NFC.
Serguei Katkov [Tue, 27 Feb 2018 06:39:31 +0000 (06:39 +0000)]
[SCEV] Cleanup SCEVInitRewriter. NFC.

Set default value for IgnoreOtherLoops of SCEVInitRewriter::rewrite to true
to be consistent with SCEVPostIncRewriter which does not have this parameter
but behaves as it would be true.

This is follow up for rL326067.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326174 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Simplify if condition. NFC
Craig Topper [Tue, 27 Feb 2018 06:00:38 +0000 (06:00 +0000)]
[X86] Simplify if condition. NFC

SSE2 implies SSE1 and we already covered f32 in the SSE1 check so we don't need to check f32 in the SSE2 check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326170 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoMake test agnostic to cost model
Adam Nemet [Tue, 27 Feb 2018 05:41:16 +0000 (05:41 +0000)]
Make test agnostic to cost model

This was causing bot failures on greendragon

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326169 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Replace an impossible if condition with an assert.
Craig Topper [Tue, 27 Feb 2018 03:50:00 +0000 (03:50 +0000)]
[X86] Replace an impossible if condition with an assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326167 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix r326154 buildbots test fail
Evgeny Stupachenko [Tue, 27 Feb 2018 01:33:11 +0000 (01:33 +0000)]
Fix r326154 buildbots test fail

Summary:

Add specific mtriples to tests added in r326154.

From: Evgeny Stupachenko <evstupac@gmail.com>
                         <evgeny.v.stupachenko@intel.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326158 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix PR36032, PR35432
Evgeny Stupachenko [Tue, 27 Feb 2018 00:17:31 +0000 (00:17 +0000)]
Fix PR36032, PR35432

Summary:

The change fix an assert fail at ScalarEvolutionExpander.cpp:
  assert(ExitCount != SE.getCouldNotCompute() && "Invalid loop count");

Reviewers: sbaranga

Differential Revision: http://reviews.llvm.org/D42604

From: Evgeny Stupachenko <evstupac@gmail.com>
                         <evgeny.v.stupachenko@intel.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326154 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SelectionDAG] Remove code from PromoteIntRes_CONCAT_VECTORS that was added in r32067...
Craig Topper [Tue, 27 Feb 2018 00:07:24 +0000 (00:07 +0000)]
[SelectionDAG] Remove code from PromoteIntRes_CONCAT_VECTORS that was added in r320674 to help X86.

AVX512 used to promote v32i1 to v32i8 during legalization when BWI was disabled. So this code was added to improve legalization of v32i1 concat_vectors of v16i1 by extending the v16i1 to v16i8 to avoid scalarization.

X86 has since switched to legalizing v32i1 by splitting to v16i1 instead. This has rendered this code unnecessary and its no longer exercised.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326153 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine, InstSimplify] add tests with undef elements in constant FP vectors...
Sanjay Patel [Mon, 26 Feb 2018 23:23:02 +0000 (23:23 +0000)]
[InstCombine, InstSimplify] add tests with undef elements in constant FP vectors; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326148 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AArch64] Harden test cases
Evandro Menezes [Mon, 26 Feb 2018 23:19:25 +0000 (23:19 +0000)]
[AArch64] Harden test cases

NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326147 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[GISel]: Don't assert when constraining RegisterOperands which are uses.
Aditya Nandakumar [Mon, 26 Feb 2018 22:56:21 +0000 (22:56 +0000)]
[GISel]: Don't assert when constraining RegisterOperands which are uses.

Currently we assert that only non target specific opcodes can have
missing RegisterClass constraints in the MCDesc. The backend can have
instructions with register operands but don't have RegisterClass
constraints (say using unknown_class) in which case the instruction
defining the register will constrain it.
Change the assert to only fire if a def has no regclass.

https://reviews.llvm.org/D43409

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326142 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ValueTracking] Teach cannotBeOrderedLessThanZeroImpl to handle vector constants.
Craig Topper [Mon, 26 Feb 2018 22:33:17 +0000 (22:33 +0000)]
[ValueTracking] Teach cannotBeOrderedLessThanZeroImpl to handle vector constants.

Summary: This allows vector fabs to be removed in more cases.

Reviewers: spatel, arsenm, RKSimon

Reviewed By: spatel

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43739

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326138 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][SSE] Reduce FADD/FSUB/FMUL costs on later targets (PR36280)
Simon Pilgrim [Mon, 26 Feb 2018 22:10:17 +0000 (22:10 +0000)]
[X86][SSE] Reduce FADD/FSUB/FMUL costs on later targets (PR36280)

Agner's tables indicate that for SSE42+ targets (Core2 and later) we can reduce the FADD/FSUB/FMUL costs down to 1, which should fix the Himeno benchmark.

Note: the AVX512 FDIV costs look rather dodgy, but this isn't part of this patch.

Differential Revision: https://reviews.llvm.org/D43733

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326133 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[DebugInfo] Remove target-specific instructions in test
Scott Linder [Mon, 26 Feb 2018 21:21:19 +0000 (21:21 +0000)]
[DebugInfo] Remove target-specific instructions in test

This AsmParser test is target-agnostic, but contained some target-specific
instructions, which broke on SystemZ.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326129 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Add constant folding to combineMOVMSK.
Craig Topper [Mon, 26 Feb 2018 21:17:33 +0000 (21:17 +0000)]
[X86] Add constant folding to combineMOVMSK.

There's still some shortcoming in our ability to combine binops of constants with different sizes separated by an extend. I'll try to look at that next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326128 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[opt-viewer] Kill parser processes before moving onto rendering
Adam Nemet [Mon, 26 Feb 2018 21:15:51 +0000 (21:15 +0000)]
[opt-viewer] Kill parser processes before moving onto rendering

The main benefit is that they release the memory they were holding onto.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326127 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoopt-diff: Support splitting to multiple output files
Adam Nemet [Mon, 26 Feb 2018 21:15:51 +0000 (21:15 +0000)]
opt-diff: Support splitting to multiple output files

When reading the resulting files back with opt-viewer, they will be parsed in
parallel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326126 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[opt-viewer] Set title for the source pages
Adam Nemet [Mon, 26 Feb 2018 21:15:50 +0000 (21:15 +0000)]
[opt-viewer] Set title for the source pages

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326125 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoopt-viewer: also find thinlto opt.yaml files
Adam Nemet [Mon, 26 Feb 2018 21:15:49 +0000 (21:15 +0000)]
opt-viewer: also find thinlto opt.yaml files

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326124 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoopt-viewer: output index first
Adam Nemet [Mon, 26 Feb 2018 21:15:47 +0000 (21:15 +0000)]
opt-viewer: output index first

One can start looking at the index while the pages are still generating

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326123 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Add a custom legalization for (i16 (bitcast v16i1)) and (i32 (bitcast v32i1...
Craig Topper [Mon, 26 Feb 2018 20:32:27 +0000 (20:32 +0000)]
[X86] Add a custom legalization for (i16 (bitcast v16i1)) and (i32 (bitcast v32i1)) without AVX512 to prevent scalarization

Summary:
We have an early DAG combine to turn these patterns into MOVMSK, but that combine doesn't work if the vXi1 type has more elements than the widest legal vXi8 type. Type legalization will eventually split it down to v16i1 or v32i1 and then the bitcast gets legalized to a truncstore and a scalar load. The truncstore will get lowered to a series of extracts and bit math.

This patch adds a custom legalization to use a sign extend and MOVMSK instead. This prevents the eventual scalarization.

Reviewers: spatel, RKSimon, zvi

Reviewed By: RKSimon

Subscribers: mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D43593

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326119 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SLP] Added new test + fixed some checks, NFC.
Alexey Bataev [Mon, 26 Feb 2018 20:01:24 +0000 (20:01 +0000)]
[SLP] Added new test + fixed some checks, NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326117 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] Add test cases with vector constants to fpextend.ll
Craig Topper [Mon, 26 Feb 2018 19:36:37 +0000 (19:36 +0000)]
[InstCombine] Add test cases with vector constants to fpextend.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326115 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] Switch to using FileCheck instead of grep. Auto-generate checks. NFC
Craig Topper [Mon, 26 Feb 2018 19:36:36 +0000 (19:36 +0000)]
[InstCombine] Switch to using FileCheck instead of grep. Auto-generate checks. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326114 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ADT] Simplify and optimize StringSwitch
David Zarzycki [Mon, 26 Feb 2018 18:41:26 +0000 (18:41 +0000)]
[ADT] Simplify and optimize StringSwitch

This change improves incremental rebuild performance on dual Xeon 8168
machines by 54%. This change also improves run time code gen by not
forcing the case values to be lvalues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326109 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LTO] Support filtering by hotness threshold
Adam Nemet [Mon, 26 Feb 2018 18:37:45 +0000 (18:37 +0000)]
[LTO] Support filtering by hotness threshold

This wires up -pass-remarks-hotness-threshold to LTO and ThinLTO.

Next is to change the clang driver to pass this
with -fdiagnostics-hotness-threshold.

Differential Revision: https://reviews.llvm.org/D41465

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326107 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][AVX] createPSADBW - support 256-bit cases on AVX1 via SplitBinaryOpsAndApply
Simon Pilgrim [Mon, 26 Feb 2018 18:17:25 +0000 (18:17 +0000)]
[X86][AVX] createPSADBW - support 256-bit cases on AVX1 via SplitBinaryOpsAndApply

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326104 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU/GlobalISel: Make f64 constants legal
Matt Arsenault [Mon, 26 Feb 2018 17:20:43 +0000 (17:20 +0000)]
AMDGPU/GlobalISel: Make f64 constants legal

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326101 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] allow fdiv folds with less than fully 'fast' ops
Sanjay Patel [Mon, 26 Feb 2018 16:02:45 +0000 (16:02 +0000)]
[InstCombine] allow fdiv folds with less than fully 'fast' ops

Note: gcc appears to allow this fold with -freciprocal-math alone,
but clang/llvm require more than that with this patch. The wording
in the definitions seems fuzzy enough that it could go either way,
but we'll err on the conservative side of FMF interpretation.

This patch also changes the newly created fmul to have FMF propagated
by the last fdiv rather than intersecting the FMF of the fdivs. This
matches the behavior of other folds near here. The new fmul is only
used to produce an intermediate op for the final fdiv result, so it
shouldn't be any stricter than that result. The previous behavior
could result in dropping FMF via other folds in instcombine or CSE.

Differential Revision: https://reviews.llvm.org/D43398

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326098 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][AVX] Add AVX1 PSAD tests
Simon Pilgrim [Mon, 26 Feb 2018 15:55:25 +0000 (15:55 +0000)]
[X86][AVX] Add AVX1 PSAD tests

Cleanup check-prefixes to share more AVX/AVX512 codegen checks

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326097 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert r326092: [gtest] Add PrintTo overload for StringRef.
Ilya Biryukov [Mon, 26 Feb 2018 15:54:59 +0000 (15:54 +0000)]
Revert r326092: [gtest] Add PrintTo overload for StringRef.

It seems to break the following buildbot:
http://lab.llvm.org:8011/builders/sanitizer-windows/builds/24729

Will resubmit after investigating and fixing it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326096 91177308-0d34-0410-b5e6-96231b3b80d8