OSDN Git Service

android-x86/external-llvm.git
7 years ago[APInt] Fix typo in comment. NFC
Craig Topper [Sat, 13 May 2017 00:35:30 +0000 (00:35 +0000)]
[APInt] Fix typo in comment. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302974 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AVR] When lowering Select8/Select16, put newly generated MBBs in the same spot
Dylan McKay [Sat, 13 May 2017 00:22:34 +0000 (00:22 +0000)]
[AVR] When lowering Select8/Select16, put newly generated MBBs in the same spot

Contributed by Dr. Gergő Érdi.

Fixes a bug.

Raised from (https://github.com/avr-rust/rust/issues/49).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302973 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAA: Use generic intrinsics for tests instead of target specific ones
Justin Bogner [Sat, 13 May 2017 00:12:52 +0000 (00:12 +0000)]
AA: Use generic intrinsics for tests instead of target specific ones

Update a few tests to use llvm.masked.load/store instead of arm neon
vector loads and stores, and move the tests that are actually specific
to those arm intrinsics to their own files. This lets us mark the
tests that use target specific intrinsics as requiring those targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302972 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CodeView] Silence some -Wsign-compare warnings
Justin Bogner [Sat, 13 May 2017 00:11:39 +0000 (00:11 +0000)]
[CodeView] Silence some -Wsign-compare warnings

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302971 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AVR] Remove an unused variable
Dylan McKay [Sat, 13 May 2017 00:00:26 +0000 (00:00 +0000)]
[AVR] Remove an unused variable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302970 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PartialInlining] Profile based cost analysis
Xinliang David Li [Fri, 12 May 2017 23:41:43 +0000 (23:41 +0000)]
[PartialInlining] Profile based cost analysis

Implemented frequency based cost/saving analysis
and related options.

The pass is now in a state ready to be turne on
in the pipeline (in follow up).

Differential Revision: http://reviews.llvm.org/D32783

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302967 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[GISel]: Add a getConstantFPVRegVal utility
Aditya Nandakumar [Fri, 12 May 2017 22:54:52 +0000 (22:54 +0000)]
[GISel]: Add a getConstantFPVRegVal utility

This might be useful across various GISel Passes

https://reviews.llvm.org/D33051

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302964 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[GISel]: Fix undefined behavior while accessing DefaultAction map
Aditya Nandakumar [Fri, 12 May 2017 22:43:58 +0000 (22:43 +0000)]
[GISel]: Fix undefined behavior while accessing DefaultAction map

We end up dereferencing the end iterator here when the Aspect doesn't exist in the DefaultAction map.
Change the API to return Optional<LLT> and return None when not found.
Also update the callers to handle the None case

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302963 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[IR] Fix some Clang-tidy modernize-use-using warnings; other minor fixes (NFC).
Eugene Zelenko [Fri, 12 May 2017 22:25:07 +0000 (22:25 +0000)]
[IR] Fix some Clang-tidy modernize-use-using warnings; other minor fixes (NFC).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302961 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[TLI] Add mapping for various '__<func>_finite' forms of the math routines to SVML...
Andrew Kaylor [Fri, 12 May 2017 22:11:26 +0000 (22:11 +0000)]
[TLI] Add mapping for various '__<func>_finite' forms of the math routines to SVML routines

Patch by Chris Chrulski

Differential Revision: https://reviews.llvm.org/D31789

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302957 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ConstantFolding] Add folding for various math '__<func>_finite' routines generated...
Andrew Kaylor [Fri, 12 May 2017 22:11:20 +0000 (22:11 +0000)]
[ConstantFolding] Add folding for various math '__<func>_finite' routines generated from -ffast-math

Patch by Chris Chrulski

Differential Revision: https://reviews.llvm.org/D31788

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302956 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[TLI] Add declarations for various math header file routines from math-finite.h that...
Andrew Kaylor [Fri, 12 May 2017 22:11:12 +0000 (22:11 +0000)]
[TLI] Add declarations for various math header file routines from math-finite.h that create '__<func>_finite as functions

Patch by Chris Chrulski

Differential Revision: https://reviews.llvm.org/D31787

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302955 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[APInt] Add early outs for a division by 1 to udiv/urem/udivrem
Craig Topper [Fri, 12 May 2017 21:45:50 +0000 (21:45 +0000)]
[APInt] Add early outs for a division by 1 to udiv/urem/udivrem

We already counted the number of bits in the RHS so its pretty cheap to just check if the RHS is 1.

Differential Revision: https://reviews.llvm.org/D33154

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302953 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[APInt] In udivrem, remember the bit width in a local variable so we don't reread...
Craig Topper [Fri, 12 May 2017 21:45:44 +0000 (21:45 +0000)]
[APInt] In udivrem, remember the bit width in a local variable so we don't reread it from the LHS which might be aliased with Quotient or Remainder.

This helped the compiler generate better code for the single word case. It was able to remember that the bit width was still a single word when it created the Remainder APInt and not create code for it possibly being multiword.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302952 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLTO: Don't verify modules twice in verifyMergedModuleOnce
Adrian Prantl [Fri, 12 May 2017 21:38:32 +0000 (21:38 +0000)]
LTO: Don't verify modules twice in verifyMergedModuleOnce

Differential Revision: https://reviews.llvm.org/D33140

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302951 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Doc] Document "Splat" in the lexicon
Sanjay Patel [Fri, 12 May 2017 21:30:31 +0000 (21:30 +0000)]
[Doc] Document "Splat" in the lexicon

Patch by Wei-Ren Chen (陳韋任)!

Differential Revision: https://reviews.llvm.org/D32964

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302950 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] add vector tests for demanded bits; NFC
Sanjay Patel [Fri, 12 May 2017 20:53:48 +0000 (20:53 +0000)]
[x86] add vector tests for demanded bits; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302949 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Don't promote to vector if the load/store is volatile.
Changpeng Fang [Fri, 12 May 2017 20:31:12 +0000 (20:31 +0000)]
AMDGPU/SI: Don't promote to vector if the load/store is volatile.

Summary:
  We should not change volatile loads/stores in promoting alloca to vector.

Reviewers:
  arsenm

Differential Revision:
  http://reviews.llvm.org/D33107

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302943 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)
Simon Pilgrim [Fri, 12 May 2017 19:56:43 +0000 (19:56 +0000)]
[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)

This fixes 47 of the 75 NVPTX '-verify-machineinstrs with EXPENSIVE_CHECKS' errors in PR32146.

Differential Revision: https://reviews.llvm.org/D33147

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302942 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove ignore-empty-index-file option
Teresa Johnson [Fri, 12 May 2017 19:32:11 +0000 (19:32 +0000)]
Remove ignore-empty-index-file option

Summary:
As discussed in the D32195 review thread and on IRC, remove this option
and replace with parameter, which will be set to true when invoked
from clang in the context of a ThinLTO distributed backend.

Reviewers: pcc

Subscribers: mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D33133

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302939 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd LiveRangeShrink pass to shrink live range within BB.
Dehao Chen [Fri, 12 May 2017 19:29:27 +0000 (19:29 +0000)]
Add LiveRangeShrink pass to shrink live range within BB.

Summary: LiveRangeShrink pass moves instruction right after the definition with the same BB if the instruction and its operands all have more than one use. This pass is inexpensive and guarantees optimal live-range within BB.

Reviewers: davidxl, wmi, hfinkel, MatzeB, andreadb

Reviewed By: MatzeB, andreadb

Subscribers: hiraditya, jyknight, sanjoy, skatkov, gberry, jholewinski, qcolombet, javed.absar, krytarowski, atrick, spatel, RKSimon, andreadb, MatzeB, mehdi_amini, mgorny, efriedma, davide, dberlin, llvm-commits

Differential Revision: https://reviews.llvm.org/D32563

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302938 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PPC] Move the combine "a << (b % (sizeof(a) * 8)) -> (PPCshl a, b)" to the backend...
Tim Shen [Fri, 12 May 2017 19:25:37 +0000 (19:25 +0000)]
[PPC] Move the combine "a << (b % (sizeof(a) * 8)) -> (PPCshl a, b)" to the backend. NFC.

Summary:
Eli pointed out that it's unsafe to combine the shifts to ISD::SHL etc.,
because those are not defined for b > sizeof(a) * 8, even after some of
the combiners run.

However, PPCISD::SHL defines that behavior (as the instructions themselves).
Move the combination to the backend.

The tests in shift_mask.ll still pass.

Reviewers: echristo, hfinkel, efriedma, iteratee

Subscribers: nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D33076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302937 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CodeView] Add a random access type visitor.
Zachary Turner [Fri, 12 May 2017 19:18:12 +0000 (19:18 +0000)]
[CodeView] Add a random access type visitor.

This adds a visitor that is capable of accessing type
records randomly and caching intermediate results that it
learns about during partial linear scans.  This yields
amortized O(1) access to a type stream even though type
streams cannot normally be indexed.

Differential Revision: https://reviews.llvm.org/D33009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302936 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64][Falkor] Refine modeling of multiply accumulate forwarding.
Geoff Berry [Fri, 12 May 2017 18:57:10 +0000 (18:57 +0000)]
[AArch64][Falkor] Refine modeling of multiply accumulate forwarding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302933 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[APInt] Add an assert to check for divide by zero in udivrem. NFC
Craig Topper [Fri, 12 May 2017 18:19:01 +0000 (18:19 +0000)]
[APInt] Add an assert to check for divide by zero in udivrem. NFC

udiv and urem already had the same assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302931 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[APInt] Remove unnecessary checks of rhsWords==1 with lhsWords==1 from udiv and udivr...
Craig Topper [Fri, 12 May 2017 18:18:57 +0000 (18:18 +0000)]
[APInt] Remove unnecessary checks of rhsWords==1 with lhsWords==1 from udiv and udivrem. NFC

At this point in the code rhsWords is guaranteed to be non-zero and less than or equal to lhsWords. So if lhsWords is 1, rhsWords must also be 1. urem alread had the check removed so this makes all 3 consistent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302930 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Add lit.local.cfg to disable global-isel tests when global-isel is disabled
Tom Stellard [Fri, 12 May 2017 17:59:30 +0000 (17:59 +0000)]
AMDGPU: Add lit.local.cfg to disable global-isel tests when global-isel is disabled

This should fix bots broken by r302919.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302928 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoStrip trailing whitespace. NFCI.
Simon Pilgrim [Fri, 12 May 2017 17:42:36 +0000 (17:42 +0000)]
Strip trailing whitespace. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302927 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[KnownBits] Add bit counting methods to KnownBits struct and use them where possible
Craig Topper [Fri, 12 May 2017 17:20:30 +0000 (17:20 +0000)]
[KnownBits] Add bit counting methods to KnownBits struct and use them where possible

This patch adds min/max population count, leading/trailing zero/one bit counting methods.

The min methods return answers based on bits that are known without considering unknown bits. The max methods give answers taking into account the largest count that unknown bits could give.

Differential Revision: https://reviews.llvm.org/D32931

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302925 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[codeview] Fix assertion failure introduced in r295354 refactoring
Reid Kleckner [Fri, 12 May 2017 17:02:40 +0000 (17:02 +0000)]
[codeview] Fix assertion failure introduced in r295354 refactoring

CodeViewDebug sets Asm to nullptr to disable debug info generation.  You
can get a .ll file like no-cus.ll from 'clang -gcodeview -g0', which
happens in the ubsan test suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302923 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMake sure we have actually written what is expected by the test.
Galina Kistanova [Fri, 12 May 2017 17:00:13 +0000 (17:00 +0000)]
Make sure we have actually written what is expected by the test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302922 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/GlobalISel: Mark 32-bit integer constants as legal
Tom Stellard [Fri, 12 May 2017 16:46:46 +0000 (16:46 +0000)]
AMDGPU/GlobalISel: Mark 32-bit integer constants as legal

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D33115

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302919 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[APInt] Use MathExtras.h BitsToFloat/Double and Float/DoubleToBits instead of type...
Craig Topper [Fri, 12 May 2017 16:28:21 +0000 (16:28 +0000)]
[APInt] Use MathExtras.h BitsToFloat/Double and Float/DoubleToBits instead of type punning through a union

The functions in MathExtras.h uses a safer memcpy instead of going through a union.

Differential Revision: https://reviews.llvm.org/D33116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302916 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SPARC] Support 'f' and 'e' inline asm constraints.
James Y Knight [Fri, 12 May 2017 15:59:10 +0000 (15:59 +0000)]
[SPARC] Support 'f' and 'e' inline asm constraints.

Based on patch by Patrick Boettcher and Chris Dewhurst.

Differential Revision: https://reviews.llvm.org/D29116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302911 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] add tests for potential vector narrowing optimization (PR32790)
Sanjay Patel [Fri, 12 May 2017 15:56:39 +0000 (15:56 +0000)]
[x86] add tests for potential vector narrowing optimization (PR32790)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302910 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LoopUnroll] Fix a test. REQUIRE should be REQUIRES.
Davide Italiano [Fri, 12 May 2017 15:30:58 +0000 (15:30 +0000)]
[LoopUnroll] Fix a test. REQUIRE should be REQUIRES.

Found by inspection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302909 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[NewGVN] Improve debug output a bit. NFCI.
Davide Italiano [Fri, 12 May 2017 15:28:12 +0000 (15:28 +0000)]
[NewGVN] Improve debug output a bit. NFCI.

While debugging a predicate info problem, I noticed this was missing
a newline, making the debug output slightly less readable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302908 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[DAGCombine] Use SelectionDAG::getAnyExtOrTrunc helper. NFCI.
Simon Pilgrim [Fri, 12 May 2017 15:26:50 +0000 (15:26 +0000)]
[DAGCombine] Use SelectionDAG::getAnyExtOrTrunc helper. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302907 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[NewGVN] Format an assertion and fix a typo. NFCI.
Davide Italiano [Fri, 12 May 2017 15:25:56 +0000 (15:25 +0000)]
[NewGVN] Format an assertion and fix a typo. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302906 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[NewGVN] Don't incorrectly reset the memory leader.
Davide Italiano [Fri, 12 May 2017 15:22:45 +0000 (15:22 +0000)]
[NewGVN] Don't incorrectly reset the memory leader.

This code was missing a check for stores, so we were thinking the
congruency class didn't have any memory members, and reset the
memory leader.

Differential Revision:  https://reviews.llvm.org/D33056

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302905 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[DAGCombine] Use SelectionDAG::getZExtOrTrunc helper. NFCI.
Simon Pilgrim [Fri, 12 May 2017 13:22:12 +0000 (13:22 +0000)]
[DAGCombine] Use SelectionDAG::getZExtOrTrunc helper. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302897 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse SDValue::getOperand() helper. NFCI.
Simon Pilgrim [Fri, 12 May 2017 13:20:24 +0000 (13:20 +0000)]
Use SDValue::getOperand() helper. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302896 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse SDValue::getOperand() helper. NFCI.
Simon Pilgrim [Fri, 12 May 2017 13:08:45 +0000 (13:08 +0000)]
Use SDValue::getOperand() helper. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302894 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AVR] Migrate to new StructType::get owing to Supress all uses of LLVM_END_WITH_NULL
Leslie Zhai [Fri, 12 May 2017 09:08:03 +0000 (09:08 +0000)]
[AVR] Migrate to new StructType::get owing to Supress all uses of LLVM_END_WITH_NULL

Reviewers: dylanmckay, jroelofs, RKSimon, serge-sans-paille

Reviewed By: serge-sans-paille

Differential Revision: https://reviews.llvm.org/D33119

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302885 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[BPI] Ignore remainder while distributing the remaining probability from unreachanble
Serguei Katkov [Fri, 12 May 2017 07:50:06 +0000 (07:50 +0000)]
[BPI] Ignore remainder while distributing the remaining probability from unreachanble

This is a follow up patch for https://reviews.llvm.org/rL300440
to address a comment.

To make implementation to be consistent with other cases we just
ignore the remainder after distribution of remaining probability between
reachable edges.

If we reduced the probability of some edges coming to unreachable
blocks we should distribute the remaining part across other edges
coming to reachable blocks to satisfy the condition that sum of all
probabilities should be equal to one. If this remaining part is not
divided by number of "reachable" edges then we get this remainder.
This remainder probability should be pretty small. Other cases just ignore
if the sum of probabilities is not equal to one so we do the same.

Reviewers: chandlerc, sanjoy, vsk, junbuml, reames
Reviewed By: reames
Subscribers: reames, llvm-commits
Differential Revision: https://reviews.llvm.org/D32124

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302883 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[APInt] Fix a case where udivrem might delete and create a new allocation instead...
Craig Topper [Fri, 12 May 2017 07:21:09 +0000 (07:21 +0000)]
[APInt] Fix a case where udivrem might delete and create a new allocation instead of reusing the original.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302882 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Support/Compiler.h] - Use gnu::fallthrough for LLVM_FALLTHROUGH when available.
George Rimar [Fri, 12 May 2017 06:53:48 +0000 (06:53 +0000)]
[Support/Compiler.h] - Use gnu::fallthrough for LLVM_FALLTHROUGH when available.

I tried to compile LLD using GCC 7.1.0 and got warnings like
"warning: this statement may fall through [-Wimplicit-fallthrough=]"
(some more details are here: D32907)

GCC's __cplusplus value is 201402L by default, so macro expands to nothing,
though GCC 7 has support for [[fallthrough]].

Patch uses gnu::fallthrough when it is available and fixes warning I am observing.

Initial idea of way to fix belongs to Davide Italiano.

Differential revision: https://reviews.llvm.org/D33036

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302878 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoHandle a COPY with undef source operand in LowerCopy()
Jonas Paulsson [Fri, 12 May 2017 06:32:03 +0000 (06:32 +0000)]
Handle a COPY with undef source operand in LowerCopy()

Llvm-stress discovered that a COPY may end up in ExpandPostRA::LowerCopy()
with an undef source operand. It is not possible for the target to handle
this, as this flag is not passed to TII->copyPhysReg().

This patch solves this by treating such a COPY as an identity COPY.

Review: Matthias Braun
https://reviews.llvm.org/D32892

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302877 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[IfConversion] Keep the CFG updated incrementally in IfConvertTriangle
Mikael Holmen [Fri, 12 May 2017 06:28:58 +0000 (06:28 +0000)]
[IfConversion] Keep the CFG updated incrementally in IfConvertTriangle

Summary:
Instead of using RemoveExtraEdges (which uses analyzeBranch, which cannot
always be trusted) at the end to fixup the CFG we keep the CFG updated as
we go along and remove or add branches and merge blocks.

This way we won't have any problems if the involved MBBs contain
unanalyzable instructions.

This fixes PR32721.

In that case we had a triangle

   EBB
   | \
   |  |
   | TBB
   |  /
   FBB

where FBB didn't have any successors at all since it ended with an
unconditional return. Then TBB and FBB were be merged into EBB, but EBB
would still keep its successors, and the use of analyzeBranch and
CorrectExtraCFGEdges wouldn't help to remove them since the return
instruction is not analyzable (at least not on ARM).

Reviewers: kparzysz, iteratee, MatzeB

Reviewed By: iteratee

Subscribers: aemerson, rengolin, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D33037

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302876 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PM/Unswitch] Teach the new simple loop unswitch to handle loop
Chandler Carruth [Fri, 12 May 2017 02:19:59 +0000 (02:19 +0000)]
[PM/Unswitch] Teach the new simple loop unswitch to handle loop
invariant PHI inputs and to rewrite PHI nodes during the actual
unswitching.

The checking is quite easy, but rewriting the PHI nodes is somewhat
surprisingly challenging. This should handle both branches and switches.

I think this is now a full featured trivial unswitcher, and more full
featured than the trivial cases in the old pass while still being (IMO)
somewhat simpler in how it works.

Next up is to verify its correctness in more widespread testing, and
then to add non-trivial unswitching.

Thanks to Davide and Sanjoy for the excellent review. There is one
remaining question that I may address in a follow-up patch (see the
review thread for details) but it isn't related to the functionality
specifically.

Differential Revision: https://reviews.llvm.org/D32699

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302867 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[APInt] Add a utility method to change the bit width and storage size of an APInt.
Craig Topper [Fri, 12 May 2017 01:46:01 +0000 (01:46 +0000)]
[APInt] Add a utility method to change the bit width and storage size of an APInt.

Summary:
This adds a resize method to APInt that manages deleting/allocating storage for an APInt and changes its bit width. Use this to simplify code in copy assignment and divide.

The assignment code in particular was overly complicated. Treating every possible case as a separate implementation. I'm also pretty sure the clearUnusedBits code at the end was unnecessary. Since we always copying whole words from the source APInt. All unused bits should be clear in the source.

Reviewers: hans, RKSimon

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33073

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302863 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDWARF: Avoid cross-CU references under Fission
David Blaikie [Fri, 12 May 2017 01:13:45 +0000 (01:13 +0000)]
DWARF: Avoid cross-CU references under Fission

Turns out that the Fission/Split DWARF package format (DWP) is currently
insufficient to handle cross-CU (ref_addr) references. So for now,
duplicate any debug info needed in these situations:
* inlined_subroutine's abstract_origin
* inlined variable's abstract_origin
* types

Keep the ref_addr behavior in general, including in the split DWARF
inline debug info that can be emitted into the object files for online
symbolication.
Keep a flag to use the old (ref_addr) behavior for testing ways of
addressing this limitation in the DWP tool (& for those not using DWP
packaging).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302858 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[XRay][lib] Support and temporarily skip over CustomEvent records
Dean Michael Berris [Fri, 12 May 2017 01:06:41 +0000 (01:06 +0000)]
[XRay][lib] Support and temporarily skip over CustomEvent records

Summary:
In D30630 we will start writing custom event records. To avoid breaking
the tools that read the FDR mode records, we skip over these records.
To support these custom event records more effectively, we will have to
expose them in the trace loading API. Those changes will be forthcoming.

Reviewers: kpw, pelikan

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33032

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302856 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[git-llvm] Fix svn:eol-style issue for one-file patches
Reid Kleckner [Fri, 12 May 2017 00:10:19 +0000 (00:10 +0000)]
[git-llvm] Fix svn:eol-style issue for one-file patches

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302853 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCallGraph: Remove almost-unused field 'Root'.
Peter Collingbourne [Thu, 11 May 2017 23:59:05 +0000 (23:59 +0000)]
CallGraph: Remove almost-unused field 'Root'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302852 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoChange sample profile writer to make it deterministic.
Dehao Chen [Thu, 11 May 2017 23:43:44 +0000 (23:43 +0000)]
Change sample profile writer to make it deterministic.

Summary: This patch changes the function profile output order to be deterministic. In order to make it easier to understand, hottest functions (with most total samples) is ordered first.

Reviewers: dnovillo, davidxl

Reviewed By: dnovillo

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33111

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302851 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRestrict call metadata based hotness detection to Sample PGO mode
Teresa Johnson [Thu, 11 May 2017 23:18:05 +0000 (23:18 +0000)]
Restrict call metadata based hotness detection to Sample PGO mode

Summary:
Don't use the metadata on call instructions for determining hotness
unless we are in sample PGO mode, where it is needed because profile
counts are not accurate. In instrumentation mode this is not necessary
and does more harm than good when calls have VP metadata that hasn't
been properly scaled after transformations or dropped after constant
prop based devirtualization (both should be fixed, but we don't need
to do this in the first place for instrumentation PGO).

This required adjusting a number of tests to distinguish between sample
and instrumentation PGO handling, and to add in profile summary metadata
so that getProfileCount can get the summary.

Reviewers: davidxl, danielcdh

Subscribers: aemerson, rengolin, mehdi_amini, Prazek, llvm-commits

Differential Revision: https://reviews.llvm.org/D32877

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302844 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIssue diagnostics when returning FP values on x86_64 without SSE1/2
Reid Kleckner [Thu, 11 May 2017 22:43:02 +0000 (22:43 +0000)]
Issue diagnostics when returning FP values on x86_64 without SSE1/2

Avoid using report_fatal_error, because it will ask the user to file a
bug. If the user attempts to disable SSE on x86_64 and them use floating
point, that's a bug in their code, not a bug in the compiler.

This is just a start. There are other ways to crash the backend in this
configuration, but they should be updated to follow this pattern.

Differential Revision: https://reviews.llvm.org/D27522

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302835 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PPC] Change the register constraint of the first source operand of instruction mtvsr...
Guozhi Wei [Thu, 11 May 2017 22:17:35 +0000 (22:17 +0000)]
[PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0

According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0.

This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified.

Differential Revision: https://reviews.llvm.org/D32880

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302834 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[GISel]: Remove unused lambda captures. NFC
Aditya Nandakumar [Thu, 11 May 2017 21:56:51 +0000 (21:56 +0000)]
[GISel]: Remove unused lambda captures. NFC

https://reviews.llvm.org/D33085

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302831 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDecrease inlinecold-threshold to 45
Easwaran Raman [Thu, 11 May 2017 21:36:28 +0000 (21:36 +0000)]
Decrease inlinecold-threshold to 45

I ran the test-suite (including SPEC 2006) in PGO mode comparing cold
thresholds of 225 and 45. Here are some stats on the text size:

Out of 904 tests that ran, 197 see a change in text size. The average
text size reduction (of all the 904 binaries) is 1.07%. Of the 197
binaries, 19 see a text size increase, as high as 18%, but most of them
are small single source benchmarks. There are 3 multisource benchmarks
with a >0.5% size increase (0.7, 1.3 and 2.1 are their % increases). On
the other side of the spectrum, 31 benchmarks see >10% size reduction
and 6 of them are MultiSource.

I haven't run the test-suite with other values of inlinecold-threshold.
Since we have a cold callsite threshold of 45, I picked this value.

Differential revision: https://reviews.llvm.org/D33106

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302829 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDe-virtualize TerminatorInst successor accessors
Reid Kleckner [Thu, 11 May 2017 21:26:55 +0000 (21:26 +0000)]
De-virtualize TerminatorInst successor accessors

Use the same switch technique to eliminate virtual successor accessors
from TerminatorInst. Extracted from D31261.

NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302827 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDe-virtualize GlobalValue
Reid Kleckner [Thu, 11 May 2017 21:14:29 +0000 (21:14 +0000)]
De-virtualize GlobalValue

The erase/remove from parent methods now use a switch table to remove
themselves from their appropriate parent ilist.

The copyAttributesFrom method is now completely non-virtual, since we
only ever copy attributes from a global of the appropriate type.

Pre-requisite to de-virtualizing Value to save a vptr
(https://reviews.llvm.org/D31261).

NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302823 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64][MachineCombine] Fold FNMUL+FSUB -> FNMADD.
Chad Rosier [Thu, 11 May 2017 20:07:24 +0000 (20:07 +0000)]
[AArch64][MachineCombine] Fold FNMUL+FSUB -> FNMADD.

Differential Revision: http://reviews.llvm.org/D33101.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302822 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AMDGPU] Placate unused variable warning in release builds.
Davide Italiano [Thu, 11 May 2017 19:58:52 +0000 (19:58 +0000)]
[AMDGPU] Placate unused variable warning in release builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302821 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[MSP430] Generate EABI-compliant libcalls
Vadzim Dambrouski [Thu, 11 May 2017 19:56:14 +0000 (19:56 +0000)]
[MSP430] Generate EABI-compliant libcalls

Updates the MSP430 target to generate EABI-compatible libcall names.
As a byproduct, adjusts the hardware multiplier options available in
the MSP430 target, adds support for promotion of the ISD::MUL operation
for 8-bit integers, and correctly marks R11 as used by call instructions.

Patch by Andrew Wygle.

Differential Revision: https://reviews.llvm.org/D32676

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302820 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LiveVariables] Switch Kill/Defs sets to be DenseSet(s).
Davide Italiano [Thu, 11 May 2017 19:37:43 +0000 (19:37 +0000)]
[LiveVariables] Switch Kill/Defs sets to be DenseSet(s).

The testcase in PR32984 shows a non linear compile time increase
after a change that made the LoopUnroll pass more aggressive
(increasing the threshold).

My profiling shows all the time of PHI elimination goes to
llvm::LiveVariables::addNewBlock. This is because we keep
Defs/Kills registers in a SmallSet and vfind(const T &V); is O(N).

Switching to a DenseSet reduces the time spent in the pass from
297 seconds to 97 seconds. Profiling still shows a lot of time is
spent iterating the data structure, so I guess there's room for
improvement.

Dan tells me GCC uses real set operations for live registers and
it takes no-time on this testcase. Matthias points out we might
want to switch all this to LiveIntervalAnalysis so it's not entirely
sure if a rewrite is worth it.

Differential Revision:  https://reviews.llvm.org/D33088

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302819 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[APInt] Remove an APInt copy from the return of APInt::multiplicativeInverse.
Craig Topper [Thu, 11 May 2017 18:40:53 +0000 (18:40 +0000)]
[APInt] Remove an APInt copy from the return of APInt::multiplicativeInverse.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302816 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[APInt] Fix typo in comment. NFC
Craig Topper [Thu, 11 May 2017 17:57:43 +0000 (17:57 +0000)]
[APInt] Fix typo in comment. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302815 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Remove tfe bit from flat instruction definitions
Matt Arsenault [Thu, 11 May 2017 17:38:33 +0000 (17:38 +0000)]
AMDGPU: Remove tfe bit from flat instruction definitions

We don't use it and it was removed in gfx9, and the encoding
bit repurposed.

Additionally actually using it requires changing the output register
class, which wasn't done anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302814 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Pull fneg out of extract_vector_elt
Matt Arsenault [Thu, 11 May 2017 17:26:25 +0000 (17:26 +0000)]
AMDGPU: Pull fneg out of extract_vector_elt

This allows folding source modifiers in more f16 cases.
Makes it easier to select per-component packed neg modifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302813 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AMDGPU] Fix incorrect register pressure calculation
Stanislav Mekhanoshin [Thu, 11 May 2017 17:16:55 +0000 (17:16 +0000)]
[AMDGPU] Fix incorrect register pressure calculation

Earlier fix D32572 introduced a bug where live-ins were calculated
for basic block instead of scheduling region. This change fixes it.

Differential Revision: https://reviews.llvm.org/D33086

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302812 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SLP] Emit optimization remarks
Adam Nemet [Thu, 11 May 2017 17:06:17 +0000 (17:06 +0000)]
[SLP] Emit optimization remarks

The approach I followed was to emit the remark after getTreeCost concludes
that SLP is profitable.  I initially tried emitting them after the
vectorizeRootInstruction calls in vectorizeChainsInBlock but I vaguely
remember missing a few cases for example in HorizontalReduction::tryToReduce.

ORE is placed in BoUpSLP so that it's available from everywhere (notably
HorizontalReduction::tryToReduce).

We use the first instruction in the root bundle as the locator for the remark.
In order to get a sense how far the tree is spanning I've include the size of
the tree in the remark.  This is not perfect of course but it gives you at
least a rough idea about the tree.  Then you can follow up with -view-slp-tree
to really see the actual tree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302811 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Eliminate integer compare instructions - vol. 1
Nemanja Ivanovic [Thu, 11 May 2017 16:54:23 +0000 (16:54 +0000)]
[PowerPC] Eliminate integer compare instructions - vol. 1

This patch is the first in a series of patches to provide code gen for
doing compares in GPRs when the compare result is required in a GPR.

It adds the infrastructure to select GPR sequences for i1->i32 and i1->i64
extensions. This first patch handles equality comparison on i32 operands with
the result sign or zero extended.

Differential Revision: https://reviews.llvm.org/D31847

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302810 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[DAGCombine] Use SelectionDAG::getAnyExtOrTrunc helper. NFCI.
Simon Pilgrim [Thu, 11 May 2017 16:40:44 +0000 (16:40 +0000)]
[DAGCombine] Use SelectionDAG::getAnyExtOrTrunc helper. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302808 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix -DLLVM_ENABLE_THREADS=OFF build after r302748
Hans Wennborg [Thu, 11 May 2017 15:32:47 +0000 (15:32 +0000)]
Fix -DLLVM_ENABLE_THREADS=OFF build after r302748

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302806 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][AVX] Added zeroall/zeroupper scheduler tests
Simon Pilgrim [Thu, 11 May 2017 15:02:49 +0000 (15:02 +0000)]
[X86][AVX] Added zeroall/zeroupper scheduler tests

Missing on SandyBridge and Btver2 models

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302804 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoModules: fix modules build.
Tim Northover [Thu, 11 May 2017 14:51:43 +0000 (14:51 +0000)]
Modules: fix modules build.

A recent commit made GlobalVariable.h depend on intrinsics generation, so (I
think) it needs to be in the lower-level module. I'll confirm with others, but
this should fix the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302803 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[IR] Allow attributes with global variables
Javed Absar [Thu, 11 May 2017 12:28:08 +0000 (12:28 +0000)]
[IR] Allow attributes with global variables

This patch extends llvm-ir to allow attributes to be set on global variables.
An RFC was sent out earlier by my colleague James Molloy: http://lists.llvm.org/pipermail/cfe-dev/2017-March/053100.html
A key part of that proposal was to extend LLVM-IR to carry attributes on global variables.
This generic feature could be useful for multiple purposes.
In our present context, it would be useful to carry user specified sections for bss/rodata/data.

Reviewed by: Jonathan Roelofs, Reid Kleckner
Differential Revision: https://reviews.llvm.org/D32009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302794 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[GlobalISel][X86] Remove hand-written G_FADD/F_SUB selection.
Igor Breger [Thu, 11 May 2017 12:15:03 +0000 (12:15 +0000)]
[GlobalISel][X86] Remove hand-written G_FADD/F_SUB selection.
Now it handle by TableGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302793 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Moving X86Local namespace from .cpp to .h file to use it in memory folding...
Ayman Musa [Thu, 11 May 2017 11:51:12 +0000 (11:51 +0000)]
[X86] Moving X86Local namespace from .cpp to .h file to use it in memory folding TableGen backend.

Differential Revision: https://reviews.llvm.org/D32797

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302791 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LV] Refactor ILV.vectorize{Loop}() by introducing LVP.executePlan(); NFC
Ayal Zaks [Thu, 11 May 2017 11:36:33 +0000 (11:36 +0000)]
[LV] Refactor ILV.vectorize{Loop}() by introducing LVP.executePlan(); NFC

Introduce LoopVectorizationPlanner.executePlan(), replacing ILV.vectorize() and
refactoring ILV.vectorizeLoop(). Method collectDeadInstructions() is moved from
ILV to LVP. These changes facilitate building VPlans and using them to generate
code, following https://reviews.llvm.org/D28975 and its tentative breakdown.

Method ILV.createEmptyLoop() is renamed ILV.createVectorizedLoopSkeleton() to
improve clarity; it's contents remain intact.

Differential Revision: https://reviews.llvm.org/D32200

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302790 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[msan] Fix PR32842
Alexander Potapenko [Thu, 11 May 2017 11:07:48 +0000 (11:07 +0000)]
[msan] Fix PR32842

It turned out that MSan was incorrectly calculating the shadow for int comparisons: it was done by truncating the result of (Shadow1 OR Shadow2) to i1, effectively rendering all bits except LSB useless.
This approach doesn't work e.g. in the case where the values being compared are even (i.e. have the LSB of the shadow equal to zero).
Instead, if CreateShadowCast() has to cast a bigger int to i1, we replace the truncation with an ICMP to 0.

This patch doesn't affect the code generated for SPEC 2006 binaries, i.e. there's no performance impact.

For the test case reported in PR32842 MSan with the patch generates a slightly more efficient code:

  orq     %rcx, %rax
  jne     .LBB0_6
, instead of:

  orl     %ecx, %eax
  testb   $1, %al
  jne     .LBB0_6

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302787 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Fix a failure to select with AVX-512 when the type legalizer
Chandler Carruth [Thu, 11 May 2017 10:52:16 +0000 (10:52 +0000)]
[x86] Fix a failure to select with AVX-512 when the type legalizer
manages to form a VSELECT with a non-i1 element type condition. Those
are technically allowed in SDAG (at least, the generic type legalization
logic will form them and I wouldn't want to try to audit everything te
preclude forming them) so we need to be able to lower them.

This isn't too hard to implement. We mark VSELECT as custom so we get
a chance in C++, add a fast path for i1 conditions to get directly
handled by the patterns, and a fallback when we need to manually force
the condition to be an i1 that uses the vptestm instruction to turn
a non-mask into a mask.

This, unsurprisingly, generates awful code. But it at least doesn't
crash. This was actually impacting open source packages built with LLVM
for AVX-512 in the wild, so quickly landing a patch that at least stops
the immediate bleeding.

I think I've found where to fix the codegen quality issue, but less
confident of that change so separating it out from the thing that
doesn't change the result of any existing test case but causes mine to
not crash.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302785 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoStrip trailing whitespace. NFCI.
Simon Pilgrim [Thu, 11 May 2017 10:03:05 +0000 (10:03 +0000)]
Strip trailing whitespace. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302784 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM][GlobalISel] Legalize narrow scalar ops by widening
Diana Picus [Thu, 11 May 2017 09:45:57 +0000 (09:45 +0000)]
[ARM][GlobalISel] Legalize narrow scalar ops by widening

This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB
and MUL to 32 bits since we only have TableGen patterns for 32 bits.
See the commit message for r292827 for more details.

At this point we could just remove some of the tests for regbankselect
and instruction-select, since we're not going to see any narrow
operations at those levels anymore. Instead I decided to update them
with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences
generated by the legalizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302782 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove spurious cast of nullptr. NFC.
Serge Guelton [Thu, 11 May 2017 08:53:00 +0000 (08:53 +0000)]
Remove spurious cast of nullptr. NFC.

Conversion rules allow automatic casting of nullptr to any pointer type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302780 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove now useless trailing nullptr in StructType::get
Serge Guelton [Thu, 11 May 2017 08:46:02 +0000 (08:46 +0000)]
Remove now useless trailing nullptr in StructType::get

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302779 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM][GlobalISel] Support for G_ANYEXT
Diana Picus [Thu, 11 May 2017 08:28:31 +0000 (08:28 +0000)]
[ARM][GlobalISel] Support for G_ANYEXT

G_ANYEXT can be introduced by the legalizer when widening scalars. Add
support for it in the register bank info (same mapping as everything
else) and in the instruction selector.

When selecting it, we treat it as a COPY, just like G_TRUNC. On this
occasion we get rid of some assertions in selectCopy so we can reuse it.
This shouldn't be a problem at the moment since we're not supporting any
complicated cases (e.g. FPR, different register banks). We might want to
separate the paths when we do.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302778 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[GlobalISel][X86] G_ICMP support.
Igor Breger [Thu, 11 May 2017 07:17:40 +0000 (07:17 +0000)]
[GlobalISel][X86] G_ICMP support.

Summary: support G_ICMP for scalar types i8/i16/i64.

Reviewers: zvi, guyblank

Reviewed By: guyblank

Subscribers: rovka, kristof.beyls, llvm-commits, krytarowski

Differential Revision: https://reviews.llvm.org/D32995

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302774 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[APInt] Remove an unneeded extra temporary APInt from toString.
Craig Topper [Thu, 11 May 2017 07:10:43 +0000 (07:10 +0000)]
[APInt] Remove an unneeded extra temporary APInt from toString.

Turns out udivrem can write its output to the same location as one of its inputs so the extra temporary isn't needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302772 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[APInt] Use negate() instead of copying an APInt to negate it and then writing back...
Craig Topper [Thu, 11 May 2017 07:02:04 +0000 (07:02 +0000)]
[APInt] Use negate() instead of copying an APInt to negate it and then writing back over the original value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302770 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SCEV] Reduce possible APInt allocations a bit.
Craig Topper [Thu, 11 May 2017 06:48:54 +0000 (06:48 +0000)]
[SCEV] Reduce possible APInt allocations a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302769 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SCEV] Remove unneeded 'using namespace APIntOps'.
Craig Topper [Thu, 11 May 2017 06:48:51 +0000 (06:48 +0000)]
[SCEV] Remove unneeded 'using namespace APIntOps'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302768 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Move getX86ConditionCode() from X86FastISel.cpp to X86InstrInfo.cpp. NFC
Igor Breger [Thu, 11 May 2017 06:36:37 +0000 (06:36 +0000)]
[X86] Move getX86ConditionCode() from X86FastISel.cpp to X86InstrInfo.cpp. NFC

Summary:
Move getX86ConditionCode() from X86FastISel.cpp to X86InstrInfo.cpp so it can be used by GloabalIsel instruction selector.
This is a pre-commit for a patch I'm working on to support G_ICMP. NFC.

Reviewers: zvi, guyblank, delena

Reviewed By: guyblank, delena

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33038

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302767 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSupportTests: Suppress ParallelTests on mingw for now. Investigating.
NAKAMURA Takumi [Thu, 11 May 2017 06:35:51 +0000 (06:35 +0000)]
SupportTests: Suppress ParallelTests on mingw for now. Investigating.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302766 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove redundant initialization. NFC
Paul Robinson [Thu, 11 May 2017 02:07:08 +0000 (02:07 +0000)]
Remove redundant initialization. NFC

Post-commit review of r301940 by David Blaikie.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302756 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd temporary workaround to allow in-tree libc++ builds on Windows
Eric Fiselier [Thu, 11 May 2017 01:44:30 +0000 (01:44 +0000)]
Add temporary workaround to allow in-tree libc++ builds on Windows

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302753 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFinal (hopefully) fix for the build bots.
Zachary Turner [Thu, 11 May 2017 00:22:18 +0000 (00:22 +0000)]
Final (hopefully) fix for the build bots.

This time it actually occurred to me to change the #defines
to actually test the pre-processed out codepath.  Hopefully
this time it works.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302752 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTry again to fix the buildbots.
Zachary Turner [Thu, 11 May 2017 00:18:52 +0000 (00:18 +0000)]
Try again to fix the buildbots.

TaskGroup and Latch need to be in llvm::parallel::detail, not
in llvm::detail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302751 91177308-0d34-0410-b5e6-96231b3b80d8