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Francis Visoiu Mistrih [Wed, 28 Nov 2018 12:00:28 +0000 (12:00 +0000)]
[MachineScheduler] Add support for clustering mem ops with FI base operands
Before this patch, the following stores in `merge_fail` would fail to be
merged, while they would get merged in `merge_ok`:
```
void use(unsigned long long *);
void merge_fail(unsigned key, unsigned index)
{
unsigned long long args[8];
args[0] = key;
args[1] = index;
use(args);
}
void merge_ok(unsigned long long *dst, unsigned a, unsigned b)
{
dst[0] = a;
dst[1] = b;
}
```
The reason is that `getMemOpBaseImmOfs` would return false for FI base
operands.
This adds support for this.
Differential Revision: https://reviews.llvm.org/D54847
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347747
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Francis Visoiu Mistrih [Wed, 28 Nov 2018 12:00:20 +0000 (12:00 +0000)]
[CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operand
Currently, instructions doing memory accesses through a base operand that is
not a register can not be analyzed using `TII::getMemOpBaseRegImmOfs`.
This means that functions such as `TII::shouldClusterMemOps` will bail
out on instructions using an FI as a base instead of a register.
The goal of this patch is to refactor all this to return a base
operand instead of a base register.
Then in a separate patch, I will add FI support to the mem op clustering
in the MachineScheduler.
Differential Revision: https://reviews.llvm.org/D54846
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347746
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Simon Atanasyan [Wed, 28 Nov 2018 11:48:07 +0000 (11:48 +0000)]
[DebugInfo] Rename EmitDebugThreadLocal back to EmitDebugValue. NFC
This reverts r294500. DwarfCompileUnit::addAddressExpr uses DIEExpr
for PCOffset. In that case the expression is unrelated to thread locals
and so emitting a value of the DIEExpr does not have to always mean
emit-debug-thread-local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347744
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Simon Tatham [Wed, 28 Nov 2018 11:43:49 +0000 (11:43 +0000)]
[TableGen] Better error checking for TIED_TO constraints.
There are quite strong constraints on how you can use the TIED_TO
constraint between MC operands, many of which are currently not
checked until compiler run time.
MachineVerifier enforces that operands can only be tied together in
pairs (no three-way ties), and MachineInstr::tieOperands enforces that
one of the tied operands must be an output operand (def) and the other
must be an input operand (use).
Now we check these at TableGen time, so that if you violate any of
them in a new instruction definition, you find out immediately,
instead of having to wait until you compile something that makes code
generation hit one of those assertions.
Also in this commit, all the error reports in ParseConstraint now
include the name and source location of the def where the problem
happened, so that if you do trigger any of these errors, it's easier
to find the part of your TableGen input where you made the mistake.
The trunk sources already build successfully with this additional
error check, so I think no in-tree target has any of these problems.
Reviewers: fhahn, lhames, nhaehnle, MatzeB
Reviewed By: MatzeB
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53815
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347743
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David Spickett [Wed, 28 Nov 2018 11:38:10 +0000 (11:38 +0000)]
[ARM, AArch64] Move ARM/AArch64 target parsers into
separate files to enable future changes.
This moves ARM and AArch64 target parsing into their
own files. They are still accessible through
TargetParser.h as before.
Several functions in AArch64 which were just forwarders to ARM
have been removed. All except AArch64::getFPUName were unused,
and that was only used in a test. Which itself was overlapping
one in ARM, so it has also been removed.
Differential revision: https://reviews.llvm.org/D53980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347741
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Jonas Paulsson [Wed, 28 Nov 2018 08:58:27 +0000 (08:58 +0000)]
[SystemZ::TTI] Improve cost for compare of i64 with extended i32 load
CGF/CLGF compares an i64 register with a sign/zero extended loaded i32 value
in memory.
This patch makes such a load considered foldable and so gets a 0 cost.
Review: Ulrich Weigand
https://reviews.llvm.org/D54944
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347735
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Jonas Paulsson [Wed, 28 Nov 2018 08:31:50 +0000 (08:31 +0000)]
[SystemZ::TTI] Improve costs for i16 add, sub and mul against memory.
AH, SH and MH costs are already covered in the cases where LHS is 32 bits and
RHS is 16 bits of memory sign-extended to i32.
As these instructions are also used when LHS is i16, this patch recognizes
that the loads will get folded then as well.
Review: Ulrich Weigand
https://reviews.llvm.org/D54940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347734
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Jonas Paulsson [Wed, 28 Nov 2018 08:08:05 +0000 (08:08 +0000)]
[SystemZ::TTI] Improved cost values for comparison against memory.
Single instructions exist for i8 and i16 comparisons of memory against a
small immediate.
This patch makes sure that if the load in these cases has a single user (the
ICmp), it gets a 0 cost (folded), and also that the ICmp gets a cost of 1.
Review: Ulrich Weigand
https://reviews.llvm.org/D54897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347733
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Jonas Paulsson [Wed, 28 Nov 2018 07:52:34 +0000 (07:52 +0000)]
[SystemZ::TTI] Return zero cost for scalar load/store connected with a bswap.
Since byte-swapping loads and stores are supported, a 'load -> bswap' or
'bswap -> store' sequence should have the cost of one.
Review: Ulrich Weigand
https://reviews.llvm.org/D54870
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347732
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Martin Storsjo [Wed, 28 Nov 2018 06:51:50 +0000 (06:51 +0000)]
[llvm-objcopy] Hook up the -V alias to --version, output "GNU strip"
This allows libtool to detect the presence of llvm-strip and use
it with the options --strip-debug and --strip-unneeded.
Also hook up the -V alias for objcopy.
Differential Revision: https://reviews.llvm.org/D54936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347731
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Mircea Trofin [Wed, 28 Nov 2018 01:08:45 +0000 (01:08 +0000)]
Do not insert prefetches with unsupported memory operands.
Summary:
Ignore advices where the memory operand of the 'anchor' instruction
uses unsupported register types.
Reviewers: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D54983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347724
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Craig Topper [Wed, 28 Nov 2018 00:33:34 +0000 (00:33 +0000)]
[X86] Add test cases to show that we don't properly take -mprefer-vector-width=256 and -min-legal-vector-width=256 into account when costing sext/zext.
The check lines marked AVX256 in the zext256/sext256 functions should be closer to the AVX values which would take into account a splitting cost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347722
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Craig Topper [Tue, 27 Nov 2018 22:46:05 +0000 (22:46 +0000)]
[X86] Add exhaustive cost model testing for sext/zext for all vector types we reasonably support. Add cost model tests for truncating to vXi1.
Our sext/zext cost modeling was somewhat incomplete. And had no coverage for the fact that avx512bw v32i16/v64i8 types return a scalarization cost.
Truncates are a whole different mess because isTruncateFree is returning true for vectors when it shouldn't and that's the fall back for anything not in the tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347719
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Evandro Menezes [Tue, 27 Nov 2018 20:59:01 +0000 (20:59 +0000)]
[TableGen] Improve readability of generated code (NFC)
Improve the readability of the generated code for `MCOpcodeSwitchStatement`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347707
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Evandro Menezes [Tue, 27 Nov 2018 20:58:27 +0000 (20:58 +0000)]
[TableGen] Refactor macro names (NFC)
Make the names for the macros for `TargetInstrInfo` uniform.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347706
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Martin Storsjo [Tue, 27 Nov 2018 20:47:38 +0000 (20:47 +0000)]
[yaml2obj] Treat COFF/ARM64 as a 64 bit architecture
Differential Revision: https://reviews.llvm.org/D54935
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347703
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Nico Weber [Tue, 27 Nov 2018 20:10:26 +0000 (20:10 +0000)]
[gn build] Add enough build files to be able to build llvm-tblgen.
Adds build files for:
- llvm/lib/DebugInfo/CodeView
- llvm/lib/DebugInfo/MSF
- llvm/lib/MC
- llvm/lib/TableGen
- llvm/utils/TableGen
All the build files just list sources and deps and are uninteresting.
Differential Revision: https://reviews.llvm.org/D54931
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347702
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Zola Bridges [Tue, 27 Nov 2018 19:56:46 +0000 (19:56 +0000)]
[clang][slh] add attribute for speculative load hardening
Summary:
Resubmit this with no changes because I think the build was broken
by a different diff.
-----
The prior diff had to be reverted because there were two tests
that failed. I updated the two tests in this diff
clang/test/Misc/pragma-attribute-supported-attributes-list.test
clang/test/SemaCXX/attr-speculative-load-hardening.cpp
----- Summary from Previous Diff (Still Accurate) -----
LLVM IR already has an attribute for speculative_load_hardening. Before
this commit, when a user passed the -mspeculative-load-hardening flag to
Clang, every function would have this attribute added to it. This Clang
attribute will allow users to opt into SLH on a function by function basis.
This can be applied to functions and Objective C methods.
Reviewers: chandlerc, echristo, kristof.beyls, aaron.ballman
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D54915
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347701
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Nikita Popov [Tue, 27 Nov 2018 19:52:56 +0000 (19:52 +0000)]
[InstCombine] Add tests for saturating add/sub; NFC
These are baseline tests for D54534.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347700
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Craig Topper [Tue, 27 Nov 2018 19:44:40 +0000 (19:44 +0000)]
[X86] Add cost model tests for experimental.vector.reduce.* with -x86-experimental-vector-widening-legalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347697
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Craig Topper [Tue, 27 Nov 2018 19:44:36 +0000 (19:44 +0000)]
[X86] Add cost model test for masked load an store with -x86-experimental-vector-widening-legalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347696
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Craig Topper [Tue, 27 Nov 2018 19:44:34 +0000 (19:44 +0000)]
[X86] Add cost model tests for fp_to_int/int_to_fp with -x86-experimental-vector-widening-legalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347695
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Craig Topper [Tue, 27 Nov 2018 19:44:30 +0000 (19:44 +0000)]
[X86] Add cost model tests for shifts with -x86-experimental-vector-widening-legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347694
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Zachary Turner [Tue, 27 Nov 2018 19:29:12 +0000 (19:29 +0000)]
[lit] Pass more environment variables through to child processes.
This arose when I was trying to have a substitution which invoked a
python script P, and that python script tried to invoke clang-cl (or
even cl). Since we invoke P with a custom environment, it doesn't
inherit the environment of the parent, and then when we go to invoke
clang-cl, it's unable to find the MSVC installation directory. There
were many more I could have passed through which are set by vcvarsall,
but I tried to keep it simple and only pass through the important ones.
Differential Revision: https://reviews.llvm.org/D54963
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347691
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Reid Kleckner [Tue, 27 Nov 2018 19:14:11 +0000 (19:14 +0000)]
Add missing error checking code intended for r347687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347690
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Reid Kleckner [Tue, 27 Nov 2018 19:00:23 +0000 (19:00 +0000)]
[PDB] Add symbol records in bulk
Summary:
This speeds up linking clang.exe/pdb with /DEBUG:GHASH by 31%, from
12.9s to 9.8s.
Symbol records are typically small (16.7 bytes on average), but we
processed them one at a time. CVSymbol is a relatively "large" type. It
wraps an ArrayRef<uint8_t> with a kind an optional 32-bit hash, which we
don't need. Before this change, each DbiModuleDescriptorBuilder would
maintain an array of CVSymbols, and would write them individually with a
BinaryItemStream.
With this change, we now add symbols that happen to appear contiguously
in bulk. For each .debug$S section (roughly one per function), we
allocate two copies, one for relocation, and one for realignment
purposes. For runs of symbols that go in the module stream, which is
most symbols, we now add them as a single ArrayRef<uint8_t>, so the
vector DbiModuleDescriptorBuilder is roughly linear in the number of
.debug$S sections (O(# funcs)) instead of the number of symbol records
(very large).
Some stats on symbol sizes for the curious:
PDB size: 507M
sym bytes: 316,508,016
sym count: 18,954,971
sym byte avg: 16.7
As future work, we may be able to skip copying symbol records in the
linker for realignment purposes if we make LLVM write them aligned into
the object file. We need to double check that such symbol records are
still compatible with link.exe, but if so, it's definitely worth doing,
since my profile shows we spend 500ms in memcpy in the symbol merging
code. We could potentially cut that in half by saving a copy.
Alternatively, we could apply the relocations *after* we iterate the
symbols. This would require some careful re-engineering of the
relocation processing code, though.
Reviewers: zturner, aganea, ruiu
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D54554
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347687
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Vyacheslav Zakharin [Tue, 27 Nov 2018 18:57:43 +0000 (18:57 +0000)]
[TableGen] Preprocessing support
Differential Revision: https://reviews.llvm.org/D54926
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347686
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Craig Topper [Tue, 27 Nov 2018 18:24:56 +0000 (18:24 +0000)]
[X86] Replace an APInt that is guaranteed to be 8-bits with just an 'unsigned'
We're already mixing this APInt with other 'unsigned' variables. This allows us to use regular comparison operators instead of needing to use APInt::ult or APInt::uge. And it removes a later conversion from APInt to unsigned.
I might be adding another combine to this function and this will probably simplify the logic required for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347684
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Florian Hahn [Tue, 27 Nov 2018 18:17:27 +0000 (18:17 +0000)]
[PartialInliner] Make PHIs free in cost computation.
InlineCost also treats them as free and the current implementation
can cause assertion failures if PHI nodes are moved outside the region
from entry BBs to the region.
It also updates the code to use the instructionsWithoutDebug iterator.
Reviewers: davidxl, davide, vsk, graham-yiu-huawei
Reviewed By: davidxl
Differential Revision: https://reviews.llvm.org/D54748
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347683
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Craig Topper [Tue, 27 Nov 2018 18:05:00 +0000 (18:05 +0000)]
[X86] Add cascade lake arch in X86 target.
This is skylake-avx512 with the addition of avx512vnni ISA.
Patch by Jianping Chen
Differential Revision: https://reviews.llvm.org/D54785
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347681
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James Dennett [Tue, 27 Nov 2018 17:53:03 +0000 (17:53 +0000)]
Documentation: add \file markup as needed.
This makes Doxygen correctly associate the doc comment with the current
file rather than adding to the documentation for namespace llvm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347679
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Pavel Labath [Tue, 27 Nov 2018 16:11:24 +0000 (16:11 +0000)]
[Demangle] remove itaniumFindTypesInMangledName
Summary:
This (very specialized) function was added to enable an LLDB use case.
Now that a more generic interface (overriding of parser functions -
D52992) is available, and LLDB has been converted to use that (D54074),
the function is unused and can be removed.
Reviewers: erik.pilkington, sgraenitz, rsmith
Subscribers: mgorny, hiraditya, christof, libcxx-commits, llvm-commits
Differential Revision: https://reviews.llvm.org/D54893
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347670
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Andrea Di Biagio [Tue, 27 Nov 2018 15:56:00 +0000 (15:56 +0000)]
[llvm-mca] pass -dispatch-stats flag to a couple of tests. NFC
This change is in preparation for a patch that fixes PR36666.
llvm-mca currently doesn't know if a buffered processor resource describes a
load or store queue. So, any dynamic dispatch stall caused by the lack of
load/store queue entries is normally reported as a generic SCHEDULER stall. See for
example the -dispatch-stats output from the two tests modified by this patch.
In future, processor models will be able to tag processor resources that are
used to describe load/store queues. That information would then be used by
llvm-mca to correctly classify dynamic dispatch stalls caused by the lack of
tokens in the LS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347662
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Sanjay Patel [Tue, 27 Nov 2018 15:52:17 +0000 (15:52 +0000)]
[x86] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347661
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Stanislav Mekhanoshin [Tue, 27 Nov 2018 15:13:37 +0000 (15:13 +0000)]
[AMDGPU] Disable DAG combine at -O0
Differential Revision: https://reviews.llvm.org/D54358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347659
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Tim Northover [Tue, 27 Nov 2018 11:08:14 +0000 (11:08 +0000)]
InstCombine: add comment explaining malloc deletion. NFC.
I tried to change this, not quite realising the logic behind what we
were doing. Hopefully this comment will help the next person to come
along.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347653
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Max Kazantsev [Tue, 27 Nov 2018 07:51:18 +0000 (07:51 +0000)]
Add missing REQUIRES: asserts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347644
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Craig Topper [Tue, 27 Nov 2018 07:20:19 +0000 (07:20 +0000)]
[X86] Add test cases for vector shifts of v2i32/v2i16/v4i16/v2i8/v4i8/v8i8 with promotion legalization and widening legalization. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347643
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Craig Topper [Tue, 27 Nov 2018 06:24:56 +0000 (06:24 +0000)]
[X86] Use getUnpackl/getUnpackh instead of directly creating UNPCKL/UNPCKH nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347642
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Max Kazantsev [Tue, 27 Nov 2018 06:19:42 +0000 (06:19 +0000)]
[LoopSimplifyCFG] Turn on term folding after underlying bug fixed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347641
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Max Kazantsev [Tue, 27 Nov 2018 06:17:21 +0000 (06:17 +0000)]
[LoopSimplifyCFG] Fix corner case with duplicating successors
It fixes a bug that doesn't update Phi inputs of the only live successor that
is in the list of block's successors more than once.
Thanks @uabelho for finding this.
Differential Revision: https://reviews.llvm.org/D54849
Reviewed By: anna
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347640
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Nico Weber [Tue, 27 Nov 2018 06:04:49 +0000 (06:04 +0000)]
[gn build] Merge r347530 to gn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347639
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Nico Weber [Tue, 27 Nov 2018 05:49:08 +0000 (05:49 +0000)]
Move a file I forgot to move in r347636.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347638
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Nico Weber [Tue, 27 Nov 2018 05:19:17 +0000 (05:19 +0000)]
[gn build] Create abi-breaking.h, config.h, llvm-config.h, and add a build file for llvm/lib/Support.
The comments at the top of
llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn and
llvm/utils/gn/build/write_cmake_config.py should explain the main bits
happening in this patch. The main parts here are that these headers are
generated at build time, not gn time, and that currently they don't do any
actual feature checks but just hardcode most things based on the current OS,
which seems to work well enough. If this stops being enough, the feature checks
should each be their own action writing the result to somewhere, and the config
write step should depend on those checks (so that they can run in parallel and
as part of the build) -- utils/llvm/gn/README.rst already has some more words
on that in "Philosophy".
(write_cmake_config.py is also going to be used to write clang's
clang/include/clang/Config/config.h)
This also adds a few files for linking to system libraries in a consistent way
if needed in llvm/utils/gn/build/libs (and moves pthread to that model).0
I'm also adding llvm/utils/gn/secondary/llvm/lib/Target/targets.gni in this
patch because $native_arch is needed for writing llvm-config.h -- the rest of
it will be used later, when the build files for llvm/lib/Target get added. That
file describes how to select which archs to build.
As a demo, also add a build file for llvm-undname and make it the default build
target (it depends on everything that can currently be built).
Differential Revision: https://reviews.llvm.org/D54678
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347636
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Craig Topper [Tue, 27 Nov 2018 02:57:27 +0000 (02:57 +0000)]
[X86] Prevent DAG combine from folding a bitcast from vXi1 to iX with a store on pre-AVX512 targets.
If we fold the bitcast into the store we'll end up creating a truncating store to vXi1 that will get scalarized. Instead allow the bitcast to be turned into a movmsk.
We probably need to do something if the store itself is a vXi1 type, but I'll leave that til a testcase appears.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347632
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Craig Topper [Tue, 27 Nov 2018 02:57:23 +0000 (02:57 +0000)]
[X86] Add a bunch of test cases for storing a scalar bitcasted from a vXi1 type.
Currently a store combine will absorb the bitcast before our combine that turns bitcasts into movmsk gets a chance to run. This results in a store being created with a vXi1 type. Type legalization then promotes the input type and makes this a truncating store. Then we badly scalarize this store.
Currently we avoid this on v8i1->i8 bitcasts due to an incompletely qualified(per the original intention) check in isLoadBitCastBeneficial. An easy fix is to disable this for all vXi1->iX bitcasts on pre-avx512 targets. We'll still generate terrible code if the IR explicitly contains a store of vXi1 without a bitcast. We could probably solve that by just turning all stores of vXi1 into (store (iX (bitcast))) as an early DAG combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347631
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Zola Bridges [Tue, 27 Nov 2018 02:22:00 +0000 (02:22 +0000)]
Revert "[clang][slh] add attribute for speculative load hardening"
until I figure out why the build is failing or timing out
***************************
Summary:
The prior diff had to be reverted because there were two tests
that failed. I updated the two tests in this diff
clang/test/Misc/pragma-attribute-supported-attributes-list.test
clang/test/SemaCXX/attr-speculative-load-hardening.cpp
LLVM IR already has an attribute for speculative_load_hardening. Before
this commit, when a user passed the -mspeculative-load-hardening flag to
Clang, every function would have this attribute added to it. This Clang
attribute will allow users to opt into SLH on a function by function
basis.
This can be applied to functions and Objective C methods.
Reviewers: chandlerc, echristo, kristof.beyls, aaron.ballman
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D54915
This reverts commit
a5b3c232d1e3613f23efbc3960f8e23ea70f2a79.
(r347617)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347628
91177308-0d34-0410-b5e6-
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Vitaly Buka [Tue, 27 Nov 2018 01:56:44 +0000 (01:56 +0000)]
[stack-safety] Update comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347626
91177308-0d34-0410-b5e6-
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Vitaly Buka [Tue, 27 Nov 2018 01:56:35 +0000 (01:56 +0000)]
[stack-safety] Fix and uncomment assert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347625
91177308-0d34-0410-b5e6-
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Vitaly Buka [Tue, 27 Nov 2018 01:56:26 +0000 (01:56 +0000)]
[stack-safety] Fix build on gcc 5.4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347624
91177308-0d34-0410-b5e6-
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Sanjay Patel [Tue, 27 Nov 2018 00:08:21 +0000 (00:08 +0000)]
[InstCombine] add tests for rotate/bswap equality; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347618
91177308-0d34-0410-b5e6-
96231b3b80d8
Zola Bridges [Tue, 27 Nov 2018 00:03:44 +0000 (00:03 +0000)]
[clang][slh] add attribute for speculative load hardening
Summary:
The prior diff had to be reverted because there were two tests
that failed. I updated the two tests in this diff
clang/test/Misc/pragma-attribute-supported-attributes-list.test
clang/test/SemaCXX/attr-speculative-load-hardening.cpp
----- Summary from Previous Diff (Still Accurate) -----
LLVM IR already has an attribute for speculative_load_hardening. Before
this commit, when a user passed the -mspeculative-load-hardening flag to
Clang, every function would have this attribute added to it. This Clang
attribute will allow users to opt into SLH on a function by function basis.
This can be applied to functions and Objective C methods.
Reviewers: chandlerc, echristo, kristof.beyls, aaron.ballman
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D54915
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347617
91177308-0d34-0410-b5e6-
96231b3b80d8
JF Bastien [Mon, 26 Nov 2018 23:48:47 +0000 (23:48 +0000)]
Fix debug build break
Comment out an assertion from D54543 which failed with error: no member named 'Range' in '(anonymous namespace)::PassAsArgInfo'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347616
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Sterling Augustine [Mon, 26 Nov 2018 23:26:31 +0000 (23:26 +0000)]
Notify the linker when a TU compiled with split-stack has a function without a prologue.
More context here: https://go-review.googlesource.com/c/go/+/148819/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347614
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Vitaly Buka [Mon, 26 Nov 2018 23:17:52 +0000 (23:17 +0000)]
Remove trailing empty line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347613
91177308-0d34-0410-b5e6-
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Vitaly Buka [Mon, 26 Nov 2018 23:16:07 +0000 (23:16 +0000)]
[stack-safety] Analysis documentation
Summary:
Basic documentation of the Stack Safety Analysis.
It will be improved during review and upstream of an implementation.
Reviewers: kcc, eugenis, vlad.tsyrklevich, glider
Reviewed By: vlad.tsyrklevich
Subscribers: arphaman, llvm-commits
Differential Revision: https://reviews.llvm.org/D53336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347612
91177308-0d34-0410-b5e6-
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Vitaly Buka [Mon, 26 Nov 2018 23:05:58 +0000 (23:05 +0000)]
[stack-safety] Inter-Procedural Analysis implementation
Summary:
IPA is implemented as module pass which produce map from Function or Alias to
StackSafetyInfo for a single function.
From prototype by Evgenii Stepanov and Vlad Tsyrklevich.
Reviewers: eugenis, vlad.tsyrklevich, pcc, glider
Subscribers: hiraditya, mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D54543
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347611
91177308-0d34-0410-b5e6-
96231b3b80d8
Vitaly Buka [Mon, 26 Nov 2018 23:05:48 +0000 (23:05 +0000)]
[stack-safety] Empty local passes for Stack Safety Global Analysis
Reviewers: eugenis, vlad.tsyrklevich
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D54541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347610
91177308-0d34-0410-b5e6-
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David Blaikie [Mon, 26 Nov 2018 22:57:18 +0000 (22:57 +0000)]
AArch64ISelLowering: Remove a return-of-assignment to allow NRVO
Patch by Arthur O'Dwyer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347609
91177308-0d34-0410-b5e6-
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Mircea Trofin [Mon, 26 Nov 2018 22:49:17 +0000 (22:49 +0000)]
Add new passes to X86 pipeline tests
Summary: Fixes test failures introduced by rL347596.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D54916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347607
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Fangrui Song [Mon, 26 Nov 2018 22:16:19 +0000 (22:16 +0000)]
[X86] Add dependency from X86 to ProfileData after rL347596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347606
91177308-0d34-0410-b5e6-
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Xin Tong [Mon, 26 Nov 2018 22:03:52 +0000 (22:03 +0000)]
[ICP] Remove incompatible attributes at indirect-call promoted callsites.
Summary:
Removing ncompatible attributes at indirect-call promoted callsites, not removing it results in
at least a IR verification error.
Reviewers: davidxl, xur, mssimpso
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D54913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347605
91177308-0d34-0410-b5e6-
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Sanjay Patel [Mon, 26 Nov 2018 22:00:41 +0000 (22:00 +0000)]
[InstCombine] add helper function to reduce code duplication; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347604
91177308-0d34-0410-b5e6-
96231b3b80d8
Vitaly Buka [Mon, 26 Nov 2018 21:57:59 +0000 (21:57 +0000)]
[stack-safety] Local analysis implementation
Summary:
Analysis produces StackSafetyInfo which contains information with how allocas
and parameters were used in functions.
From prototype by Evgenii Stepanov and Vlad Tsyrklevich.
Reviewers: eugenis, vlad.tsyrklevich, pcc, glider
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D54504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347603
91177308-0d34-0410-b5e6-
96231b3b80d8
Vitaly Buka [Mon, 26 Nov 2018 21:57:47 +0000 (21:57 +0000)]
[stack-safety] Empty local passes for Stack Safety Local Analysis
Reviewers: eugenis, vlad.tsyrklevich
Subscribers: mgorny, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D54502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347602
91177308-0d34-0410-b5e6-
96231b3b80d8
Vitaly Buka [Mon, 26 Nov 2018 21:48:55 +0000 (21:48 +0000)]
[cfi] Help sanstats to find binary if they are not at the original location
Summary:
By default sanstats search binaries at the same location where they were when
stats was collected. Sometime you can not print report immediately or you need
to move post-processing to another workstation. To support this use-case when
original binary is missing sanstats will fall-back to directory with sanstats
file.
Reviewers: pcc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347601
91177308-0d34-0410-b5e6-
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Vitaly Buka [Mon, 26 Nov 2018 21:48:45 +0000 (21:48 +0000)]
[cfi] Make sanstats print address of the check
Summary: Help with off-line symbolization or other type debugging.
Reviewers: pcc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53606
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347600
91177308-0d34-0410-b5e6-
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Evandro Menezes [Mon, 26 Nov 2018 21:47:46 +0000 (21:47 +0000)]
[AArch64] Refactor the scheduling predicates (3/3) (NFC)
Refactor the scheduling predicates based on `MCInstPredicate`. In this
case, `AArch64InstrInfo::hasExtendedReg()`.
Differential revision: https://reviews.llvm.org/D54822
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347599
91177308-0d34-0410-b5e6-
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Evandro Menezes [Mon, 26 Nov 2018 21:47:41 +0000 (21:47 +0000)]
[AArch64] Refactor the scheduling predicates (2/3) (NFC)
Refactor the scheduling predicates based on `MCInstPredicate`. In this
case, `AArch64InstrInfo::hasShiftedReg()`.
Differential revision: https://reviews.llvm.org/D54820
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347598
91177308-0d34-0410-b5e6-
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Evandro Menezes [Mon, 26 Nov 2018 21:47:28 +0000 (21:47 +0000)]
[AArch64] Refactor the scheduling predicates (1/3) (NFC)
Refactor the scheduling predicates based on `MCInstPredicate`. In this
case, `AArch64InstrInfo::isScaledAddr()`
Differential revision: https://reviews.llvm.org/D54777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347597
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Mircea Trofin [Mon, 26 Nov 2018 21:36:18 +0000 (21:36 +0000)]
Support for inserting profile-directed cache prefetches
Summary:
Support for profile-driven cache prefetching (X86)
This change is part of a larger system, consisting of a cache prefetches recommender, create_llvm_prof (https://github.com/google/autofdo), and LLVM.
A proof of concept recommender is DynamoRIO's cache miss analyzer. It processes memory access traces obtained from a running binary and identifies patterns in cache misses. Based on them, it produces a csv file with recommendations. The expectation is that, by leveraging such recommendations, we can reduce the amount of clock cycles spent waiting for data from memory. A microbenchmark based on the DynamoRIO analyzer is available as a proof of concept: https://goo.gl/6TM2Xp.
The recommender makes prefetch recommendations in terms of:
* the binary offset of an instruction with a memory operand;
* a delta;
* and a type (nta, t0, t1, t2)
meaning: a prefetch of that type should be inserted right before the instrution at that binary offset, and the prefetch should be for an address delta away from the memory address the instruction will access.
For example:
0x400ab2,64,nta
and assuming the instruction at 0x400ab2 is:
movzbl (%rbx,%rdx,1),%edx
means that the recommender determined it would be beneficial for a prefetchnta instruction to be inserted right before this instruction, as such:
prefetchnta 0x40(%rbx,%rdx,1)
movzbl (%rbx, %rdx, 1), %edx
The workflow for prefetch cache instrumentation is as follows (the proof of concept script details these steps as well):
1. build binary, making sure -gmlt -fdebug-info-for-profiling is passed. The latter option will enable the X86DiscriminateMemOps pass, which ensures instructions with memory operands are uniquely identifiable (this causes ~2% size increase in total binary size due to the additional debug information).
2. collect memory traces, run analysis to obtain recommendations (see above-referenced DynamoRIO demo as a proof of concept).
3. use create_llvm_prof to convert recommendations to reference insertion locations in terms of debug info locations.
4. rebuild binary, using the exact same set of arguments used initially, to which -mllvm -prefetch-hints-file=<file> needs to be added, using the afdo file obtained at step 3.
Note that if sample profiling feedback-driven optimization is also desired, that happens before step 1 above. In this case, the sample profile afdo file that was used to produce the binary at step 1 must also be included in step 4.
The data needed by the compiler in order to identify prefetch insertion points is very similar to what is needed for sample profiles. For this reason, and given that the overall approach (memory tracing-based cache recommendation mechanisms) is under active development, we use the afdo format as a syntax for capturing this information. We avoid confusing semantics with sample profile afdo data by feeding the two types of information to the compiler through separate files and compiler flags. Should the approach prove successful, we can investigate improvements to this encoding mechanism.
Reviewers: davidxl, wmi, craig.topper
Reviewed By: davidxl, wmi, craig.topper
Subscribers: davide, danielcdh, mgorny, aprantl, eraman, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D54052
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347596
91177308-0d34-0410-b5e6-
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Matt Arsenault [Mon, 26 Nov 2018 21:28:40 +0000 (21:28 +0000)]
AMDGPU: Record SGPR spills when restoring too
It's possible in some cases to have a restore present
without a corresponding spill. Due to an apparent bug
in D54366 <https://reviews.llvm.org/D54366>, only the
restore for a register was emitted. It's probably
always a bug for this to happen, but due to how SGPR
spilling is implemented, this makes the issues appear
worse than it is.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347595
91177308-0d34-0410-b5e6-
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Craig Topper [Mon, 26 Nov 2018 21:12:39 +0000 (21:12 +0000)]
[LegalizeVectorTypes][X86][ARM][AArch64][PowerPC] Don't use SplitVecOp_TruncateHelper for FP_TO_SINT/UINT.
SplitVecOp_TruncateHelper tries to promote the result type while splitting FP_TO_SINT/UINT. It then concatenates the result and introduces a truncate to the original result type. But it does this without inserting the AssertZExt/AssertSExt that the regular result type promotion would insert. Nor does it turn FP_TO_UINT into FP_TO_SINT the way normal result type promotion for these operations does. This is bad on X86 which doesn't support FP_TO_SINT until AVX512.
This patch disables the use of SplitVecOp_TruncateHelper for these operations and just lets normal promotion handle it. I've tweaked a couple things in X86ISelLowering to avoid a few obvious regressions there. I believe all the changes on X86 are improvements. The other targets look neutral.
Differential Revision: https://reviews.llvm.org/D54906
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347593
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Teresa Johnson [Mon, 26 Nov 2018 20:40:37 +0000 (20:40 +0000)]
[ThinLTO] Consolidate cache key computation between new/old LTO APIs
Summary:
The old legacy LTO API had a separate cache key computation, which was
a subset of the cache key computation in the new LTO API (from what I
can tell this is largely just because certain features such as CFI,
dsoLocal, etc are only utilized via the new LTO API). However, having
separate computations is unnecessary (much of the code is duplicated),
and can lead to bugs when adding new optimizations if both cache
computation algorithms aren't updated properly - it's much easier to
maintain if we have a single facility.
This patch refactors the old LTO API code to use the cache key
computation from the new LTO API. To do this, we set up an lto::Config
object and fill in the fields that the old LTO was hashing (the others
will just use the defaults).
There are two notable changes:
- I added a Freestanding flag to the LTO Config. Currently this is only
used by the legacy LTO API. In the patch that added it (D30791) I had
asked about adding it to the new LTO API, but it looks like that was not
addressed. This should probably be discussed as a follow up to this
change, as it is orthogonal.
- The legacy LTO API had some code that was hashing the GUID of all
preserved symbols defined in the module. I looked back at the history of
this (which was added with the original hashing in the legacy LTO API in
D18494), and there is a comment in the review thread that it was added
in preparation for future internalization. We now do the internalization
of course, and that is handled in the new LTO API cache key computation
by hashing the recorded linkage type of all defined globals. Therefore I
didn't try to move over and keep the preserved symbols handling.
Reviewers: steven_wu, pcc
Subscribers: mehdi_amini, inglorion, eraman, dexonsmith, dang, llvm-commits
Differential Revision: https://reviews.llvm.org/D54635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347592
91177308-0d34-0410-b5e6-
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Craig Topper [Mon, 26 Nov 2018 20:16:33 +0000 (20:16 +0000)]
[SelectionDAG] Teach BaseIndexOffset::match to unwrap the base after looking through an add/or
We might find a target specific node that needs to be unwrapped after we look through an add/or. Otherwise we get inconsistent results if one pointer is just X86WrapperRIP and the other is (add X86WrapperRIP, C)
Differential Revision: https://reviews.llvm.org/D54818
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347591
91177308-0d34-0410-b5e6-
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Craig Topper [Mon, 26 Nov 2018 20:16:31 +0000 (20:16 +0000)]
[X86] Add test case for D54818
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347590
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Zola Bridges [Mon, 26 Nov 2018 20:11:18 +0000 (20:11 +0000)]
Revert "[clang][slh] add attribute for speculative load hardening"
This reverts commit
801eaf91221ba6dd6996b29ff82659ad6359e885.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347588
91177308-0d34-0410-b5e6-
96231b3b80d8
Zola Bridges [Mon, 26 Nov 2018 19:41:14 +0000 (19:41 +0000)]
[clang][slh] add attribute for speculative load hardening
Summary:
LLVM IR already has an attribute for speculative_load_hardening. Before
this commit, when a user passed the -mspeculative-load-hardening flag to
Clang, every function would have this attribute added to it. This Clang
attribute will allow users to opt into SLH on a function by function basis.
This can be applied to functions and Objective C methods.
Reviewers: chandlerc, echristo
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D54555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347586
91177308-0d34-0410-b5e6-
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Than McIntosh [Mon, 26 Nov 2018 18:43:48 +0000 (18:43 +0000)]
[CodeGen] Support custom format of stack maps
Summary:
Add a hook to the GCMetadataPrinter for emitting stack maps in
custom format. The hook will be called at stack map generation
time. The default stack map format is used if there is no hook.
For this to be useful a few data structures and accessors are
exposed from the StackMaps class, so the custom printer can
access the stack map data.
This patch authored by Cherry Zhang <cherryyz@google.com>.
Reviewers: thanm, apilipenko, reames
Reviewed By: reames
Subscribers: reames, apilipenko, nemanjai, javed.absar, kbarton, jsji, llvm-commits
Differential Revision: https://reviews.llvm.org/D53892
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347584
91177308-0d34-0410-b5e6-
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Erich Keane [Mon, 26 Nov 2018 17:51:27 +0000 (17:51 +0000)]
Delete dead code introduced in r347354.
ParentTy is never used other than an assignment, and since it is a
pointer, there is no side effect. Some versions of GCC notice and warn
on this.
Change-Id: I37dc1a18c7b58040419afb803621de13d8904a8f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347581
91177308-0d34-0410-b5e6-
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Matt Arsenault [Mon, 26 Nov 2018 17:17:07 +0000 (17:17 +0000)]
AMDGPU: Cleanup / relax tests for future changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347576
91177308-0d34-0410-b5e6-
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Matt Arsenault [Mon, 26 Nov 2018 17:02:02 +0000 (17:02 +0000)]
AMDGPU: Don't optimize exec masks at -O0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347573
91177308-0d34-0410-b5e6-
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Matt Arsenault [Mon, 26 Nov 2018 17:02:01 +0000 (17:02 +0000)]
AMDGPU: Only add implicit super-reg def for first subreg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347572
91177308-0d34-0410-b5e6-
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Than McIntosh [Mon, 26 Nov 2018 16:16:09 +0000 (16:16 +0000)]
[CodeGen] Take SPAdj into account for STATEPOINT liveness args
Summary:
STATEPOINT records its args' locations on stack relative to SP.
If the SP is changed, take that into account.
This patch authored by Cherry Zhang <cherryyz@google.com>.
Reviewers: thanm, reames
Reviewed By: reames
Subscribers: reames, llvm-commits
Differential Revision: https://reviews.llvm.org/D53603
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347569
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Aaron Ballman [Mon, 26 Nov 2018 15:54:36 +0000 (15:54 +0000)]
Remove an unnecessary file; NFC.
This source file has not been needed since r346522 and was triggering diagnostics in MSVC about an object file which exports no public symbols (LNK4221).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347565
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Nikita Popov [Mon, 26 Nov 2018 15:36:57 +0000 (15:36 +0000)]
[DemandedBits] Add support for funnel shifts
Add support for funnel shifts to the DemandedBits analysis. The
demanded bits of the first two operands can be determined if the
shift amount is constant. The demanded bits of the third operand
(shift amount) can be determined if the bitwidth is a power of two.
This is basically the same functionality as implemented in D54869
and D54478, but for DemandedBits rather than InstCombine.
Differential Revision: https://reviews.llvm.org/D54876
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347561
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Sanjay Patel [Mon, 26 Nov 2018 15:22:30 +0000 (15:22 +0000)]
[x86] promote all multiply i8 by constant to i32
We have these 2 "isDesirable" promotion hooks (I'm not sure why we need both of them, but that's
independent of this patch), and we can adjust them to promote "mul i8 X, C" to i32. Then, all of
our existing LEA and other multiply expansion magic happens as it would for i32 ops.
Some of the test diffs show that we could end up with an actual 32-bit mul instruction here
because we choose not to expand to simpler ops. That instruction could be slower depending on the
subtarget. On the plus side, this means we don't need a separate instruction to load the constant
operand and possibly an extra instruction to move the result. If we need to tune mul i32 further,
we could add a later transform that tries to shrink it back to i8 based on subtarget timing.
I did not bother to duplicate all of the 32-bit test file RUNs and target settings that exist to
test whether LEA expansion is cheap or not. The diffs here assume a default target, so that means
LEA is generally cheap.
Differential Revision: https://reviews.llvm.org/D54803
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347557
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Diana Picus [Mon, 26 Nov 2018 11:07:02 +0000 (11:07 +0000)]
[ARM GlobalISel] Support G_CTLZ and G_CTLZ_ZERO_UNDEF
We can now select CLZ via the TableGen'erated code, so support G_CTLZ
and G_CTLZ_ZERO_UNDEF throughout the pipeline for types <= s32.
Legalizer:
If the CLZ instruction is available, use it for both G_CTLZ and
G_CTLZ_ZERO_UNDEF. Otherwise, use a libcall for G_CTLZ_ZERO_UNDEF and
lower G_CTLZ in terms of it.
In order to achieve this we need to add support to the LegalizerHelper
for the legalization of G_CTLZ_ZERO_UNDEF for s32 as a libcall (__clzsi2).
We also need to allow lowering of G_CTLZ in terms of G_CTLZ_ZERO_UNDEF
if that is supported as a libcall, as opposed to just if it is Legal or
Custom. Due to a minor refactoring of the helper function in charge of
this, we will also allow the same behaviour for G_CTTZ and G_CTPOP.
This is not going to be a problem in practice since we don't yet have
support for treating G_CTTZ and G_CTPOP as libcalls (not even in
DAGISel).
Reg bank select:
Map G_CTLZ to GPR. G_CTLZ_ZERO_UNDEF should not make it to this point.
Instruction select:
Nothing to do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347545
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Diana Picus [Mon, 26 Nov 2018 11:06:53 +0000 (11:06 +0000)]
Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347544
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Sam Parker [Mon, 26 Nov 2018 10:22:55 +0000 (10:22 +0000)]
[ARM] Prevent parallel macs for unsigned values
Both zext and sext are currently allowed during the search for narrow
sequences and sexts operands are later added to the mac candidates.
But operands of muls are also added, without checking whether they're
sext or zext, which means we can generate a signed smlad when we
shouldn't.
Differential Revision: https://reviews.llvm.org/D54790
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347542
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Fedor Sergeev [Mon, 26 Nov 2018 10:17:27 +0000 (10:17 +0000)]
Revert "[TTI] Reduction costs only need to include a single extract element cost"
This reverts commit r346970.
It was causing PR39774, a crash in slp-vectorizer on a rather simple loop
with just a bunch of 'and's in the body.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347541
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Kang Zhang [Mon, 26 Nov 2018 07:15:31 +0000 (07:15 +0000)]
Revert "[PowerPC] Fix inconsistent ImmMustBeMultipleOf for same instruction"
This reverts commits r347532. Forget add the option
-mtriple powerpc64-unknown-linux-gnu. So other platform is error except
for PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347534
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Craig Topper [Mon, 26 Nov 2018 06:50:19 +0000 (06:50 +0000)]
[X86] Add test cases to show bad type legalization of fptosi/fptosui v16f32->v16i8 and v8f64->v8i16 on pre-AVX512 targets.
When splitting the v16f32/v8f64 result type, type legalization will try to promote the integer result type before a concat and an explicit truncate. But for the fptoui test case this is particularly bad since fptoui isn't supported on X86 until AVX512. We could use an fptosi since the result range would fit in a signed 32-bit value, but the generic type legalization doesn't do that transformation when splitting. It does do this when promoting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347533
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Kang Zhang [Mon, 26 Nov 2018 06:03:25 +0000 (06:03 +0000)]
[PowerPC] Fix inconsistent ImmMustBeMultipleOf for same instruction
Summary:
There are 4 instructions which have Inconsistent ImmMustBeMultipleOf in the
function PPCInstrInfo::instrHasImmForm, they are LFS, LFD, STFS, STFD.
These four instructions should set the ImmMustBeMultipleOf to 1 instead of 4.
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D54738
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347532
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Argyrios Kyrtzidis [Mon, 26 Nov 2018 00:03:39 +0000 (00:03 +0000)]
[Support/FileSystem] Add sub-second precision for atime/mtime of sys::fs::file_status on unix platforms
Summary:
getLastAccessedTime() and getLastModificationTime() provided times in nanoseconds but with only 1 second resolution, even when the underlying file system could provide more precise times than that.
These changes add sub-second precision for unix platforms that support improved precision.
Also add some comments to make sure people are aware that the resolution of times can vary across different file systems.
Reviewers: labath, zturner, aaron.ballman, kristina
Reviewed By: aaron.ballman, kristina
Subscribers: lebedev.ri, mgorny, kristina, llvm-commits
Differential Revision: https://reviews.llvm.org/D54826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347530
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Florian Hahn [Sun, 25 Nov 2018 19:38:02 +0000 (19:38 +0000)]
[MetadataTest] Fix off-by-one strncpy warning reported by gcc8. (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347528
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Sanjay Patel [Sun, 25 Nov 2018 17:27:02 +0000 (17:27 +0000)]
[x86] limit transform for select-of-fp-constants
This should likely be adjusted to limit this transform
further, but these diffs should be clear wins.
If we have blendv/conditional move, then we should assume
those are cheap ops. The loads become independent of the
compare, so those can be speculated before we need to use
the values in the blend/mov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347526
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Sanjay Patel [Sun, 25 Nov 2018 16:54:43 +0000 (16:54 +0000)]
[x86] add tests for select-of-fp-constants; NFC
There are many options here depending on subtarget,
but we are uniformly relying on a transform that was
driven by performance for a 32-bit SSE2 target in 2009.
Note: The same motivation was apparently used to do this
transform for *all* targets, so non-x86 may want to look
at this too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347525
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Florian Hahn [Sun, 25 Nov 2018 16:32:02 +0000 (16:32 +0000)]
[IPSCCP] Use input operand instead of OriginalOp for ssa_copy.
OriginalOp of a Predicate refers to the original IR value,
before renaming. While solving in IPSCCP, we have to use
the operand of the ssa_copy instead, to avoid missing
updates for nested conditions on the same IR value.
Fixes PR39772.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347524
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Sanjay Patel [Sun, 25 Nov 2018 16:09:32 +0000 (16:09 +0000)]
[SelectionDAG] move constant or splat functions to common location
rL347502 moved the null sibling, so we should group all of these
together. I'm not sure why these aren't methods of the SDValue
class itself, but that's another patch if that's possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347523
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